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-rw-r--r--arch/sh/kernel/timers/timer-mtu2.c202
1 files changed, 0 insertions, 202 deletions
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
deleted file mode 100644
index 9b0ef0126479..000000000000
--- a/arch/sh/kernel/timers/timer-mtu2.c
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1/*
2 * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
3 *
4 * Copyright (C) 2005 Paul Mundt
5 *
6 * Based off of arch/sh/kernel/timers/timer-tmu.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/seqlock.h>
16#include <asm/timer.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/clock.h>
20
21/*
22 * We use channel 1 for our lowly system timer. Channel 2 would be the other
23 * likely candidate, but we leave it alone as it has higher divisors that
24 * would be of more use to other more interesting applications.
25 *
26 * TODO: Presently we only implement a 16-bit single-channel system timer.
27 * However, we can implement channel cascade if we go the overflow route and
28 * get away with using 2 MTU2 channels as a 32-bit timer.
29 */
30#define MTU2_TSTR 0xfffe4280
31#define MTU2_TCR_1 0xfffe4380
32#define MTU2_TMDR_1 0xfffe4381
33#define MTU2_TIOR_1 0xfffe4382
34#define MTU2_TIER_1 0xfffe4384
35#define MTU2_TSR_1 0xfffe4385
36#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
37
38#if defined(CONFIG_CPU_SUBTYPE_SH7201) || \
39 defined(CONFIG_CPU_SUBTYPE_SH7203)
40#define MTU2_TGRA_1 0xfffe4388
41#else
42#define MTU2_TGRA_1 0xfffe438a
43#endif
44
45#define STBCR3 0xfffe0408
46
47#define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
48
49#define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
50
51#define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
52
53#define MTU2_TCR_INIT 0x22
54
55#define MTU2_TCR_CALIB 0x00
56
57static unsigned long mtu2_timer_get_offset(void)
58{
59 int count;
60 static int count_p = 0x7fff; /* for the first call after boot */
61 static unsigned long jiffies_p = 0;
62
63 /*
64 * cache volatile jiffies temporarily; we have IRQs turned off.
65 */
66 unsigned long jiffies_t;
67
68 /* timer count may underflow right here */
69 count = ctrl_inw(MTU2_TCNT_1); /* read the latched count */
70
71 jiffies_t = jiffies;
72
73 /*
74 * avoiding timer inconsistencies (they are rare, but they happen)...
75 * there is one kind of problem that must be avoided here:
76 * 1. the timer counter underflows
77 */
78
79 if (jiffies_t == jiffies_p) {
80 if (count > count_p) {
81 if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
82 count -= LATCH;
83 } else {
84 printk("%s (): hardware timer problem?\n",
85 __func__);
86 }
87 }
88 } else
89 jiffies_p = jiffies_t;
90
91 count_p = count;
92
93 count = ((LATCH-1) - count) * TICK_SIZE;
94 count = (count + LATCH/2) / LATCH;
95
96 return count;
97}
98
99static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
100{
101 unsigned long timer_status;
102
103 /* Clear TGFA bit */
104 timer_status = ctrl_inb(MTU2_TSR_1);
105 timer_status &= ~MTU2_TSR_TGFA;
106 ctrl_outb(timer_status, MTU2_TSR_1);
107
108 /* Do timer tick */
109 handle_timer_tick();
110
111 return IRQ_HANDLED;
112}
113
114static struct irqaction mtu2_irq = {
115 .name = "timer",
116 .handler = mtu2_timer_interrupt,
117 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
118};
119
120static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
121
122static void mtu2_clk_init(struct clk *clk)
123{
124 u8 idx = MTU2_TCR_INIT & 0x7;
125
126 clk->rate = clk->parent->rate / divisors[idx];
127 /* Start TCNT counting */
128 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
129
130}
131
132static void mtu2_clk_recalc(struct clk *clk)
133{
134 u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
135 clk->rate = clk->parent->rate / divisors[idx];
136}
137
138static struct clk_ops mtu2_clk_ops = {
139 .init = mtu2_clk_init,
140 .recalc = mtu2_clk_recalc,
141};
142
143static struct clk mtu2_clk1 = {
144 .name = "mtu2_clk1",
145 .ops = &mtu2_clk_ops,
146};
147
148static int mtu2_timer_start(void)
149{
150 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
151 return 0;
152}
153
154static int mtu2_timer_stop(void)
155{
156 ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
157 return 0;
158}
159
160static int mtu2_timer_init(void)
161{
162 unsigned long interval;
163
164 setup_irq(CONFIG_SH_TIMER_IRQ, &mtu2_irq);
165
166 mtu2_clk1.parent = clk_get(NULL, "module_clk");
167
168 ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
169
170 /* Normal operation */
171 ctrl_outb(0, MTU2_TMDR_1);
172 ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
173 ctrl_outb(0x01, MTU2_TIOR_1);
174
175 /* Enable underflow interrupt */
176 ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
177
178 interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
179 printk(KERN_INFO "Interval = %ld\n", interval);
180
181 ctrl_outw(interval, MTU2_TGRA_1);
182 ctrl_outw(0, MTU2_TCNT_1);
183
184 clk_register(&mtu2_clk1);
185 clk_enable(&mtu2_clk1);
186
187 return 0;
188}
189
190struct sys_timer_ops mtu2_timer_ops = {
191 .init = mtu2_timer_init,
192 .start = mtu2_timer_start,
193 .stop = mtu2_timer_stop,
194#ifndef CONFIG_GENERIC_TIME
195 .get_offset = mtu2_timer_get_offset,
196#endif
197};
198
199struct sys_timer mtu2_timer = {
200 .name = "mtu2",
201 .ops = &mtu2_timer_ops,
202};
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