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-rw-r--r--arch/sh/kernel/cpu/clock.c63
-rw-r--r--arch/sh/kernel/cpu/irq/imask.c64
-rw-r--r--arch/sh/kernel/cpu/irq/intc-sh5.c36
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c8
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c84
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c111
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c115
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c154
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c187
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c108
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c108
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c108
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c270
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c164
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c187
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c140
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c112
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c2230
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c116
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c113
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c117
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c216
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c757
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c204
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c546
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c204
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c204
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c393
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c209
-rw-r--r--arch/sh/kernel/cpu/sh5/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c2
-rw-r--r--arch/sh/kernel/cpu/sh5/entry.S65
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c195
35 files changed, 7385 insertions, 217 deletions
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 1dc896483b59..f54769f455b1 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -19,7 +19,6 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/mutex.h> 20#include <linux/mutex.h>
21#include <linux/list.h> 21#include <linux/list.h>
22#include <linux/kref.h>
23#include <linux/kobject.h> 22#include <linux/kobject.h>
24#include <linux/sysdev.h> 23#include <linux/sysdev.h>
25#include <linux/seq_file.h> 24#include <linux/seq_file.h>
@@ -27,7 +26,6 @@
27#include <linux/platform_device.h> 26#include <linux/platform_device.h>
28#include <linux/proc_fs.h> 27#include <linux/proc_fs.h>
29#include <asm/clock.h> 28#include <asm/clock.h>
30#include <asm/timer.h>
31 29
32static LIST_HEAD(clock_list); 30static LIST_HEAD(clock_list);
33static DEFINE_SPINLOCK(clock_lock); 31static DEFINE_SPINLOCK(clock_lock);
@@ -90,7 +88,7 @@ static void propagate_rate(struct clk *clk)
90 } 88 }
91} 89}
92 90
93static int __clk_enable(struct clk *clk) 91static void __clk_init(struct clk *clk)
94{ 92{
95 /* 93 /*
96 * See if this is the first time we're enabling the clock, some 94 * See if this is the first time we're enabling the clock, some
@@ -99,17 +97,34 @@ static int __clk_enable(struct clk *clk)
99 * changes and the clock needs to hunt for the proper set of 97 * changes and the clock needs to hunt for the proper set of
100 * divisors to use before it can effectively recalc. 98 * divisors to use before it can effectively recalc.
101 */ 99 */
102 if (unlikely(atomic_read(&clk->kref.refcount) == 1)) 100
101 if (clk->flags & CLK_NEEDS_INIT) {
103 if (clk->ops && clk->ops->init) 102 if (clk->ops && clk->ops->init)
104 clk->ops->init(clk); 103 clk->ops->init(clk);
105 104
106 kref_get(&clk->kref); 105 clk->flags &= ~CLK_NEEDS_INIT;
106 }
107}
108
109static int __clk_enable(struct clk *clk)
110{
111 if (!clk)
112 return -EINVAL;
107 113
114 clk->usecount++;
115
116 /* nothing to do if always enabled */
108 if (clk->flags & CLK_ALWAYS_ENABLED) 117 if (clk->flags & CLK_ALWAYS_ENABLED)
109 return 0; 118 return 0;
110 119
111 if (likely(clk->ops && clk->ops->enable)) 120 if (clk->usecount == 1) {
112 clk->ops->enable(clk); 121 __clk_init(clk);
122
123 __clk_enable(clk->parent);
124
125 if (clk->ops && clk->ops->enable)
126 clk->ops->enable(clk);
127 }
113 128
114 return 0; 129 return 0;
115} 130}
@@ -119,11 +134,6 @@ int clk_enable(struct clk *clk)
119 unsigned long flags; 134 unsigned long flags;
120 int ret; 135 int ret;
121 136
122 if (!clk)
123 return -EINVAL;
124
125 clk_enable(clk->parent);
126
127 spin_lock_irqsave(&clock_lock, flags); 137 spin_lock_irqsave(&clock_lock, flags);
128 ret = __clk_enable(clk); 138 ret = __clk_enable(clk);
129 spin_unlock_irqrestore(&clock_lock, flags); 139 spin_unlock_irqrestore(&clock_lock, flags);
@@ -132,21 +142,23 @@ int clk_enable(struct clk *clk)
132} 142}
133EXPORT_SYMBOL_GPL(clk_enable); 143EXPORT_SYMBOL_GPL(clk_enable);
134 144
135static void clk_kref_release(struct kref *kref)
136{
137 /* Nothing to do */
138}
139
140static void __clk_disable(struct clk *clk) 145static void __clk_disable(struct clk *clk)
141{ 146{
142 int count = kref_put(&clk->kref, clk_kref_release); 147 if (!clk)
148 return;
149
150 clk->usecount--;
151
152 WARN_ON(clk->usecount < 0);
143 153
144 if (clk->flags & CLK_ALWAYS_ENABLED) 154 if (clk->flags & CLK_ALWAYS_ENABLED)
145 return; 155 return;
146 156
147 if (!count) { /* count reaches zero, disable the clock */ 157 if (clk->usecount == 0) {
148 if (likely(clk->ops && clk->ops->disable)) 158 if (likely(clk->ops && clk->ops->disable))
149 clk->ops->disable(clk); 159 clk->ops->disable(clk);
160
161 __clk_disable(clk->parent);
150 } 162 }
151} 163}
152 164
@@ -154,14 +166,9 @@ void clk_disable(struct clk *clk)
154{ 166{
155 unsigned long flags; 167 unsigned long flags;
156 168
157 if (!clk)
158 return;
159
160 spin_lock_irqsave(&clock_lock, flags); 169 spin_lock_irqsave(&clock_lock, flags);
161 __clk_disable(clk); 170 __clk_disable(clk);
162 spin_unlock_irqrestore(&clock_lock, flags); 171 spin_unlock_irqrestore(&clock_lock, flags);
163
164 clk_disable(clk->parent);
165} 172}
166EXPORT_SYMBOL_GPL(clk_disable); 173EXPORT_SYMBOL_GPL(clk_disable);
167 174
@@ -170,14 +177,14 @@ int clk_register(struct clk *clk)
170 mutex_lock(&clock_list_sem); 177 mutex_lock(&clock_list_sem);
171 178
172 list_add(&clk->node, &clock_list); 179 list_add(&clk->node, &clock_list);
173 kref_init(&clk->kref); 180 clk->usecount = 0;
181 clk->flags |= CLK_NEEDS_INIT;
174 182
175 mutex_unlock(&clock_list_sem); 183 mutex_unlock(&clock_list_sem);
176 184
177 if (clk->flags & CLK_ALWAYS_ENABLED) { 185 if (clk->flags & CLK_ALWAYS_ENABLED) {
186 __clk_init(clk);
178 pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name); 187 pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
179 if (clk->ops && clk->ops->init)
180 clk->ops->init(clk);
181 if (clk->ops && clk->ops->enable) 188 if (clk->ops && clk->ops->enable)
182 clk->ops->enable(clk); 189 clk->ops->enable(clk);
183 pr_debug( "Enabled."); 190 pr_debug( "Enabled.");
@@ -353,7 +360,7 @@ static int show_clocks(char *buf, char **start, off_t off,
353 p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name, 360 p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
354 rate / 1000000, (rate % 1000000) / 10000, 361 rate / 1000000, (rate % 1000000) / 10000,
355 ((clk->flags & CLK_ALWAYS_ENABLED) || 362 ((clk->flags & CLK_ALWAYS_ENABLED) ||
356 (atomic_read(&clk->kref.refcount) != 1)) ? 363 clk->usecount > 0) ?
357 "enabled" : "disabled"); 364 "enabled" : "disabled");
358 } 365 }
359 366
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 301b505c4278..3bef3c2629ad 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -18,38 +18,17 @@
18#include <linux/spinlock.h> 18#include <linux/spinlock.h>
19#include <linux/cache.h> 19#include <linux/cache.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/bitmap.h>
21#include <asm/system.h> 22#include <asm/system.h>
22#include <asm/irq.h> 23#include <asm/irq.h>
23 24
24/* Bitmap of IRQ masked */ 25/* Bitmap of IRQ masked */
25static unsigned long imask_mask = 0x7fff;
26static int interrupt_priority = 0;
27
28static void enable_imask_irq(unsigned int irq);
29static void disable_imask_irq(unsigned int irq);
30static void shutdown_imask_irq(unsigned int irq);
31static void mask_and_ack_imask(unsigned int);
32static void end_imask_irq(unsigned int irq);
33
34#define IMASK_PRIORITY 15 26#define IMASK_PRIORITY 15
35 27
36static unsigned int startup_imask_irq(unsigned int irq) 28static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
37{ 29static int interrupt_priority;
38 /* Nothing to do */
39 return 0; /* never anything pending */
40}
41 30
42static struct hw_interrupt_type imask_irq_type = { 31static inline void set_interrupt_registers(int ip)
43 .typename = "SR.IMASK",
44 .startup = startup_imask_irq,
45 .shutdown = shutdown_imask_irq,
46 .enable = enable_imask_irq,
47 .disable = disable_imask_irq,
48 .ack = mask_and_ack_imask,
49 .end = end_imask_irq
50};
51
52void static inline set_interrupt_registers(int ip)
53{ 32{
54 unsigned long __dummy; 33 unsigned long __dummy;
55 34
@@ -72,42 +51,31 @@ void static inline set_interrupt_registers(int ip)
72 : "t"); 51 : "t");
73} 52}
74 53
75static void disable_imask_irq(unsigned int irq) 54static void mask_imask_irq(unsigned int irq)
76{ 55{
77 clear_bit(irq, &imask_mask); 56 clear_bit(irq, &imask_mask);
78 if (interrupt_priority < IMASK_PRIORITY - irq) 57 if (interrupt_priority < IMASK_PRIORITY - irq)
79 interrupt_priority = IMASK_PRIORITY - irq; 58 interrupt_priority = IMASK_PRIORITY - irq;
80
81 set_interrupt_registers(interrupt_priority); 59 set_interrupt_registers(interrupt_priority);
82} 60}
83 61
84static void enable_imask_irq(unsigned int irq) 62static void unmask_imask_irq(unsigned int irq)
85{ 63{
86 set_bit(irq, &imask_mask); 64 set_bit(irq, &imask_mask);
87 interrupt_priority = IMASK_PRIORITY - ffz(imask_mask); 65 interrupt_priority = IMASK_PRIORITY -
88 66 find_first_zero_bit(imask_mask, IMASK_PRIORITY);
89 set_interrupt_registers(interrupt_priority); 67 set_interrupt_registers(interrupt_priority);
90} 68}
91 69
92static void mask_and_ack_imask(unsigned int irq) 70static struct irq_chip imask_irq_chip = {
93{ 71 .typename = "SR.IMASK",
94 disable_imask_irq(irq); 72 .mask = mask_imask_irq,
95} 73 .unmask = unmask_imask_irq,
96 74 .mask_ack = mask_imask_irq,
97static void end_imask_irq(unsigned int irq) 75};
98{
99 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
100 enable_imask_irq(irq);
101}
102
103static void shutdown_imask_irq(unsigned int irq)
104{
105 /* Nothing to do */
106}
107 76
108void make_imask_irq(unsigned int irq) 77void make_imask_irq(unsigned int irq)
109{ 78{
110 disable_irq_nosync(irq); 79 set_irq_chip_and_handler_name(irq, &imask_irq_chip,
111 irq_desc[irq].chip = &imask_irq_type; 80 handle_level_irq, "level");
112 enable_irq(irq);
113} 81}
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 726f0335da76..6c092f1f5557 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -84,7 +84,7 @@ static void disable_intc_irq(unsigned int irq);
84static void mask_and_ack_intc(unsigned int); 84static void mask_and_ack_intc(unsigned int);
85static void end_intc_irq(unsigned int irq); 85static void end_intc_irq(unsigned int irq);
86 86
87static struct hw_interrupt_type intc_irq_type = { 87static struct irq_chip intc_irq_type = {
88 .typename = "INTC", 88 .typename = "INTC",
89 .startup = startup_intc_irq, 89 .startup = startup_intc_irq,
90 .shutdown = shutdown_intc_irq, 90 .shutdown = shutdown_intc_irq,
@@ -152,43 +152,13 @@ static void end_intc_irq(unsigned int irq)
152 enable_intc_irq(irq); 152 enable_intc_irq(irq);
153} 153}
154 154
155/* For future use, if we ever support IRLM=0) */
156void make_intc_irq(unsigned int irq)
157{
158 disable_irq_nosync(irq);
159 irq_desc[irq].chip = &intc_irq_type;
160 disable_intc_irq(irq);
161}
162
163#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
164static int IRQ_to_vectorN[NR_INTC_IRQS] = {
165 0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /* 0- 7 */
166 -1, -1, -1, -1, 0x50, 0x51, 0x52, 0x53, /* 8-15 */
167 0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36, -1, /* 16-23 */
168 -1, -1, -1, -1, -1, -1, -1, -1, /* 24-31 */
169 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
170 0x39, 0x3A, 0x3B, -1, -1, -1, -1, -1, /* 40-47 */
171 -1, -1, -1, -1, -1, -1, -1, -1, /* 48-55 */
172 -1, -1, -1, -1, -1, -1, -1, 0x2B, /* 56-63 */
173
174};
175
176int intc_irq_describe(char* p, int irq)
177{
178 if (irq < NR_INTC_IRQS)
179 return sprintf(p, "(0x%3x)", IRQ_to_vectorN[irq]*0x20);
180 else
181 return 0;
182}
183#endif
184
185void __init plat_irq_setup(void) 155void __init plat_irq_setup(void)
186{ 156{
187 unsigned long long __dummy0, __dummy1=~0x00000000100000f0; 157 unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
188 unsigned long reg; 158 unsigned long reg;
189 int i; 159 int i;
190 160
191 intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); 161 intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
192 if (!intc_virt) { 162 if (!intc_virt) {
193 panic("Unable to remap INTC\n"); 163 panic("Unable to remap INTC\n");
194 } 164 }
@@ -196,7 +166,7 @@ void __init plat_irq_setup(void)
196 166
197 /* Set default: per-line enable/disable, priority driven ack/eoi */ 167 /* Set default: per-line enable/disable, priority driven ack/eoi */
198 for (i = 0; i < NR_INTC_IRQS; i++) 168 for (i = 0; i < NR_INTC_IRQS; i++)
199 irq_desc[i].chip = &intc_irq_type; 169 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
200 170
201 171
202 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ 172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 3eb17ee5540e..fa0c8467a280 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -59,10 +59,18 @@ void register_ipr_controller(struct ipr_desc *desc)
59 59
60 for (i = 0; i < desc->nr_irqs; i++) { 60 for (i = 0; i < desc->nr_irqs; i++) {
61 struct ipr_data *p = desc->ipr_data + i; 61 struct ipr_data *p = desc->ipr_data + i;
62 struct irq_desc *irq_desc;
62 63
63 BUG_ON(p->ipr_idx >= desc->nr_offsets); 64 BUG_ON(p->ipr_idx >= desc->nr_offsets);
64 BUG_ON(!desc->ipr_offsets[p->ipr_idx]); 65 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
65 66
67 irq_desc = irq_to_desc_alloc_cpu(p->irq, smp_processor_id());
68 if (unlikely(!irq_desc)) {
69 printk(KERN_INFO "can not get irq_desc for %d\n",
70 p->irq);
71 continue;
72 }
73
66 disable_irq_nosync(p->irq); 74 disable_irq_nosync(p->irq);
67 set_irq_chip_and_handler_name(p->irq, &desc->chip, 75 set_irq_chip_and_handler_name(p->irq, &desc->chip,
68 handle_level_irq, "level"); 76 handle_level_irq, "level");
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 0e32d8e448ca..94ac27fc2237 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
15 17
16enum { 18enum {
17 UNUSED = 0, 19 UNUSED = 0,
@@ -109,9 +111,75 @@ static struct platform_device eth_device = {
109 .resource = eth_resources, 111 .resource = eth_resources,
110}; 112};
111 113
114static struct sh_timer_config cmt0_platform_data = {
115 .name = "CMT0",
116 .channel_offset = 0x02,
117 .timer_bit = 0,
118 .clk = "module_clk",
119 .clockevent_rating = 125,
120 .clocksource_rating = 0, /* disabled due to code generation issues */
121};
122
123static struct resource cmt0_resources[] = {
124 [0] = {
125 .name = "CMT0",
126 .start = 0xf84a0072,
127 .end = 0xf84a0077,
128 .flags = IORESOURCE_MEM,
129 },
130 [1] = {
131 .start = 86,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136static struct platform_device cmt0_device = {
137 .name = "sh_cmt",
138 .id = 0,
139 .dev = {
140 .platform_data = &cmt0_platform_data,
141 },
142 .resource = cmt0_resources,
143 .num_resources = ARRAY_SIZE(cmt0_resources),
144};
145
146static struct sh_timer_config cmt1_platform_data = {
147 .name = "CMT1",
148 .channel_offset = 0x08,
149 .timer_bit = 1,
150 .clk = "module_clk",
151 .clockevent_rating = 125,
152 .clocksource_rating = 0, /* disabled due to code generation issues */
153};
154
155static struct resource cmt1_resources[] = {
156 [0] = {
157 .name = "CMT1",
158 .start = 0xf84a0078,
159 .end = 0xf84a007d,
160 .flags = IORESOURCE_MEM,
161 },
162 [1] = {
163 .start = 87,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device cmt1_device = {
169 .name = "sh_cmt",
170 .id = 1,
171 .dev = {
172 .platform_data = &cmt1_platform_data,
173 },
174 .resource = cmt1_resources,
175 .num_resources = ARRAY_SIZE(cmt1_resources),
176};
177
112static struct platform_device *sh7619_devices[] __initdata = { 178static struct platform_device *sh7619_devices[] __initdata = {
113 &sci_device, 179 &sci_device,
114 &eth_device, 180 &eth_device,
181 &cmt0_device,
182 &cmt1_device,
115}; 183};
116 184
117static int __init sh7619_devices_setup(void) 185static int __init sh7619_devices_setup(void)
@@ -125,3 +193,19 @@ void __init plat_irq_setup(void)
125{ 193{
126 register_intc_controller(&intc_desc); 194 register_intc_controller(&intc_desc);
127} 195}
196
197static struct platform_device *sh7619_early_devices[] __initdata = {
198 &cmt0_device,
199 &cmt1_device,
200};
201
202#define STBCR3 0xf80a0000
203
204void __init plat_early_device_setup(void)
205{
206 /* enable CMT clock */
207 __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
208
209 early_platform_add_devices(sh7619_early_devices,
210 ARRAY_SIZE(sh7619_early_devices));
211}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 844293723cfc..a452d9649069 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
14 15
15enum { 16enum {
16 UNUSED = 0, 17 UNUSED = 0,
@@ -24,7 +25,7 @@ enum {
24 25
25 SCIF0, SCIF1, 26 SCIF0, SCIF1,
26 27
27 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5 28 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
28 MTU2_TGI3B, MTU2_TGI3C, 29 MTU2_TGI3B, MTU2_TGI3C,
29 30
30 /* interrupt groups */ 31 /* interrupt groups */
@@ -113,6 +114,99 @@ static struct intc_mask_reg mask_registers[] __initdata = {
113static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups, 114static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
114 mask_registers, prio_registers, NULL); 115 mask_registers, prio_registers, NULL);
115 116
117static struct sh_timer_config mtu2_0_platform_data = {
118 .name = "MTU2_0",
119 .channel_offset = -0x80,
120 .timer_bit = 0,
121 .clk = "module_clk",
122 .clockevent_rating = 200,
123};
124
125static struct resource mtu2_0_resources[] = {
126 [0] = {
127 .name = "MTU2_0",
128 .start = 0xff801300,
129 .end = 0xff801326,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = 228,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device mtu2_0_device = {
139 .name = "sh_mtu2",
140 .id = 0,
141 .dev = {
142 .platform_data = &mtu2_0_platform_data,
143 },
144 .resource = mtu2_0_resources,
145 .num_resources = ARRAY_SIZE(mtu2_0_resources),
146};
147
148static struct sh_timer_config mtu2_1_platform_data = {
149 .name = "MTU2_1",
150 .channel_offset = -0x100,
151 .timer_bit = 1,
152 .clk = "module_clk",
153 .clockevent_rating = 200,
154};
155
156static struct resource mtu2_1_resources[] = {
157 [0] = {
158 .name = "MTU2_1",
159 .start = 0xff801380,
160 .end = 0xff801390,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 234,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device mtu2_1_device = {
170 .name = "sh_mtu2",
171 .id = 1,
172 .dev = {
173 .platform_data = &mtu2_1_platform_data,
174 },
175 .resource = mtu2_1_resources,
176 .num_resources = ARRAY_SIZE(mtu2_1_resources),
177};
178
179static struct sh_timer_config mtu2_2_platform_data = {
180 .name = "MTU2_2",
181 .channel_offset = 0x80,
182 .timer_bit = 2,
183 .clk = "module_clk",
184 .clockevent_rating = 200,
185};
186
187static struct resource mtu2_2_resources[] = {
188 [0] = {
189 .name = "MTU2_2",
190 .start = 0xff801000,
191 .end = 0xff80100a,
192 .flags = IORESOURCE_MEM,
193 },
194 [1] = {
195 .start = 240,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device mtu2_2_device = {
201 .name = "sh_mtu2",
202 .id = 2,
203 .dev = {
204 .platform_data = &mtu2_2_platform_data,
205 },
206 .resource = mtu2_2_resources,
207 .num_resources = ARRAY_SIZE(mtu2_2_resources),
208};
209
116static struct plat_sci_port sci_platform_data[] = { 210static struct plat_sci_port sci_platform_data[] = {
117 { 211 {
118 .mapbase = 0xff804000, 212 .mapbase = 0xff804000,
@@ -134,6 +228,9 @@ static struct platform_device sci_device = {
134 228
135static struct platform_device *mxg_devices[] __initdata = { 229static struct platform_device *mxg_devices[] __initdata = {
136 &sci_device, 230 &sci_device,
231 &mtu2_0_device,
232 &mtu2_1_device,
233 &mtu2_2_device,
137}; 234};
138 235
139static int __init mxg_devices_setup(void) 236static int __init mxg_devices_setup(void)
@@ -147,3 +244,15 @@ void __init plat_irq_setup(void)
147{ 244{
148 register_intc_controller(&intc_desc); 245 register_intc_controller(&intc_desc);
149} 246}
247
248static struct platform_device *mxg_early_devices[] __initdata = {
249 &mtu2_0_device,
250 &mtu2_1_device,
251 &mtu2_2_device,
252};
253
254void __init plat_early_device_setup(void)
255{
256 early_platform_add_devices(mxg_early_devices,
257 ARRAY_SIZE(mxg_early_devices));
258}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 00f42f9e3f5c..772358b7685e 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
15 17
16enum { 18enum {
17 UNUSED = 0, 19 UNUSED = 0,
@@ -249,9 +251,105 @@ static struct platform_device rtc_device = {
249 .resource = rtc_resources, 251 .resource = rtc_resources,
250}; 252};
251 253
254static struct sh_timer_config mtu2_0_platform_data = {
255 .name = "MTU2_0",
256 .channel_offset = -0x80,
257 .timer_bit = 0,
258 .clk = "module_clk",
259 .clockevent_rating = 200,
260};
261
262static struct resource mtu2_0_resources[] = {
263 [0] = {
264 .name = "MTU2_0",
265 .start = 0xfffe4300,
266 .end = 0xfffe4326,
267 .flags = IORESOURCE_MEM,
268 },
269 [1] = {
270 .start = 108,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device mtu2_0_device = {
276 .name = "sh_mtu2",
277 .id = 0,
278 .dev = {
279 .platform_data = &mtu2_0_platform_data,
280 },
281 .resource = mtu2_0_resources,
282 .num_resources = ARRAY_SIZE(mtu2_0_resources),
283};
284
285static struct sh_timer_config mtu2_1_platform_data = {
286 .name = "MTU2_1",
287 .channel_offset = -0x100,
288 .timer_bit = 1,
289 .clk = "module_clk",
290 .clockevent_rating = 200,
291};
292
293static struct resource mtu2_1_resources[] = {
294 [0] = {
295 .name = "MTU2_1",
296 .start = 0xfffe4380,
297 .end = 0xfffe4390,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = 116,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device mtu2_1_device = {
307 .name = "sh_mtu2",
308 .id = 1,
309 .dev = {
310 .platform_data = &mtu2_1_platform_data,
311 },
312 .resource = mtu2_1_resources,
313 .num_resources = ARRAY_SIZE(mtu2_1_resources),
314};
315
316static struct sh_timer_config mtu2_2_platform_data = {
317 .name = "MTU2_2",
318 .channel_offset = 0x80,
319 .timer_bit = 2,
320 .clk = "module_clk",
321 .clockevent_rating = 200,
322};
323
324static struct resource mtu2_2_resources[] = {
325 [0] = {
326 .name = "MTU2_2",
327 .start = 0xfffe4000,
328 .end = 0xfffe400a,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 .start = 124,
333 .flags = IORESOURCE_IRQ,
334 },
335};
336
337static struct platform_device mtu2_2_device = {
338 .name = "sh_mtu2",
339 .id = 2,
340 .dev = {
341 .platform_data = &mtu2_2_platform_data,
342 },
343 .resource = mtu2_2_resources,
344 .num_resources = ARRAY_SIZE(mtu2_2_resources),
345};
346
252static struct platform_device *sh7201_devices[] __initdata = { 347static struct platform_device *sh7201_devices[] __initdata = {
253 &sci_device, 348 &sci_device,
254 &rtc_device, 349 &rtc_device,
350 &mtu2_0_device,
351 &mtu2_1_device,
352 &mtu2_2_device,
255}; 353};
256 354
257static int __init sh7201_devices_setup(void) 355static int __init sh7201_devices_setup(void)
@@ -265,3 +363,20 @@ void __init plat_irq_setup(void)
265{ 363{
266 register_intc_controller(&intc_desc); 364 register_intc_controller(&intc_desc);
267} 365}
366
367static struct platform_device *sh7201_early_devices[] __initdata = {
368 &mtu2_0_device,
369 &mtu2_1_device,
370 &mtu2_2_device,
371};
372
373#define STBCR3 0xfffe0408
374
375void __init plat_early_device_setup(void)
376{
377 /* enable MTU2 clock */
378 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
379
380 early_platform_add_devices(sh7201_early_devices,
381 ARRAY_SIZE(sh7201_early_devices));
382}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 820dfb2e8656..d7493418ba60 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -11,6 +11,8 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
15#include <linux/io.h>
14 16
15enum { 17enum {
16 UNUSED = 0, 18 UNUSED = 0,
@@ -205,6 +207,132 @@ static struct platform_device sci_device = {
205 }, 207 },
206}; 208};
207 209
210static struct sh_timer_config cmt0_platform_data = {
211 .name = "CMT0",
212 .channel_offset = 0x02,
213 .timer_bit = 0,
214 .clk = "module_clk",
215 .clockevent_rating = 125,
216 .clocksource_rating = 0, /* disabled due to code generation issues */
217};
218
219static struct resource cmt0_resources[] = {
220 [0] = {
221 .name = "CMT0",
222 .start = 0xfffec002,
223 .end = 0xfffec007,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = 142,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device cmt0_device = {
233 .name = "sh_cmt",
234 .id = 0,
235 .dev = {
236 .platform_data = &cmt0_platform_data,
237 },
238 .resource = cmt0_resources,
239 .num_resources = ARRAY_SIZE(cmt0_resources),
240};
241
242static struct sh_timer_config cmt1_platform_data = {
243 .name = "CMT1",
244 .channel_offset = 0x08,
245 .timer_bit = 1,
246 .clk = "module_clk",
247 .clockevent_rating = 125,
248 .clocksource_rating = 0, /* disabled due to code generation issues */
249};
250
251static struct resource cmt1_resources[] = {
252 [0] = {
253 .name = "CMT1",
254 .start = 0xfffec008,
255 .end = 0xfffec00d,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = 143,
260 .flags = IORESOURCE_IRQ,
261 },
262};
263
264static struct platform_device cmt1_device = {
265 .name = "sh_cmt",
266 .id = 1,
267 .dev = {
268 .platform_data = &cmt1_platform_data,
269 },
270 .resource = cmt1_resources,
271 .num_resources = ARRAY_SIZE(cmt1_resources),
272};
273
274static struct sh_timer_config mtu2_0_platform_data = {
275 .name = "MTU2_0",
276 .channel_offset = -0x80,
277 .timer_bit = 0,
278 .clk = "module_clk",
279 .clockevent_rating = 200,
280};
281
282static struct resource mtu2_0_resources[] = {
283 [0] = {
284 .name = "MTU2_0",
285 .start = 0xfffe4300,
286 .end = 0xfffe4326,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = 146,
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device mtu2_0_device = {
296 .name = "sh_mtu2",
297 .id = 0,
298 .dev = {
299 .platform_data = &mtu2_0_platform_data,
300 },
301 .resource = mtu2_0_resources,
302 .num_resources = ARRAY_SIZE(mtu2_0_resources),
303};
304
305static struct sh_timer_config mtu2_1_platform_data = {
306 .name = "MTU2_1",
307 .channel_offset = -0x100,
308 .timer_bit = 1,
309 .clk = "module_clk",
310 .clockevent_rating = 200,
311};
312
313static struct resource mtu2_1_resources[] = {
314 [0] = {
315 .name = "MTU2_1",
316 .start = 0xfffe4380,
317 .end = 0xfffe4390,
318 .flags = IORESOURCE_MEM,
319 },
320 [1] = {
321 .start = 153,
322 .flags = IORESOURCE_IRQ,
323 },
324};
325
326static struct platform_device mtu2_1_device = {
327 .name = "sh_mtu2",
328 .id = 1,
329 .dev = {
330 .platform_data = &mtu2_1_platform_data,
331 },
332 .resource = mtu2_1_resources,
333 .num_resources = ARRAY_SIZE(mtu2_1_resources),
334};
335
208static struct resource rtc_resources[] = { 336static struct resource rtc_resources[] = {
209 [0] = { 337 [0] = {
210 .start = 0xffff2000, 338 .start = 0xffff2000,
@@ -227,6 +355,10 @@ static struct platform_device rtc_device = {
227 355
228static struct platform_device *sh7203_devices[] __initdata = { 356static struct platform_device *sh7203_devices[] __initdata = {
229 &sci_device, 357 &sci_device,
358 &cmt0_device,
359 &cmt1_device,
360 &mtu2_0_device,
361 &mtu2_1_device,
230 &rtc_device, 362 &rtc_device,
231}; 363};
232 364
@@ -241,3 +373,25 @@ void __init plat_irq_setup(void)
241{ 373{
242 register_intc_controller(&intc_desc); 374 register_intc_controller(&intc_desc);
243} 375}
376
377static struct platform_device *sh7203_early_devices[] __initdata = {
378 &cmt0_device,
379 &cmt1_device,
380 &mtu2_0_device,
381 &mtu2_1_device,
382};
383
384#define STBCR3 0xfffe0408
385#define STBCR4 0xfffe040c
386
387void __init plat_early_device_setup(void)
388{
389 /* enable CMT clock */
390 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
391
392 /* enable MTU2 clock */
393 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
394
395 early_platform_add_devices(sh7203_early_devices,
396 ARRAY_SIZE(sh7203_early_devices));
397}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index c46a8355726d..2fc6bff5c5fb 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
15 17
16enum { 18enum {
17 UNUSED = 0, 19 UNUSED = 0,
@@ -165,8 +167,170 @@ static struct platform_device sci_device = {
165 }, 167 },
166}; 168};
167 169
170static struct sh_timer_config cmt0_platform_data = {
171 .name = "CMT0",
172 .channel_offset = 0x02,
173 .timer_bit = 0,
174 .clk = "module_clk",
175 .clockevent_rating = 125,
176 .clocksource_rating = 0, /* disabled due to code generation issues */
177};
178
179static struct resource cmt0_resources[] = {
180 [0] = {
181 .name = "CMT0",
182 .start = 0xfffec002,
183 .end = 0xfffec007,
184 .flags = IORESOURCE_MEM,
185 },
186 [1] = {
187 .start = 140,
188 .flags = IORESOURCE_IRQ,
189 },
190};
191
192static struct platform_device cmt0_device = {
193 .name = "sh_cmt",
194 .id = 0,
195 .dev = {
196 .platform_data = &cmt0_platform_data,
197 },
198 .resource = cmt0_resources,
199 .num_resources = ARRAY_SIZE(cmt0_resources),
200};
201
202static struct sh_timer_config cmt1_platform_data = {
203 .name = "CMT1",
204 .channel_offset = 0x08,
205 .timer_bit = 1,
206 .clk = "module_clk",
207 .clockevent_rating = 125,
208 .clocksource_rating = 0, /* disabled due to code generation issues */
209};
210
211static struct resource cmt1_resources[] = {
212 [0] = {
213 .name = "CMT1",
214 .start = 0xfffec008,
215 .end = 0xfffec00d,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = 144,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device cmt1_device = {
225 .name = "sh_cmt",
226 .id = 1,
227 .dev = {
228 .platform_data = &cmt1_platform_data,
229 },
230 .resource = cmt1_resources,
231 .num_resources = ARRAY_SIZE(cmt1_resources),
232};
233
234static struct sh_timer_config mtu2_0_platform_data = {
235 .name = "MTU2_0",
236 .channel_offset = -0x80,
237 .timer_bit = 0,
238 .clk = "module_clk",
239 .clockevent_rating = 200,
240};
241
242static struct resource mtu2_0_resources[] = {
243 [0] = {
244 .name = "MTU2_0",
245 .start = 0xfffe4300,
246 .end = 0xfffe4326,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = 156,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device mtu2_0_device = {
256 .name = "sh_mtu2",
257 .id = 0,
258 .dev = {
259 .platform_data = &mtu2_0_platform_data,
260 },
261 .resource = mtu2_0_resources,
262 .num_resources = ARRAY_SIZE(mtu2_0_resources),
263};
264
265static struct sh_timer_config mtu2_1_platform_data = {
266 .name = "MTU2_1",
267 .channel_offset = -0x100,
268 .timer_bit = 1,
269 .clk = "module_clk",
270 .clockevent_rating = 200,
271};
272
273static struct resource mtu2_1_resources[] = {
274 [0] = {
275 .name = "MTU2_1",
276 .start = 0xfffe4380,
277 .end = 0xfffe4390,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = 164,
282 .flags = IORESOURCE_IRQ,
283 },
284};
285
286static struct platform_device mtu2_1_device = {
287 .name = "sh_mtu2",
288 .id = 1,
289 .dev = {
290 .platform_data = &mtu2_1_platform_data,
291 },
292 .resource = mtu2_1_resources,
293 .num_resources = ARRAY_SIZE(mtu2_1_resources),
294};
295
296static struct sh_timer_config mtu2_2_platform_data = {
297 .name = "MTU2_2",
298 .channel_offset = 0x80,
299 .timer_bit = 2,
300 .clk = "module_clk",
301 .clockevent_rating = 200,
302};
303
304static struct resource mtu2_2_resources[] = {
305 [0] = {
306 .name = "MTU2_2",
307 .start = 0xfffe4000,
308 .end = 0xfffe400a,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = 180,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct platform_device mtu2_2_device = {
318 .name = "sh_mtu2",
319 .id = 2,
320 .dev = {
321 .platform_data = &mtu2_2_platform_data,
322 },
323 .resource = mtu2_2_resources,
324 .num_resources = ARRAY_SIZE(mtu2_2_resources),
325};
326
168static struct platform_device *sh7206_devices[] __initdata = { 327static struct platform_device *sh7206_devices[] __initdata = {
169 &sci_device, 328 &sci_device,
329 &cmt0_device,
330 &cmt1_device,
331 &mtu2_0_device,
332 &mtu2_1_device,
333 &mtu2_2_device,
170}; 334};
171 335
172static int __init sh7206_devices_setup(void) 336static int __init sh7206_devices_setup(void)
@@ -180,3 +344,26 @@ void __init plat_irq_setup(void)
180{ 344{
181 register_intc_controller(&intc_desc); 345 register_intc_controller(&intc_desc);
182} 346}
347
348static struct platform_device *sh7206_early_devices[] __initdata = {
349 &cmt0_device,
350 &cmt1_device,
351 &mtu2_0_device,
352 &mtu2_1_device,
353 &mtu2_2_device,
354};
355
356#define STBCR3 0xfffe0408
357#define STBCR4 0xfffe040c
358
359void __init plat_early_device_setup(void)
360{
361 /* enable CMT clock */
362 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
363
364 /* enable MTU2 clock */
365 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
366
367 early_platform_add_devices(sh7206_early_devices,
368 ARRAY_SIZE(sh7206_early_devices));
369}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 63b67badd67e..39513664d5d7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h>
16#include <asm/rtc.h> 17#include <asm/rtc.h>
17 18
18enum { 19enum {
@@ -116,7 +117,102 @@ static struct platform_device rtc_device = {
116 }, 117 },
117}; 118};
118 119
120static struct sh_timer_config tmu0_platform_data = {
121 .name = "TMU0",
122 .channel_offset = 0x02,
123 .timer_bit = 0,
124 .clk = "module_clk",
125 .clockevent_rating = 200,
126};
127
128static struct resource tmu0_resources[] = {
129 [0] = {
130 .name = "TMU0",
131 .start = 0xfffffe94,
132 .end = 0xfffffe9f,
133 .flags = IORESOURCE_MEM,
134 },
135 [1] = {
136 .start = 16,
137 .flags = IORESOURCE_IRQ,
138 },
139};
140
141static struct platform_device tmu0_device = {
142 .name = "sh_tmu",
143 .id = 0,
144 .dev = {
145 .platform_data = &tmu0_platform_data,
146 },
147 .resource = tmu0_resources,
148 .num_resources = ARRAY_SIZE(tmu0_resources),
149};
150
151static struct sh_timer_config tmu1_platform_data = {
152 .name = "TMU1",
153 .channel_offset = 0xe,
154 .timer_bit = 1,
155 .clk = "module_clk",
156 .clocksource_rating = 200,
157};
158
159static struct resource tmu1_resources[] = {
160 [0] = {
161 .name = "TMU1",
162 .start = 0xfffffea0,
163 .end = 0xfffffeab,
164 .flags = IORESOURCE_MEM,
165 },
166 [1] = {
167 .start = 17,
168 .flags = IORESOURCE_IRQ,
169 },
170};
171
172static struct platform_device tmu1_device = {
173 .name = "sh_tmu",
174 .id = 1,
175 .dev = {
176 .platform_data = &tmu1_platform_data,
177 },
178 .resource = tmu1_resources,
179 .num_resources = ARRAY_SIZE(tmu1_resources),
180};
181
182static struct sh_timer_config tmu2_platform_data = {
183 .name = "TMU2",
184 .channel_offset = 0x1a,
185 .timer_bit = 2,
186 .clk = "module_clk",
187};
188
189static struct resource tmu2_resources[] = {
190 [0] = {
191 .name = "TMU2",
192 .start = 0xfffffeac,
193 .end = 0xfffffebb,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = {
197 .start = 18,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device tmu2_device = {
203 .name = "sh_tmu",
204 .id = 2,
205 .dev = {
206 .platform_data = &tmu2_platform_data,
207 },
208 .resource = tmu2_resources,
209 .num_resources = ARRAY_SIZE(tmu2_resources),
210};
211
119static struct platform_device *sh7705_devices[] __initdata = { 212static struct platform_device *sh7705_devices[] __initdata = {
213 &tmu0_device,
214 &tmu1_device,
215 &tmu2_device,
120 &sci_device, 216 &sci_device,
121 &rtc_device, 217 &rtc_device,
122}; 218};
@@ -128,6 +224,18 @@ static int __init sh7705_devices_setup(void)
128} 224}
129__initcall(sh7705_devices_setup); 225__initcall(sh7705_devices_setup);
130 226
227static struct platform_device *sh7705_early_devices[] __initdata = {
228 &tmu0_device,
229 &tmu1_device,
230 &tmu2_device,
231};
232
233void __init plat_early_device_setup(void)
234{
235 early_platform_add_devices(sh7705_early_devices,
236 ARRAY_SIZE(sh7705_early_devices));
237}
238
131void __init plat_irq_setup(void) 239void __init plat_irq_setup(void)
132{ 240{
133 register_intc_controller(&intc_desc); 241 register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index a74f960b5e79..9412d915b84e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -18,6 +18,7 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/serial.h> 19#include <linux/serial.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h>
21 22
22enum { 23enum {
23 UNUSED = 0, 24 UNUSED = 0,
@@ -144,7 +145,102 @@ static struct platform_device sci_device = {
144 }, 145 },
145}; 146};
146 147
148static struct sh_timer_config tmu0_platform_data = {
149 .name = "TMU0",
150 .channel_offset = 0x02,
151 .timer_bit = 0,
152 .clk = "module_clk",
153 .clockevent_rating = 200,
154};
155
156static struct resource tmu0_resources[] = {
157 [0] = {
158 .name = "TMU0",
159 .start = 0xfffffe94,
160 .end = 0xfffffe9f,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 16,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device tmu0_device = {
170 .name = "sh_tmu",
171 .id = 0,
172 .dev = {
173 .platform_data = &tmu0_platform_data,
174 },
175 .resource = tmu0_resources,
176 .num_resources = ARRAY_SIZE(tmu0_resources),
177};
178
179static struct sh_timer_config tmu1_platform_data = {
180 .name = "TMU1",
181 .channel_offset = 0xe,
182 .timer_bit = 1,
183 .clk = "module_clk",
184 .clocksource_rating = 200,
185};
186
187static struct resource tmu1_resources[] = {
188 [0] = {
189 .name = "TMU1",
190 .start = 0xfffffea0,
191 .end = 0xfffffeab,
192 .flags = IORESOURCE_MEM,
193 },
194 [1] = {
195 .start = 17,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device tmu1_device = {
201 .name = "sh_tmu",
202 .id = 1,
203 .dev = {
204 .platform_data = &tmu1_platform_data,
205 },
206 .resource = tmu1_resources,
207 .num_resources = ARRAY_SIZE(tmu1_resources),
208};
209
210static struct sh_timer_config tmu2_platform_data = {
211 .name = "TMU2",
212 .channel_offset = 0x1a,
213 .timer_bit = 2,
214 .clk = "module_clk",
215};
216
217static struct resource tmu2_resources[] = {
218 [0] = {
219 .name = "TMU2",
220 .start = 0xfffffeac,
221 .end = 0xfffffebb,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 .start = 18,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230static struct platform_device tmu2_device = {
231 .name = "sh_tmu",
232 .id = 2,
233 .dev = {
234 .platform_data = &tmu2_platform_data,
235 },
236 .resource = tmu2_resources,
237 .num_resources = ARRAY_SIZE(tmu2_resources),
238};
239
147static struct platform_device *sh770x_devices[] __initdata = { 240static struct platform_device *sh770x_devices[] __initdata = {
241 &tmu0_device,
242 &tmu1_device,
243 &tmu2_device,
148 &sci_device, 244 &sci_device,
149 &rtc_device, 245 &rtc_device,
150}; 246};
@@ -156,6 +252,18 @@ static int __init sh770x_devices_setup(void)
156} 252}
157__initcall(sh770x_devices_setup); 253__initcall(sh770x_devices_setup);
158 254
255static struct platform_device *sh770x_early_devices[] __initdata = {
256 &tmu0_device,
257 &tmu1_device,
258 &tmu2_device,
259};
260
261void __init plat_early_device_setup(void)
262{
263 early_platform_add_devices(sh770x_early_devices,
264 ARRAY_SIZE(sh770x_early_devices));
265}
266
159void __init plat_irq_setup(void) 267void __init plat_irq_setup(void)
160{ 268{
161 register_intc_controller(&intc_desc); 269 register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 335098b66e2f..07ff38d055a7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h>
16#include <asm/rtc.h> 17#include <asm/rtc.h>
17 18
18enum { 19enum {
@@ -120,7 +121,102 @@ static struct platform_device sci_device = {
120 }, 121 },
121}; 122};
122 123
124static struct sh_timer_config tmu0_platform_data = {
125 .name = "TMU0",
126 .channel_offset = 0x02,
127 .timer_bit = 0,
128 .clk = "module_clk",
129 .clockevent_rating = 200,
130};
131
132static struct resource tmu0_resources[] = {
133 [0] = {
134 .name = "TMU0",
135 .start = 0xa412fe94,
136 .end = 0xa412fe9f,
137 .flags = IORESOURCE_MEM,
138 },
139 [1] = {
140 .start = 16,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static struct platform_device tmu0_device = {
146 .name = "sh_tmu",
147 .id = 0,
148 .dev = {
149 .platform_data = &tmu0_platform_data,
150 },
151 .resource = tmu0_resources,
152 .num_resources = ARRAY_SIZE(tmu0_resources),
153};
154
155static struct sh_timer_config tmu1_platform_data = {
156 .name = "TMU1",
157 .channel_offset = 0xe,
158 .timer_bit = 1,
159 .clk = "module_clk",
160 .clocksource_rating = 200,
161};
162
163static struct resource tmu1_resources[] = {
164 [0] = {
165 .name = "TMU1",
166 .start = 0xa412fea0,
167 .end = 0xa412feab,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = 17,
172 .flags = IORESOURCE_IRQ,
173 },
174};
175
176static struct platform_device tmu1_device = {
177 .name = "sh_tmu",
178 .id = 1,
179 .dev = {
180 .platform_data = &tmu1_platform_data,
181 },
182 .resource = tmu1_resources,
183 .num_resources = ARRAY_SIZE(tmu1_resources),
184};
185
186static struct sh_timer_config tmu2_platform_data = {
187 .name = "TMU2",
188 .channel_offset = 0x1a,
189 .timer_bit = 2,
190 .clk = "module_clk",
191};
192
193static struct resource tmu2_resources[] = {
194 [0] = {
195 .name = "TMU2",
196 .start = 0xa412feac,
197 .end = 0xa412feb5,
198 .flags = IORESOURCE_MEM,
199 },
200 [1] = {
201 .start = 18,
202 .flags = IORESOURCE_IRQ,
203 },
204};
205
206static struct platform_device tmu2_device = {
207 .name = "sh_tmu",
208 .id = 2,
209 .dev = {
210 .platform_data = &tmu2_platform_data,
211 },
212 .resource = tmu2_resources,
213 .num_resources = ARRAY_SIZE(tmu2_resources),
214};
215
123static struct platform_device *sh7710_devices[] __initdata = { 216static struct platform_device *sh7710_devices[] __initdata = {
217 &tmu0_device,
218 &tmu1_device,
219 &tmu2_device,
124 &sci_device, 220 &sci_device,
125 &rtc_device, 221 &rtc_device,
126}; 222};
@@ -132,6 +228,18 @@ static int __init sh7710_devices_setup(void)
132} 228}
133__initcall(sh7710_devices_setup); 229__initcall(sh7710_devices_setup);
134 230
231static struct platform_device *sh7710_early_devices[] __initdata = {
232 &tmu0_device,
233 &tmu1_device,
234 &tmu2_device,
235};
236
237void __init plat_early_device_setup(void)
238{
239 early_platform_add_devices(sh7710_early_devices,
240 ARRAY_SIZE(sh7710_early_devices));
241}
242
135void __init plat_irq_setup(void) 243void __init plat_irq_setup(void)
136{ 244{
137 register_intc_controller(&intc_desc); 245 register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 003874a2fd2a..d8b46f5dff60 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -18,6 +18,7 @@
18#include <linux/serial.h> 18#include <linux/serial.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h>
21#include <asm/rtc.h> 22#include <asm/rtc.h>
22 23
23static struct resource rtc_resources[] = { 24static struct resource rtc_resources[] = {
@@ -123,7 +124,259 @@ static struct platform_device usbf_device = {
123 .resource = usbf_resources, 124 .resource = usbf_resources,
124}; 125};
125 126
127static struct sh_timer_config cmt0_platform_data = {
128 .name = "CMT0",
129 .channel_offset = 0x10,
130 .timer_bit = 0,
131 .clk = "module_clk",
132 .clockevent_rating = 125,
133 .clocksource_rating = 125,
134};
135
136static struct resource cmt0_resources[] = {
137 [0] = {
138 .name = "CMT0",
139 .start = 0x044a0010,
140 .end = 0x044a001b,
141 .flags = IORESOURCE_MEM,
142 },
143 [1] = {
144 .start = 104,
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct platform_device cmt0_device = {
150 .name = "sh_cmt",
151 .id = 0,
152 .dev = {
153 .platform_data = &cmt0_platform_data,
154 },
155 .resource = cmt0_resources,
156 .num_resources = ARRAY_SIZE(cmt0_resources),
157};
158
159static struct sh_timer_config cmt1_platform_data = {
160 .name = "CMT1",
161 .channel_offset = 0x20,
162 .timer_bit = 1,
163 .clk = "module_clk",
164};
165
166static struct resource cmt1_resources[] = {
167 [0] = {
168 .name = "CMT1",
169 .start = 0x044a0020,
170 .end = 0x044a002b,
171 .flags = IORESOURCE_MEM,
172 },
173 [1] = {
174 .start = 104,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179static struct platform_device cmt1_device = {
180 .name = "sh_cmt",
181 .id = 1,
182 .dev = {
183 .platform_data = &cmt1_platform_data,
184 },
185 .resource = cmt1_resources,
186 .num_resources = ARRAY_SIZE(cmt1_resources),
187};
188
189static struct sh_timer_config cmt2_platform_data = {
190 .name = "CMT2",
191 .channel_offset = 0x30,
192 .timer_bit = 2,
193 .clk = "module_clk",
194};
195
196static struct resource cmt2_resources[] = {
197 [0] = {
198 .name = "CMT2",
199 .start = 0x044a0030,
200 .end = 0x044a003b,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = 104,
205 .flags = IORESOURCE_IRQ,
206 },
207};
208
209static struct platform_device cmt2_device = {
210 .name = "sh_cmt",
211 .id = 2,
212 .dev = {
213 .platform_data = &cmt2_platform_data,
214 },
215 .resource = cmt2_resources,
216 .num_resources = ARRAY_SIZE(cmt2_resources),
217};
218
219static struct sh_timer_config cmt3_platform_data = {
220 .name = "CMT3",
221 .channel_offset = 0x40,
222 .timer_bit = 3,
223 .clk = "module_clk",
224};
225
226static struct resource cmt3_resources[] = {
227 [0] = {
228 .name = "CMT3",
229 .start = 0x044a0040,
230 .end = 0x044a004b,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = 104,
235 .flags = IORESOURCE_IRQ,
236 },
237};
238
239static struct platform_device cmt3_device = {
240 .name = "sh_cmt",
241 .id = 3,
242 .dev = {
243 .platform_data = &cmt3_platform_data,
244 },
245 .resource = cmt3_resources,
246 .num_resources = ARRAY_SIZE(cmt3_resources),
247};
248
249static struct sh_timer_config cmt4_platform_data = {
250 .name = "CMT4",
251 .channel_offset = 0x50,
252 .timer_bit = 4,
253 .clk = "module_clk",
254};
255
256static struct resource cmt4_resources[] = {
257 [0] = {
258 .name = "CMT4",
259 .start = 0x044a0050,
260 .end = 0x044a005b,
261 .flags = IORESOURCE_MEM,
262 },
263 [1] = {
264 .start = 104,
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
269static struct platform_device cmt4_device = {
270 .name = "sh_cmt",
271 .id = 4,
272 .dev = {
273 .platform_data = &cmt4_platform_data,
274 },
275 .resource = cmt4_resources,
276 .num_resources = ARRAY_SIZE(cmt4_resources),
277};
278
279static struct sh_timer_config tmu0_platform_data = {
280 .name = "TMU0",
281 .channel_offset = 0x02,
282 .timer_bit = 0,
283 .clk = "module_clk",
284 .clockevent_rating = 200,
285};
286
287static struct resource tmu0_resources[] = {
288 [0] = {
289 .name = "TMU0",
290 .start = 0xa412fe94,
291 .end = 0xa412fe9f,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = 16,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct platform_device tmu0_device = {
301 .name = "sh_tmu",
302 .id = 0,
303 .dev = {
304 .platform_data = &tmu0_platform_data,
305 },
306 .resource = tmu0_resources,
307 .num_resources = ARRAY_SIZE(tmu0_resources),
308};
309
310static struct sh_timer_config tmu1_platform_data = {
311 .name = "TMU1",
312 .channel_offset = 0xe,
313 .timer_bit = 1,
314 .clk = "module_clk",
315 .clocksource_rating = 200,
316};
317
318static struct resource tmu1_resources[] = {
319 [0] = {
320 .name = "TMU1",
321 .start = 0xa412fea0,
322 .end = 0xa412feab,
323 .flags = IORESOURCE_MEM,
324 },
325 [1] = {
326 .start = 17,
327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331static struct platform_device tmu1_device = {
332 .name = "sh_tmu",
333 .id = 1,
334 .dev = {
335 .platform_data = &tmu1_platform_data,
336 },
337 .resource = tmu1_resources,
338 .num_resources = ARRAY_SIZE(tmu1_resources),
339};
340
341static struct sh_timer_config tmu2_platform_data = {
342 .name = "TMU2",
343 .channel_offset = 0x1a,
344 .timer_bit = 2,
345 .clk = "module_clk",
346};
347
348static struct resource tmu2_resources[] = {
349 [0] = {
350 .name = "TMU2",
351 .start = 0xa412feac,
352 .end = 0xa412feb5,
353 .flags = IORESOURCE_MEM,
354 },
355 [1] = {
356 .start = 18,
357 .flags = IORESOURCE_IRQ,
358 },
359};
360
361static struct platform_device tmu2_device = {
362 .name = "sh_tmu",
363 .id = 2,
364 .dev = {
365 .platform_data = &tmu2_platform_data,
366 },
367 .resource = tmu2_resources,
368 .num_resources = ARRAY_SIZE(tmu2_resources),
369};
370
126static struct platform_device *sh7720_devices[] __initdata = { 371static struct platform_device *sh7720_devices[] __initdata = {
372 &cmt0_device,
373 &cmt1_device,
374 &cmt2_device,
375 &cmt3_device,
376 &cmt4_device,
377 &tmu0_device,
378 &tmu1_device,
379 &tmu2_device,
127 &rtc_device, 380 &rtc_device,
128 &sci_device, 381 &sci_device,
129 &usb_ohci_device, 382 &usb_ohci_device,
@@ -137,6 +390,23 @@ static int __init sh7720_devices_setup(void)
137} 390}
138__initcall(sh7720_devices_setup); 391__initcall(sh7720_devices_setup);
139 392
393static struct platform_device *sh7720_early_devices[] __initdata = {
394 &cmt0_device,
395 &cmt1_device,
396 &cmt2_device,
397 &cmt3_device,
398 &cmt4_device,
399 &tmu0_device,
400 &tmu1_device,
401 &tmu2_device,
402};
403
404void __init plat_early_device_setup(void)
405{
406 early_platform_add_devices(sh7720_early_devices,
407 ARRAY_SIZE(sh7720_early_devices));
408}
409
140enum { 410enum {
141 UNUSED = 0, 411 UNUSED = 0,
142 412
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 91e3677ae09d..973ff831c8a8 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -156,6 +156,12 @@ int __init detect_cpu_and_cache_system(void)
156 break; 156 break;
157 } 157 }
158 break; 158 break;
159 case 0x300b:
160 boot_cpu_data.type = CPU_SH7724;
161 boot_cpu_data.icache.ways = 4;
162 boot_cpu_data.dcache.ways = 4;
163 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_FPU;
164 break;
159 case 0x4000: /* 1st cut */ 165 case 0x4000: /* 1st cut */
160 case 0x4001: /* 2nd cut */ 166 case 0x4001: /* 2nd cut */
161 boot_cpu_data.type = CPU_SHX3; 167 boot_cpu_data.type = CPU_SHX3;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 7371abf64f80..be79fa136255 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -2,6 +2,7 @@
2 * SH4-202 Setup 2 * SH4-202 Setup
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2009 Magnus Damm
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -11,6 +12,8 @@
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/serial.h> 13#include <linux/serial.h>
13#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
14 17
15static struct plat_sci_port sci_platform_data[] = { 18static struct plat_sci_port sci_platform_data[] = {
16 { 19 {
@@ -31,8 +34,103 @@ static struct platform_device sci_device = {
31 }, 34 },
32}; 35};
33 36
37static struct sh_timer_config tmu0_platform_data = {
38 .name = "TMU0",
39 .channel_offset = 0x04,
40 .timer_bit = 0,
41 .clk = "module_clk",
42 .clockevent_rating = 200,
43};
44
45static struct resource tmu0_resources[] = {
46 [0] = {
47 .name = "TMU0",
48 .start = 0xffd80008,
49 .end = 0xffd80013,
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .start = 16,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct platform_device tmu0_device = {
59 .name = "sh_tmu",
60 .id = 0,
61 .dev = {
62 .platform_data = &tmu0_platform_data,
63 },
64 .resource = tmu0_resources,
65 .num_resources = ARRAY_SIZE(tmu0_resources),
66};
67
68static struct sh_timer_config tmu1_platform_data = {
69 .name = "TMU1",
70 .channel_offset = 0x10,
71 .timer_bit = 1,
72 .clk = "module_clk",
73 .clocksource_rating = 200,
74};
75
76static struct resource tmu1_resources[] = {
77 [0] = {
78 .name = "TMU1",
79 .start = 0xffd80014,
80 .end = 0xffd8001f,
81 .flags = IORESOURCE_MEM,
82 },
83 [1] = {
84 .start = 17,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct platform_device tmu1_device = {
90 .name = "sh_tmu",
91 .id = 1,
92 .dev = {
93 .platform_data = &tmu1_platform_data,
94 },
95 .resource = tmu1_resources,
96 .num_resources = ARRAY_SIZE(tmu1_resources),
97};
98
99static struct sh_timer_config tmu2_platform_data = {
100 .name = "TMU2",
101 .channel_offset = 0x1c,
102 .timer_bit = 2,
103 .clk = "module_clk",
104};
105
106static struct resource tmu2_resources[] = {
107 [0] = {
108 .name = "TMU2",
109 .start = 0xffd80020,
110 .end = 0xffd8002f,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .start = 18,
115 .flags = IORESOURCE_IRQ,
116 },
117};
118
119static struct platform_device tmu2_device = {
120 .name = "sh_tmu",
121 .id = 2,
122 .dev = {
123 .platform_data = &tmu2_platform_data,
124 },
125 .resource = tmu2_resources,
126 .num_resources = ARRAY_SIZE(tmu2_resources),
127};
128
34static struct platform_device *sh4202_devices[] __initdata = { 129static struct platform_device *sh4202_devices[] __initdata = {
35 &sci_device, 130 &sci_device,
131 &tmu0_device,
132 &tmu1_device,
133 &tmu2_device,
36}; 134};
37 135
38static int __init sh4202_devices_setup(void) 136static int __init sh4202_devices_setup(void)
@@ -42,7 +140,71 @@ static int __init sh4202_devices_setup(void)
42} 140}
43__initcall(sh4202_devices_setup); 141__initcall(sh4202_devices_setup);
44 142
143static struct platform_device *sh4202_early_devices[] __initdata = {
144 &tmu0_device,
145 &tmu1_device,
146 &tmu2_device,
147};
148
149void __init plat_early_device_setup(void)
150{
151 early_platform_add_devices(sh4202_early_devices,
152 ARRAY_SIZE(sh4202_early_devices));
153}
154
155enum {
156 UNUSED = 0,
157
158 /* interrupt sources */
159 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
160 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
161};
162
163static struct intc_vect vectors[] __initdata = {
164 INTC_VECT(HUDI, 0x600),
165 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
166 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
167 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
168 INTC_VECT(RTC, 0x4c0),
169 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
170 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
171 INTC_VECT(WDT, 0x560),
172};
173
174static struct intc_prio_reg prio_registers[] __initdata = {
175 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
176 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
177 { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
178 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
179};
180
181static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
182 NULL, prio_registers, NULL);
183
184static struct intc_vect vectors_irlm[] __initdata = {
185 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
186 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
187};
188
189static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
190 NULL, prio_registers, NULL);
191
45void __init plat_irq_setup(void) 192void __init plat_irq_setup(void)
46{ 193{
47 /* do nothing - all IRL interrupts are handled by the board code */ 194 register_intc_controller(&intc_desc);
195}
196
197#define INTC_ICR 0xffd00000UL
198#define INTC_ICR_IRLM (1<<7)
199
200void __init plat_irq_setup_pins(int mode)
201{
202 switch (mode) {
203 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
204 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
205 register_intc_controller(&intc_desc_irlm);
206 break;
207 default:
208 BUG();
209 }
48} 210}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index a1c80d909cd6..09da0c187d4c 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h>
15#include <linux/serial_sci.h> 16#include <linux/serial_sci.h>
16 17
17static struct resource rtc_resources[] = { 18static struct resource rtc_resources[] = {
@@ -60,9 +61,177 @@ static struct platform_device sci_device = {
60 }, 61 },
61}; 62};
62 63
64static struct sh_timer_config tmu0_platform_data = {
65 .name = "TMU0",
66 .channel_offset = 0x04,
67 .timer_bit = 0,
68 .clk = "module_clk",
69 .clockevent_rating = 200,
70};
71
72static struct resource tmu0_resources[] = {
73 [0] = {
74 .name = "TMU0",
75 .start = 0xffd80008,
76 .end = 0xffd80013,
77 .flags = IORESOURCE_MEM,
78 },
79 [1] = {
80 .start = 16,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct platform_device tmu0_device = {
86 .name = "sh_tmu",
87 .id = 0,
88 .dev = {
89 .platform_data = &tmu0_platform_data,
90 },
91 .resource = tmu0_resources,
92 .num_resources = ARRAY_SIZE(tmu0_resources),
93};
94
95static struct sh_timer_config tmu1_platform_data = {
96 .name = "TMU1",
97 .channel_offset = 0x10,
98 .timer_bit = 1,
99 .clk = "module_clk",
100 .clocksource_rating = 200,
101};
102
103static struct resource tmu1_resources[] = {
104 [0] = {
105 .name = "TMU1",
106 .start = 0xffd80014,
107 .end = 0xffd8001f,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = 17,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device tmu1_device = {
117 .name = "sh_tmu",
118 .id = 1,
119 .dev = {
120 .platform_data = &tmu1_platform_data,
121 },
122 .resource = tmu1_resources,
123 .num_resources = ARRAY_SIZE(tmu1_resources),
124};
125
126static struct sh_timer_config tmu2_platform_data = {
127 .name = "TMU2",
128 .channel_offset = 0x1c,
129 .timer_bit = 2,
130 .clk = "module_clk",
131};
132
133static struct resource tmu2_resources[] = {
134 [0] = {
135 .name = "TMU2",
136 .start = 0xffd80020,
137 .end = 0xffd8002f,
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = 18,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device tmu2_device = {
147 .name = "sh_tmu",
148 .id = 2,
149 .dev = {
150 .platform_data = &tmu2_platform_data,
151 },
152 .resource = tmu2_resources,
153 .num_resources = ARRAY_SIZE(tmu2_resources),
154};
155
156/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
157#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
158 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
159 defined(CONFIG_CPU_SUBTYPE_SH7751R)
160
161static struct sh_timer_config tmu3_platform_data = {
162 .name = "TMU3",
163 .channel_offset = 0x04,
164 .timer_bit = 0,
165 .clk = "module_clk",
166};
167
168static struct resource tmu3_resources[] = {
169 [0] = {
170 .name = "TMU3",
171 .start = 0xfe100008,
172 .end = 0xfe100013,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = {
176 .start = 72,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device tmu3_device = {
182 .name = "sh_tmu",
183 .id = 3,
184 .dev = {
185 .platform_data = &tmu3_platform_data,
186 },
187 .resource = tmu3_resources,
188 .num_resources = ARRAY_SIZE(tmu3_resources),
189};
190
191static struct sh_timer_config tmu4_platform_data = {
192 .name = "TMU4",
193 .channel_offset = 0x10,
194 .timer_bit = 1,
195 .clk = "module_clk",
196};
197
198static struct resource tmu4_resources[] = {
199 [0] = {
200 .name = "TMU4",
201 .start = 0xfe100014,
202 .end = 0xfe10001f,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = 76,
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211static struct platform_device tmu4_device = {
212 .name = "sh_tmu",
213 .id = 4,
214 .dev = {
215 .platform_data = &tmu4_platform_data,
216 },
217 .resource = tmu4_resources,
218 .num_resources = ARRAY_SIZE(tmu4_resources),
219};
220
221#endif
222
63static struct platform_device *sh7750_devices[] __initdata = { 223static struct platform_device *sh7750_devices[] __initdata = {
64 &rtc_device, 224 &rtc_device,
65 &sci_device, 225 &sci_device,
226 &tmu0_device,
227 &tmu1_device,
228 &tmu2_device,
229#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
230 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
231 defined(CONFIG_CPU_SUBTYPE_SH7751R)
232 &tmu3_device,
233 &tmu4_device,
234#endif
66}; 235};
67 236
68static int __init sh7750_devices_setup(void) 237static int __init sh7750_devices_setup(void)
@@ -72,6 +241,24 @@ static int __init sh7750_devices_setup(void)
72} 241}
73__initcall(sh7750_devices_setup); 242__initcall(sh7750_devices_setup);
74 243
244static struct platform_device *sh7750_early_devices[] __initdata = {
245 &tmu0_device,
246 &tmu1_device,
247 &tmu2_device,
248#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
249 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
250 defined(CONFIG_CPU_SUBTYPE_SH7751R)
251 &tmu3_device,
252 &tmu4_device,
253#endif
254};
255
256void __init plat_early_device_setup(void)
257{
258 early_platform_add_devices(sh7750_early_devices,
259 ARRAY_SIZE(sh7750_early_devices));
260}
261
75enum { 262enum {
76 UNUSED = 0, 263 UNUSED = 0,
77 264
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index d9bdc931ac09..cd097335758f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -10,6 +10,7 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/sh_timer.h>
13#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
14#include <linux/io.h> 15#include <linux/io.h>
15 16
@@ -18,10 +19,7 @@ enum {
18 19
19 /* interrupt sources */ 20 /* interrupt sources */
20 IRL0, IRL1, IRL2, IRL3, 21 IRL0, IRL1, IRL2, IRL3,
21 HUDI, GPIOI, 22 HUDI, GPIOI, DMAC,
22 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
23 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
24 DMAC_DMAE,
25 IRQ4, IRQ5, IRQ6, IRQ7, 23 IRQ4, IRQ5, IRQ6, IRQ7,
26 HCAN20, HCAN21, 24 HCAN20, HCAN21,
27 SSI0, SSI1, 25 SSI0, SSI1,
@@ -36,21 +34,20 @@ enum {
36 HSPI, 34 HSPI,
37 MMCIF0, MMCIF1, MMCIF2, MMCIF3, 35 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
38 MFI, ADC, CMT, 36 MFI, ADC, CMT,
39 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 37 TMU0, TMU1, TMU2,
40 WDT, 38 WDT, REF,
41 REF_RCMI, REF_ROVI,
42 39
43 /* interrupt groups */ 40 /* interrupt groups */
44 DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, 41 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
45}; 42};
46 43
47static struct intc_vect vectors[] __initdata = { 44static struct intc_vect vectors[] __initdata = {
48 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 45 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
49 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 46 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
50 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 47 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
51 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 48 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
52 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 49 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
53 INTC_VECT(DMAC_DMAE, 0x6c0), 50 INTC_VECT(DMAC, 0x6c0),
54 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 51 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
55 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 52 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
56 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), 53 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
@@ -74,23 +71,18 @@ static struct intc_vect vectors[] __initdata = {
74 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */ 71 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
75 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0), 72 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
76 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 73 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
77 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 74 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
78 INTC_VECT(WDT, 0x560), 75 INTC_VECT(WDT, 0x560),
79 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 76 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
80}; 77};
81 78
82static struct intc_group groups[] __initdata = { 79static struct intc_group groups[] __initdata = {
83 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
84 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
85 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
86 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2), 80 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
87 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 81 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
88 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 82 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
89 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), 83 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
90 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 84 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
91 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3), 85 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
92 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
93 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
94}; 86};
95 87
96static struct intc_mask_reg mask_registers[] __initdata = { 88static struct intc_mask_reg mask_registers[] __initdata = {
@@ -168,8 +160,104 @@ static struct platform_device sci_device = {
168 }, 160 },
169}; 161};
170 162
163static struct sh_timer_config tmu0_platform_data = {
164 .name = "TMU0",
165 .channel_offset = 0x04,
166 .timer_bit = 0,
167 .clk = "module_clk",
168 .clockevent_rating = 200,
169};
170
171static struct resource tmu0_resources[] = {
172 [0] = {
173 .name = "TMU0",
174 .start = 0xffd80008,
175 .end = 0xffd80013,
176 .flags = IORESOURCE_MEM,
177 },
178 [1] = {
179 .start = 16,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device tmu0_device = {
185 .name = "sh_tmu",
186 .id = 0,
187 .dev = {
188 .platform_data = &tmu0_platform_data,
189 },
190 .resource = tmu0_resources,
191 .num_resources = ARRAY_SIZE(tmu0_resources),
192};
193
194static struct sh_timer_config tmu1_platform_data = {
195 .name = "TMU1",
196 .channel_offset = 0x10,
197 .timer_bit = 1,
198 .clk = "module_clk",
199 .clocksource_rating = 200,
200};
201
202static struct resource tmu1_resources[] = {
203 [0] = {
204 .name = "TMU1",
205 .start = 0xffd80014,
206 .end = 0xffd8001f,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = 17,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device tmu1_device = {
216 .name = "sh_tmu",
217 .id = 1,
218 .dev = {
219 .platform_data = &tmu1_platform_data,
220 },
221 .resource = tmu1_resources,
222 .num_resources = ARRAY_SIZE(tmu1_resources),
223};
224
225static struct sh_timer_config tmu2_platform_data = {
226 .name = "TMU2",
227 .channel_offset = 0x1c,
228 .timer_bit = 2,
229 .clk = "module_clk",
230};
231
232static struct resource tmu2_resources[] = {
233 [0] = {
234 .name = "TMU2",
235 .start = 0xffd80020,
236 .end = 0xffd8002f,
237 .flags = IORESOURCE_MEM,
238 },
239 [1] = {
240 .start = 18,
241 .flags = IORESOURCE_IRQ,
242 },
243};
244
245static struct platform_device tmu2_device = {
246 .name = "sh_tmu",
247 .id = 2,
248 .dev = {
249 .platform_data = &tmu2_platform_data,
250 },
251 .resource = tmu2_resources,
252 .num_resources = ARRAY_SIZE(tmu2_resources),
253};
254
255
171static struct platform_device *sh7760_devices[] __initdata = { 256static struct platform_device *sh7760_devices[] __initdata = {
172 &sci_device, 257 &sci_device,
258 &tmu0_device,
259 &tmu1_device,
260 &tmu2_device,
173}; 261};
174 262
175static int __init sh7760_devices_setup(void) 263static int __init sh7760_devices_setup(void)
@@ -179,6 +267,18 @@ static int __init sh7760_devices_setup(void)
179} 267}
180__initcall(sh7760_devices_setup); 268__initcall(sh7760_devices_setup);
181 269
270static struct platform_device *sh7760_early_devices[] __initdata = {
271 &tmu0_device,
272 &tmu1_device,
273 &tmu2_device,
274};
275
276void __init plat_early_device_setup(void)
277{
278 early_platform_add_devices(sh7760_early_devices,
279 ARRAY_SIZE(sh7760_early_devices));
280}
281
182#define INTC_ICR 0xffd00000UL 282#define INTC_ICR 0xffd00000UL
183#define INTC_ICR_IRLM (1 << 7) 283#define INTC_ICR_IRLM (1 << 7)
184 284
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 1a92361feeb9..afd6fba47849 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
15obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 16obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
16 17
@@ -26,12 +27,14 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7722.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
30clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
31 33
32# Pinmux setup 34# Pinmux setup
33pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 35pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
34pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 36pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
35pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 38pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
37 40
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 0e174af21874..1ccdfc561fef 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -130,6 +130,12 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
130 * is quite simple.. 130 * is quite simple..
131 */ 131 */
132 132
133#if defined(CONFIG_CPU_SUBTYPE_SH7724)
134#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
135#else
136#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
137#endif
138
133/* 139/*
134 * Instead of having two separate multipliers/divisors set, like this: 140 * Instead of having two separate multipliers/divisors set, like this:
135 * 141 *
@@ -139,13 +145,17 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
139 * I created the divisors2 array, which is used to calculate rate like 145 * I created the divisors2 array, which is used to calculate rate like
140 * rate = parent * 2 / divisors2[ divisor ]; 146 * rate = parent * 2 / divisors2[ divisor ];
141*/ 147*/
148#if defined(CONFIG_CPU_SUBTYPE_SH7724)
149static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
150#else
142static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; 151static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
152#endif
143 153
144static void master_clk_recalc(struct clk *clk) 154static void master_clk_recalc(struct clk *clk)
145{ 155{
146 unsigned frqcr = ctrl_inl(FRQCR); 156 unsigned frqcr = ctrl_inl(FRQCR);
147 157
148 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1); 158 clk->rate = CONFIG_SH_PCLK_FREQ * STCPLL(frqcr);
149} 159}
150 160
151static void master_clk_init(struct clk *clk) 161static void master_clk_init(struct clk *clk)
@@ -161,13 +171,30 @@ static void module_clk_recalc(struct clk *clk)
161{ 171{
162 unsigned long frqcr = ctrl_inl(FRQCR); 172 unsigned long frqcr = ctrl_inl(FRQCR);
163 173
164 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1); 174 clk->rate = clk->parent->rate / STCPLL(frqcr);
165} 175}
166 176
177#if defined(CONFIG_CPU_SUBTYPE_SH7724)
178#define MASTERDIVS { 12, 16, 24, 30, 32, 36, 48 }
179#define STCMASK 0x3f
180#define DIVCALC(div) (div/2-1)
181#define FRQCRKICK 0x80000000
182#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
183#define MASTERDIVS { 6, 8, 12, 16 }
184#define STCMASK 0x1f
185#define DIVCALC(div) (div-1)
186#define FRQCRKICK 0x00000000
187#else
188#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
189#define STCMASK 0x1f
190#define DIVCALC(div) (div-1)
191#define FRQCRKICK 0x00000000
192#endif
193
167static int master_clk_setrate(struct clk *clk, unsigned long rate, int id) 194static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
168{ 195{
169 int div = rate / clk->rate; 196 int div = rate / clk->rate;
170 int master_divs[] = { 2, 3, 4, 6, 8, 16 }; 197 int master_divs[] = MASTERDIVS;
171 int index; 198 int index;
172 unsigned long frqcr; 199 unsigned long frqcr;
173 200
@@ -180,8 +207,9 @@ static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
180 div = master_divs[index - 1]; 207 div = master_divs[index - 1];
181 208
182 frqcr = ctrl_inl(FRQCR); 209 frqcr = ctrl_inl(FRQCR);
183 frqcr &= ~(0xF << 24); 210 frqcr &= ~(STCMASK << 24);
184 frqcr |= ( (div-1) << 24); 211 frqcr |= (DIVCALC(div) << 24);
212 frqcr |= FRQCRKICK;
185 ctrl_outl(frqcr, FRQCR); 213 ctrl_outl(frqcr, FRQCR);
186 214
187 return 0; 215 return 0;
@@ -377,6 +405,7 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
377 /* clear FRQCR bits */ 405 /* clear FRQCR bits */
378 frqcr &= ~(ctx.mask << ctx.shift); 406 frqcr &= ~(ctx.mask << ctx.shift);
379 frqcr |= div << ctx.shift; 407 frqcr |= div << ctx.shift;
408 frqcr |= FRQCRKICK;
380 409
381 /* ...and perform actual change */ 410 /* ...and perform actual change */
382 ctrl_outl(frqcr, FRQCR); 411 ctrl_outl(frqcr, FRQCR);
@@ -542,8 +571,8 @@ static struct clk sh7722_r_clock = {
542 .flags = CLK_RATE_PROPAGATES, 571 .flags = CLK_RATE_PROPAGATES,
543}; 572};
544 573
545#ifndef CONFIG_CPU_SUBTYPE_SH7343 574#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
546 575 !defined(CONFIG_CPU_SUBTYPE_SH7724)
547/* 576/*
548 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops 577 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
549 * methods of clk_ops determine which register they should access by 578 * methods of clk_ops determine which register they should access by
@@ -560,15 +589,16 @@ static struct clk sh7722_siu_b_clock = {
560 .arch_flags = SCLKBCR, 589 .arch_flags = SCLKBCR,
561 .ops = &sh7722_siu_clk_ops, 590 .ops = &sh7722_siu_clk_ops,
562}; 591};
592#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */
563 593
564#if defined(CONFIG_CPU_SUBTYPE_SH7722) 594#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\
595 defined(CONFIG_CPU_SUBTYPE_SH7724)
565static struct clk sh7722_irda_clock = { 596static struct clk sh7722_irda_clock = {
566 .name = "irda_clk", 597 .name = "irda_clk",
567 .arch_flags = IrDACLKCR, 598 .arch_flags = IrDACLKCR,
568 .ops = &sh7722_siu_clk_ops, 599 .ops = &sh7722_siu_clk_ops,
569}; 600};
570#endif 601#endif
571#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
572 602
573static struct clk sh7722_video_clock = { 603static struct clk sh7722_video_clock = {
574 .name = "video_clk", 604 .name = "video_clk",
@@ -715,6 +745,61 @@ static struct clk sh7722_mstpcr_clocks[] = {
715 MSTPCR("vpu0", "bus_clk", 2, 1), 745 MSTPCR("vpu0", "bus_clk", 2, 1),
716 MSTPCR("lcdc0", "bus_clk", 2, 0), 746 MSTPCR("lcdc0", "bus_clk", 2, 0),
717#endif 747#endif
748#if defined(CONFIG_CPU_SUBTYPE_SH7724)
749 /* See Datasheet : Overview -> Block Diagram */
750 MSTPCR("tlb0", "cpu_clk", 0, 31),
751 MSTPCR("ic0", "cpu_clk", 0, 30),
752 MSTPCR("oc0", "cpu_clk", 0, 29),
753 MSTPCR("rs0", "bus_clk", 0, 28),
754 MSTPCR("ilmem0", "cpu_clk", 0, 27),
755 MSTPCR("l2c0", "sh_clk", 0, 26),
756 MSTPCR("fpu0", "cpu_clk", 0, 24),
757 MSTPCR("intc0", "peripheral_clk", 0, 22),
758 MSTPCR("dmac0", "bus_clk", 0, 21),
759 MSTPCR("sh0", "sh_clk", 0, 20),
760 MSTPCR("hudi0", "peripheral_clk", 0, 19),
761 MSTPCR("ubc0", "cpu_clk", 0, 17),
762 MSTPCR("tmu0", "peripheral_clk", 0, 15),
763 MSTPCR("cmt0", "r_clk", 0, 14),
764 MSTPCR("rwdt0", "r_clk", 0, 13),
765 MSTPCR("dmac1", "bus_clk", 0, 12),
766 MSTPCR("tmu1", "peripheral_clk", 0, 10),
767 MSTPCR("scif0", "peripheral_clk", 0, 9),
768 MSTPCR("scif1", "peripheral_clk", 0, 8),
769 MSTPCR("scif2", "peripheral_clk", 0, 7),
770 MSTPCR("scif3", "bus_clk", 0, 6),
771 MSTPCR("scif4", "bus_clk", 0, 5),
772 MSTPCR("scif5", "bus_clk", 0, 4),
773 MSTPCR("msiof0", "bus_clk", 0, 2),
774 MSTPCR("msiof1", "bus_clk", 0, 1),
775 MSTPCR("keysc0", "r_clk", 1, 12),
776 MSTPCR("rtc0", "r_clk", 1, 11),
777 MSTPCR("i2c0", "peripheral_clk", 1, 9),
778 MSTPCR("i2c1", "peripheral_clk", 1, 8),
779 MSTPCR("mmc0", "bus_clk", 2, 29),
780 MSTPCR("eth0", "bus_clk", 2, 28),
781 MSTPCR("atapi0", "bus_clk", 2, 26),
782 MSTPCR("tpu0", "bus_clk", 2, 25),
783 MSTPCR("irda0", "peripheral_clk", 2, 24),
784 MSTPCR("tsif0", "bus_clk", 2, 22),
785 MSTPCR("usb1", "bus_clk", 2, 21),
786 MSTPCR("usb0", "bus_clk", 2, 20),
787 MSTPCR("2dg0", "bus_clk", 2, 19),
788 MSTPCR("sdhi0", "bus_clk", 2, 18),
789 MSTPCR("sdhi1", "bus_clk", 2, 17),
790 MSTPCR("veu1", "bus_clk", 2, 15),
791 MSTPCR("ceu1", "bus_clk", 2, 13),
792 MSTPCR("beu1", "bus_clk", 2, 12),
793 MSTPCR("2ddmac0", "sh_clk", 2, 10),
794 MSTPCR("spu0", "bus_clk", 2, 9),
795 MSTPCR("jpu0", "bus_clk", 2, 6),
796 MSTPCR("vou0", "bus_clk", 2, 5),
797 MSTPCR("beu0", "bus_clk", 2, 4),
798 MSTPCR("ceu0", "bus_clk", 2, 3),
799 MSTPCR("veu0", "bus_clk", 2, 2),
800 MSTPCR("vpu0", "bus_clk", 2, 1),
801 MSTPCR("lcdc0", "bus_clk", 2, 0),
802#endif
718#if defined(CONFIG_CPU_SUBTYPE_SH7343) 803#if defined(CONFIG_CPU_SUBTYPE_SH7343)
719 MSTPCR("uram0", "umem_clk", 0, 28), 804 MSTPCR("uram0", "umem_clk", 0, 28),
720 MSTPCR("xymem0", "bus_clk", 0, 26), 805 MSTPCR("xymem0", "bus_clk", 0, 26),
@@ -786,12 +871,15 @@ static struct clk *sh7722_clocks[] = {
786 &sh7722_sh_clock, 871 &sh7722_sh_clock,
787 &sh7722_peripheral_clock, 872 &sh7722_peripheral_clock,
788 &sh7722_sdram_clock, 873 &sh7722_sdram_clock,
789#ifndef CONFIG_CPU_SUBTYPE_SH7343 874#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
875 !defined(CONFIG_CPU_SUBTYPE_SH7724)
790 &sh7722_siu_a_clock, 876 &sh7722_siu_a_clock,
791 &sh7722_siu_b_clock, 877 &sh7722_siu_b_clock,
792#if defined(CONFIG_CPU_SUBTYPE_SH7722)
793 &sh7722_irda_clock,
794#endif 878#endif
879/* 7724 should support FSI clock */
880#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
881 defined(CONFIG_CPU_SUBTYPE_SH7724)
882 &sh7722_irda_clock,
795#endif 883#endif
796 &sh7722_video_clock, 884 &sh7722_video_clock,
797}; 885};
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
new file mode 100644
index 000000000000..1af0f9586379
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -0,0 +1,2230 @@
1/*
2 * SH7724 Pinmux
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Pinmux
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7724.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
26 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
27 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
28 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
29 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
30 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
31 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
32 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
33 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
34 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
35 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
36 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
37 PTG5_DATA, PTG4_DATA,
38 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
39 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA,
42 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
43 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
44 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
45 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
46 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
47 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
48 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
49 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
50 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
51 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
52 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
53 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
54 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
55 PTS6_DATA, PTS5_DATA, PTS4_DATA,
56 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
57 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
58 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
59 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
60 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
61 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
62 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
63 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
64 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
65 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
66 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
67 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
68 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
69 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
70 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
71 PINMUX_DATA_END,
72
73 PINMUX_INPUT_BEGIN,
74 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
75 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
76 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
77 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
78 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
79 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
80 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
81 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
82 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
83 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
84 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
85 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
86 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
87 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
88 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
89 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
90 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
91 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
92 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
93 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
94 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
95 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
96 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
97 PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN,
98 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
99 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
100 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
101 PTS6_IN, PTS5_IN, PTS4_IN,
102 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
103 PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
104 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
105 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
106 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
107 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
108 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
109 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
110 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
111 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
112 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
113 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
114 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
115 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
116 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
117 PINMUX_INPUT_END,
118
119 PINMUX_INPUT_PULLUP_BEGIN,
120 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
121 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
122 PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
123 PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
124 PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
125 PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
126 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
127 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
128 PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
129 PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
130 PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
131 PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
132 PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
133 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
134 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
135 PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
136 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
137 PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
138 PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
139 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
140 PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
141 PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU,
142 PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
143 PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU,
144 PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU,
145 PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
146 PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
147 PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU,
148 PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
149 PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
150 PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
151 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
152 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
153 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
154 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
155 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
156 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
157 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
158 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
159 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
160 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
161 PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
162 PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
163 PINMUX_INPUT_PULLUP_END,
164
165 PINMUX_OUTPUT_BEGIN,
166 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
167 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
168 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
169 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
170 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
171 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
172 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
173 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
174 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
175 PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
176 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
177 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
178 PTG5_OUT, PTG4_OUT,
179 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
180 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
181 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
182 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT,
183 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
184 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
185 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
186 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
187 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
188 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
189 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
190 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
191 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
192 PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
193 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
194 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
195 PTR1_OUT, PTR0_OUT,
196 PTS6_OUT, PTS5_OUT, PTS4_OUT,
197 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
198 PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
199 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
200 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
201 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
202 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
203 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
204 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
205 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
206 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
207 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
208 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
209 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
210 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
211 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
212 PINMUX_OUTPUT_END,
213
214 PINMUX_FUNCTION_BEGIN,
215 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
216 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
217 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
218 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
219 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
220 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
221 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
222 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
223 PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
224 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
225 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
226 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
227 PTG5_FN, PTG4_FN,
228 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
229 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
230 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
231 PTJ7_FN, PTJ6_FN, PTJ5_FN,
232 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
233 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
234 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
235 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
236 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
237 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
238 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
239 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
240 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
241 PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN,
242 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
243 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
244 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
245 PTS6_FN, PTS5_FN, PTS4_FN,
246 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
247 PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
248 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
249 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
250 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
251 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
252 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
253 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
254 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
255 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
256 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
257 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
258 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
259 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
260 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
261
262
263 PSA15_0, PSA15_1,
264 PSA14_0, PSA14_1,
265 PSA13_0, PSA13_1,
266 PSA12_0, PSA12_1,
267 PSA10_0, PSA10_1,
268 PSA9_0, PSA9_1,
269 PSA8_0, PSA8_1,
270 PSA7_0, PSA7_1,
271 PSA6_0, PSA6_1,
272 PSA5_0, PSA5_1,
273 PSA3_0, PSA3_1,
274 PSA2_0, PSA2_1,
275 PSA1_0, PSA1_1,
276 PSA0_0, PSA0_1,
277
278 PSB14_0, PSB14_1,
279 PSB13_0, PSB13_1,
280 PSB12_0, PSB12_1,
281 PSB11_0, PSB11_1,
282 PSB10_0, PSB10_1,
283 PSB9_0, PSB9_1,
284 PSB8_0, PSB8_1,
285 PSB7_0, PSB7_1,
286 PSB6_0, PSB6_1,
287 PSB5_0, PSB5_1,
288 PSB4_0, PSB4_1,
289 PSB3_0, PSB3_1,
290 PSB2_0, PSB2_1,
291 PSB1_0, PSB1_1,
292 PSB0_0, PSB0_1,
293
294 PSC15_0, PSC15_1,
295 PSC14_0, PSC14_1,
296 PSC13_0, PSC13_1,
297 PSC12_0, PSC12_1,
298 PSC11_0, PSC11_1,
299 PSC10_0, PSC10_1,
300 PSC9_0, PSC9_1,
301 PSC8_0, PSC8_1,
302 PSC7_0, PSC7_1,
303 PSC6_0, PSC6_1,
304 PSC5_0, PSC5_1,
305 PSC4_0, PSC4_1,
306 PSC2_0, PSC2_1,
307 PSC1_0, PSC1_1,
308 PSC0_0, PSC0_1,
309
310 PSD15_0, PSD15_1,
311 PSD14_0, PSD14_1,
312 PSD13_0, PSD13_1,
313 PSD12_0, PSD12_1,
314 PSD11_0, PSD11_1,
315 PSD10_0, PSD10_1,
316 PSD9_0, PSD9_1,
317 PSD8_0, PSD8_1,
318 PSD7_0, PSD7_1,
319 PSD6_0, PSD6_1,
320 PSD5_0, PSD5_1,
321 PSD4_0, PSD4_1,
322 PSD3_0, PSD3_1,
323 PSD2_0, PSD2_1,
324 PSD1_0, PSD1_1,
325 PSD0_0, PSD0_1,
326
327 PSE15_0, PSE15_1,
328 PSE14_0, PSE14_1,
329 PSE13_0, PSE13_1,
330 PSE12_0, PSE12_1,
331 PSE11_0, PSE11_1,
332 PSE10_0, PSE10_1,
333 PSE9_0, PSE9_1,
334 PSE8_0, PSE8_1,
335 PSE7_0, PSE7_1,
336 PSE6_0, PSE6_1,
337 PSE5_0, PSE5_1,
338 PSE4_0, PSE4_1,
339 PSE3_0, PSE3_1,
340 PSE2_0, PSE2_1,
341 PSE1_0, PSE1_1,
342 PSE0_0, PSE0_1,
343 PINMUX_FUNCTION_END,
344
345 PINMUX_MARK_BEGIN,
346 /*PTA*/
347 D23_MARK, KEYOUT2_MARK, IDED15_MARK,
348 D22_MARK, KEYOUT1_MARK, IDED14_MARK,
349 D21_MARK, KEYOUT0_MARK, IDED13_MARK,
350 D20_MARK, KEYIN4_MARK, IDED12_MARK,
351 D19_MARK, KEYIN3_MARK, IDED11_MARK,
352 D18_MARK, KEYIN2_MARK, IDED10_MARK,
353 D17_MARK, KEYIN1_MARK, IDED9_MARK,
354 D16_MARK, KEYIN0_MARK, IDED8_MARK,
355
356 /*PTB*/
357 D31_MARK, TPUTO1_MARK, IDEA1_MARK,
358 D30_MARK, TPUTO0_MARK, IDEA0_MARK,
359 D29_MARK, IODREQ_MARK,
360 D28_MARK, IDECS0_MARK,
361 D27_MARK, IDECS1_MARK,
362 D26_MARK, KEYOUT5_IN5_MARK, IDEIORD_MARK,
363 D25_MARK, KEYOUT4_IN6_MARK, IDEIOWR_MARK,
364 D24_MARK, KEYOUT3_MARK, IDEINT_MARK,
365
366 /*PTC*/
367 LCDD7_MARK,
368 LCDD6_MARK,
369 LCDD5_MARK,
370 LCDD4_MARK,
371 LCDD3_MARK,
372 LCDD2_MARK,
373 LCDD1_MARK,
374 LCDD0_MARK,
375
376 /*PTD*/
377 LCDD15_MARK,
378 LCDD14_MARK,
379 LCDD13_MARK,
380 LCDD12_MARK,
381 LCDD11_MARK,
382 LCDD10_MARK,
383 LCDD9_MARK,
384 LCDD8_MARK,
385
386 /*PTE*/
387 FSIMCKB_MARK,
388 FSIMCKA_MARK,
389 LCDD21_MARK, SCIF2_L_TXD_MARK,
390 LCDD20_MARK, SCIF4_SCK_MARK,
391 LCDD19_MARK, SCIF4_RXD_MARK,
392 LCDD18_MARK, SCIF4_TXD_MARK,
393 LCDD17_MARK,
394 LCDD16_MARK,
395
396 /*PTF*/
397 LCDVSYN_MARK,
398 LCDDISP_MARK, LCDRS_MARK,
399 LCDHSYN_MARK, LCDCS_MARK,
400 LCDDON_MARK,
401 LCDDCK_MARK, LCDWR_MARK,
402 LCDVEPWC_MARK, SCIF0_TXD_MARK,
403 LCDD23_MARK, SCIF2_L_SCK_MARK,
404 LCDD22_MARK, SCIF2_L_RXD_MARK,
405
406 /*PTG*/
407 AUDCK_MARK,
408 AUDSYNC_MARK,
409 AUDATA3_MARK,
410 AUDATA2_MARK,
411 AUDATA1_MARK,
412 AUDATA0_MARK,
413
414 /*PTH*/
415 VIO0_VD_MARK,
416 VIO0_CLK_MARK,
417 VIO0_D7_MARK,
418 VIO0_D6_MARK,
419 VIO0_D5_MARK,
420 VIO0_D4_MARK,
421 VIO0_D3_MARK,
422 VIO0_D2_MARK,
423
424 /*PTJ*/
425 PDSTATUS_MARK,
426 STATUS2_MARK,
427 STATUS0_MARK,
428 A25_MARK, BS_MARK,
429 A24_MARK,
430 A23_MARK,
431 A22_MARK,
432
433 /*PTK*/
434 VIO1_D5_MARK, VIO0_D13_MARK, IDED5_MARK,
435 VIO1_D4_MARK, VIO0_D12_MARK, IDED4_MARK,
436 VIO1_D3_MARK, VIO0_D11_MARK, IDED3_MARK,
437 VIO1_D2_MARK, VIO0_D10_MARK, IDED2_MARK,
438 VIO1_D1_MARK, VIO0_D9_MARK, IDED1_MARK,
439 VIO1_D0_MARK, VIO0_D8_MARK, IDED0_MARK,
440 VIO0_FLD_MARK,
441 VIO0_HD_MARK,
442
443 /*PTL*/
444 DV_D5_MARK, SCIF3_V_SCK_MARK, RMII_RXD0_MARK,
445 DV_D4_MARK, SCIF3_V_RXD_MARK, RMII_RXD1_MARK,
446 DV_D3_MARK, SCIF3_V_TXD_MARK, RMII_REF_CLK_MARK,
447 DV_D2_MARK, SCIF1_SCK_MARK, RMII_TX_EN_MARK,
448 DV_D1_MARK, SCIF1_RXD_MARK, RMII_TXD0_MARK,
449 DV_D0_MARK, SCIF1_TXD_MARK, RMII_TXD1_MARK,
450 DV_D15_MARK,
451 DV_D14_MARK, MSIOF0_MCK_MARK,
452
453 /*PTM*/
454 DV_D13_MARK, MSIOF0_TSCK_MARK,
455 DV_D12_MARK, MSIOF0_RXD_MARK,
456 DV_D11_MARK, MSIOF0_TXD_MARK,
457 DV_D10_MARK, MSIOF0_TSYNC_MARK,
458 DV_D9_MARK, MSIOF0_SS1_MARK, MSIOF0_RSCK_MARK,
459 DV_D8_MARK, MSIOF0_SS2_MARK, MSIOF0_RSYNC_MARK,
460 LCDVCPWC_MARK, SCIF0_RXD_MARK,
461 LCDRD_MARK, SCIF0_SCK_MARK,
462
463 /*PTN*/
464 VIO0_D1_MARK,
465 VIO0_D0_MARK,
466 DV_CLKI_MARK,
467 DV_CLK_MARK, SCIF2_V_SCK_MARK,
468 DV_VSYNC_MARK, SCIF2_V_RXD_MARK,
469 DV_HSYNC_MARK, SCIF2_V_TXD_MARK,
470 DV_D7_MARK, SCIF3_V_CTS_MARK, RMII_RX_ER_MARK,
471 DV_D6_MARK, SCIF3_V_RTS_MARK, RMII_CRS_DV_MARK,
472
473 /*PTQ*/
474 D7_MARK,
475 D6_MARK,
476 D5_MARK,
477 D4_MARK,
478 D3_MARK,
479 D2_MARK,
480 D1_MARK,
481 D0_MARK,
482
483 /*PTR*/
484 CS6B_CE1B_MARK,
485 CS6A_CE2B_MARK,
486 CS5B_CE1A_MARK,
487 CS5A_CE2A_MARK,
488 IOIS16_MARK, LCDLCLK_MARK,
489 WAIT_MARK,
490 WE3_ICIOWR_MARK, TPUTO3_MARK, TPUTI3_MARK,
491 WE2_ICIORD_MARK, TPUTO2_MARK, IDEA2_MARK,
492
493 /*PTS*/
494 VIO_CKO_MARK,
495 VIO1_FLD_MARK, TPUTI2_MARK, IDEIORDY_MARK,
496 VIO1_HD_MARK, SCIF5_SCK_MARK,
497 VIO1_VD_MARK, SCIF5_RXD_MARK,
498 VIO1_CLK_MARK, SCIF5_TXD_MARK,
499 VIO1_D7_MARK, VIO0_D15_MARK, IDED7_MARK,
500 VIO1_D6_MARK, VIO0_D14_MARK, IDED6_MARK,
501
502 /*PTT*/
503 D15_MARK,
504 D14_MARK,
505 D13_MARK,
506 D12_MARK,
507 D11_MARK,
508 D10_MARK,
509 D9_MARK,
510 D8_MARK,
511
512 /*PTU*/
513 DMAC_DACK0_MARK,
514 DMAC_DREQ0_MARK,
515 FSIOASD_MARK,
516 FSIIABCK_MARK,
517 FSIIALRCK_MARK,
518 FSIOABCK_MARK,
519 FSIOALRCK_MARK,
520 CLKAUDIOAO_MARK,
521
522 /*PTV*/
523 FSIIBSD_MARK, MSIOF1_SS2_MARK, MSIOF1_RSYNC_MARK,
524 FSIOBSD_MARK, MSIOF1_SS1_MARK, MSIOF1_RSCK_MARK,
525 FSIIBBCK_MARK, MSIOF1_RXD_MARK,
526 FSIIBLRCK_MARK, MSIOF1_TSYNC_MARK,
527 FSIOBBCK_MARK, MSIOF1_TSCK_MARK,
528 FSIOBLRCK_MARK, MSIOF1_TXD_MARK,
529 CLKAUDIOBO_MARK, MSIOF1_MCK_MARK,
530 FSIIASD_MARK,
531
532 /*PTW*/
533 MMC_D7_MARK, SDHI1CD_MARK, IODACK_MARK,
534 MMC_D6_MARK, SDHI1WP_MARK, IDERST_MARK,
535 MMC_D5_MARK, SDHI1D3_MARK, EXBUF_ENB_MARK,
536 MMC_D4_MARK, SDHI1D2_MARK, DIRECTION_MARK,
537 MMC_D3_MARK, SDHI1D1_MARK,
538 MMC_D2_MARK, SDHI1D0_MARK,
539 MMC_D1_MARK, SDHI1CMD_MARK,
540 MMC_D0_MARK, SDHI1CLK_MARK,
541
542 /*PTX*/
543 DMAC_DACK1_MARK, IRDA_OUT_MARK,
544 DMAC_DREQ1_MARK, IRDA_IN_MARK,
545 TSIF_TS0_SDAT_MARK, LNKSTA_MARK,
546 TSIF_TS0_SCK_MARK, MDIO_MARK,
547 TSIF_TS0_SDEN_MARK, MDC_MARK,
548 TSIF_TS0_SPSYNC_MARK,
549 MMC_CLK_MARK,
550 MMC_CMD_MARK,
551
552 /*PTY*/
553 SDHI0CD_MARK,
554 SDHI0WP_MARK,
555 SDHI0D3_MARK,
556 SDHI0D2_MARK,
557 SDHI0D1_MARK,
558 SDHI0D0_MARK,
559 SDHI0CMD_MARK,
560 SDHI0CLK_MARK,
561
562 /*PTZ*/
563 INTC_IRQ7_MARK, SCIF3_I_CTS_MARK,
564 INTC_IRQ6_MARK, SCIF3_I_RTS_MARK,
565 INTC_IRQ5_MARK, SCIF3_I_SCK_MARK,
566 INTC_IRQ4_MARK, SCIF3_I_RXD_MARK,
567 INTC_IRQ3_MARK, SCIF3_I_TXD_MARK,
568 INTC_IRQ2_MARK,
569 INTC_IRQ1_MARK,
570 INTC_IRQ0_MARK,
571 PINMUX_MARK_END,
572};
573
574static pinmux_enum_t pinmux_data[] = {
575 /* PTA GPIO */
576 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
577 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
578 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
579 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
580 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
581 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
582 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
583 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
584
585 /* PTB GPIO */
586 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
587 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
588 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
589 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
590 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
591 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
592 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
593 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
594
595 /* PTC GPIO */
596 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
597 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
598 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
599 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
600 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
601 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
602 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
603 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
604
605 /* PTD GPIO */
606 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
607 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
608 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
609 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
610 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
611 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
612 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
613 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
614
615 /* PTE GPIO */
616 PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU),
617 PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU),
618 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU),
619 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
620 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
621 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
622 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
623 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
624
625 /* PTF GPIO */
626 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU),
627 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU),
628 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU),
629 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU),
630 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU),
631 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU),
632 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU),
633 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
634
635 /* PTG GPIO */
636 PINMUX_DATA(PTG5_DATA, PTG5_OUT),
637 PINMUX_DATA(PTG4_DATA, PTG4_OUT),
638 PINMUX_DATA(PTG3_DATA, PTG3_OUT),
639 PINMUX_DATA(PTG2_DATA, PTG2_OUT),
640 PINMUX_DATA(PTG1_DATA, PTG1_OUT),
641 PINMUX_DATA(PTG0_DATA, PTG0_OUT),
642
643 /* PTH GPIO */
644 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU),
645 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
646 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
647 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
648 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
649 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
650 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
651 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
652
653 /* PTJ GPIO */
654 PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
655 PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
656 PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
657 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
658 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
659 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
660 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
661
662 /* PTK GPIO */
663 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU),
664 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU),
665 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU),
666 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU),
667 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
668 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
669 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
670 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
671
672 /* PTL GPIO */
673 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
674 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
675 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
676 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
677 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
678 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU),
679 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU),
680 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU),
681
682 /* PTM GPIO */
683 PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
684 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
685 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
686 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
687 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
688 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
689 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
690 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
691
692 /* PTN GPIO */
693 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU),
694 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU),
695 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU),
696 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU),
697 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU),
698 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU),
699 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU),
700 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU),
701
702 /* PTQ GPIO */
703 PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU),
704 PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU),
705 PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU),
706 PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU),
707 PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU),
708 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU),
709 PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU),
710 PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU),
711
712 /* PTR GPIO */
713 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
714 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
715 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
716 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
717 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_IN_PU),
718 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
719 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
720 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
721
722 /* PTS GPIO */
723 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU),
724 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU),
725 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
726 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
727 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
728 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
729 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
730
731 /* PTT GPIO */
732 PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU),
733 PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU),
734 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU),
735 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
736 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
737 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
738 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
739 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
740
741 /* PTU GPIO */
742 PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU),
743 PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU),
744 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU),
745 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
746 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
747 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
748 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
749 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
750
751 /* PTV GPIO */
752 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU),
753 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU),
754 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU),
755 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
756 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
757 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
758 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
759 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
760
761 /* PTW GPIO */
762 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU),
763 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU),
764 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU),
765 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU),
766 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU),
767 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU),
768 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU),
769 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU),
770
771 /* PTX GPIO */
772 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU),
773 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU),
774 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU),
775 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU),
776 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU),
777 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU),
778 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU),
779 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU),
780
781 /* PTY GPIO */
782 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU),
783 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU),
784 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU),
785 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU),
786 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU),
787 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU),
788 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU),
789 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU),
790
791 /* PTZ GPIO */
792 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU),
793 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU),
794 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU),
795 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU),
796 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU),
797 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU),
798 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU),
799 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU),
800
801 /* PTA FN */
802 PINMUX_DATA(D23_MARK, PSA15_0, PSA14_0, PTA7_FN),
803 PINMUX_DATA(D22_MARK, PSA15_0, PSA14_0, PTA6_FN),
804 PINMUX_DATA(D21_MARK, PSA15_0, PSA14_0, PTA5_FN),
805 PINMUX_DATA(D20_MARK, PSA15_0, PSA14_0, PTA4_FN),
806 PINMUX_DATA(D19_MARK, PSA15_0, PSA14_0, PTA3_FN),
807 PINMUX_DATA(D18_MARK, PSA15_0, PSA14_0, PTA2_FN),
808 PINMUX_DATA(D17_MARK, PSA15_0, PSA14_0, PTA1_FN),
809 PINMUX_DATA(D16_MARK, PSA15_0, PSA14_0, PTA0_FN),
810
811 PINMUX_DATA(KEYOUT2_MARK, PSA15_0, PSA14_1, PTA7_FN),
812 PINMUX_DATA(KEYOUT1_MARK, PSA15_0, PSA14_1, PTA6_FN),
813 PINMUX_DATA(KEYOUT0_MARK, PSA15_0, PSA14_1, PTA5_FN),
814 PINMUX_DATA(KEYIN4_MARK, PSA15_0, PSA14_1, PTA4_FN),
815 PINMUX_DATA(KEYIN3_MARK, PSA15_0, PSA14_1, PTA3_FN),
816 PINMUX_DATA(KEYIN2_MARK, PSA15_0, PSA14_1, PTA2_FN),
817 PINMUX_DATA(KEYIN1_MARK, PSA15_0, PSA14_1, PTA1_FN),
818 PINMUX_DATA(KEYIN0_MARK, PSA15_0, PSA14_1, PTA0_FN),
819
820 PINMUX_DATA(IDED15_MARK, PSA15_1, PSA14_0, PTA7_FN),
821 PINMUX_DATA(IDED14_MARK, PSA15_1, PSA14_0, PTA6_FN),
822 PINMUX_DATA(IDED13_MARK, PSA15_1, PSA14_0, PTA5_FN),
823 PINMUX_DATA(IDED12_MARK, PSA15_1, PSA14_0, PTA4_FN),
824 PINMUX_DATA(IDED11_MARK, PSA15_1, PSA14_0, PTA3_FN),
825 PINMUX_DATA(IDED10_MARK, PSA15_1, PSA14_0, PTA2_FN),
826 PINMUX_DATA(IDED9_MARK, PSA15_1, PSA14_0, PTA1_FN),
827 PINMUX_DATA(IDED8_MARK, PSA15_1, PSA14_0, PTA0_FN),
828
829 /* PTB FN */
830 PINMUX_DATA(D31_MARK, PSE15_0, PSE14_0, PTB7_FN),
831 PINMUX_DATA(D30_MARK, PSE15_0, PSE14_0, PTB6_FN),
832 PINMUX_DATA(D29_MARK, PSE11_0, PTB5_FN),
833 PINMUX_DATA(D28_MARK, PSE11_0, PTB4_FN),
834 PINMUX_DATA(D27_MARK, PSE11_0, PTB3_FN),
835 PINMUX_DATA(D26_MARK, PSA15_0, PSA14_0, PTB2_FN),
836 PINMUX_DATA(D25_MARK, PSA15_0, PSA14_0, PTB1_FN),
837 PINMUX_DATA(D24_MARK, PSA15_0, PSA14_0, PTB0_FN),
838
839 PINMUX_DATA(IDEA1_MARK, PSE15_1, PSE14_0, PTB7_FN),
840 PINMUX_DATA(IDEA0_MARK, PSE15_1, PSE14_0, PTB6_FN),
841 PINMUX_DATA(IODREQ_MARK, PSE11_1, PTB5_FN),
842 PINMUX_DATA(IDECS0_MARK, PSE11_1, PTB4_FN),
843 PINMUX_DATA(IDECS1_MARK, PSE11_1, PTB3_FN),
844 PINMUX_DATA(IDEIORD_MARK, PSA15_1, PSA14_0, PTB2_FN),
845 PINMUX_DATA(IDEIOWR_MARK, PSA15_1, PSA14_0, PTB1_FN),
846 PINMUX_DATA(IDEINT_MARK, PSA15_1, PSA14_0, PTB0_FN),
847
848 PINMUX_DATA(TPUTO1_MARK, PSE15_0, PSE14_1, PTB7_FN),
849 PINMUX_DATA(TPUTO0_MARK, PSE15_0, PSE14_1, PTB6_FN),
850
851 PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_0, PSA14_1, PTB2_FN),
852 PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_0, PSA14_1, PTB1_FN),
853 PINMUX_DATA(KEYOUT3_MARK, PSA15_0, PSA14_1, PTB0_FN),
854
855 /* PTC FN */
856 PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN),
857 PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN),
858 PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN),
859 PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN),
860 PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN),
861 PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN),
862 PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN),
863 PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN),
864
865 /* PTD FN */
866 PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN),
867 PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN),
868 PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN),
869 PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN),
870 PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN),
871 PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN),
872 PINMUX_DATA(LCDD9_MARK, PSD5_0, PTD1_FN),
873 PINMUX_DATA(LCDD8_MARK, PSD5_0, PTD0_FN),
874
875 /* PTE FN */
876 PINMUX_DATA(FSIMCKB_MARK, PTE7_FN),
877 PINMUX_DATA(FSIMCKA_MARK, PTE6_FN),
878
879 PINMUX_DATA(LCDD21_MARK, PSC5_0, PSC4_0, PTE5_FN),
880 PINMUX_DATA(LCDD20_MARK, PSD3_0, PSD2_0, PTE4_FN),
881 PINMUX_DATA(LCDD19_MARK, PSA3_0, PSA2_0, PTE3_FN),
882 PINMUX_DATA(LCDD18_MARK, PSA3_0, PSA2_0, PTE2_FN),
883 PINMUX_DATA(LCDD17_MARK, PSD5_0, PTE1_FN),
884 PINMUX_DATA(LCDD16_MARK, PSD5_0, PTE0_FN),
885
886 PINMUX_DATA(SCIF2_L_TXD_MARK, PSC5_0, PSC4_1, PTE5_FN),
887 PINMUX_DATA(SCIF4_SCK_MARK, PSD3_0, PSD2_1, PTE4_FN),
888 PINMUX_DATA(SCIF4_RXD_MARK, PSA3_0, PSA2_1, PTE3_FN),
889 PINMUX_DATA(SCIF4_TXD_MARK, PSA3_0, PSA2_1, PTE2_FN),
890
891 /* PTF FN */
892 PINMUX_DATA(LCDVSYN_MARK, PSD8_0, PTF7_FN),
893 PINMUX_DATA(LCDDISP_MARK, PSD10_0, PSD9_0, PTF6_FN),
894 PINMUX_DATA(LCDHSYN_MARK, PSD10_0, PSD9_0, PTF5_FN),
895 PINMUX_DATA(LCDDON_MARK, PSD8_0, PTF4_FN),
896 PINMUX_DATA(LCDDCK_MARK, PSD10_0, PSD9_0, PTF3_FN),
897 PINMUX_DATA(LCDVEPWC_MARK, PSA6_0, PTF2_FN),
898 PINMUX_DATA(LCDD23_MARK, PSC7_0, PSC6_0, PTF1_FN),
899 PINMUX_DATA(LCDD22_MARK, PSC5_0, PSC4_0, PTF0_FN),
900
901 PINMUX_DATA(LCDRS_MARK, PSD10_0, PSD9_1, PTF6_FN),
902 PINMUX_DATA(LCDCS_MARK, PSD10_0, PSD9_1, PTF5_FN),
903 PINMUX_DATA(LCDWR_MARK, PSD10_0, PSD9_1, PTF3_FN),
904
905 PINMUX_DATA(SCIF0_TXD_MARK, PSA6_1, PTF2_FN),
906 PINMUX_DATA(SCIF2_L_SCK_MARK, PSC7_0, PSC6_1, PTF1_FN),
907 PINMUX_DATA(SCIF2_L_RXD_MARK, PSC5_0, PSC4_1, PTF0_FN),
908
909 /* PTG FN */
910 PINMUX_DATA(AUDCK_MARK, PTG5_FN),
911 PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
912 PINMUX_DATA(AUDATA3_MARK, PTG3_FN),
913 PINMUX_DATA(AUDATA2_MARK, PTG2_FN),
914 PINMUX_DATA(AUDATA1_MARK, PTG1_FN),
915 PINMUX_DATA(AUDATA0_MARK, PTG0_FN),
916
917 /* PTH FN */
918 PINMUX_DATA(VIO0_VD_MARK, PTH7_FN),
919 PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN),
920 PINMUX_DATA(VIO0_D7_MARK, PTH5_FN),
921 PINMUX_DATA(VIO0_D6_MARK, PTH4_FN),
922 PINMUX_DATA(VIO0_D5_MARK, PTH3_FN),
923 PINMUX_DATA(VIO0_D4_MARK, PTH2_FN),
924 PINMUX_DATA(VIO0_D3_MARK, PTH1_FN),
925 PINMUX_DATA(VIO0_D2_MARK, PTH0_FN),
926
927 /* PTJ FN */
928 PINMUX_DATA(PDSTATUS_MARK, PTJ7_FN),
929 PINMUX_DATA(STATUS2_MARK, PTJ6_FN),
930 PINMUX_DATA(STATUS0_MARK, PTJ5_FN),
931 PINMUX_DATA(A25_MARK, PSA8_0, PTJ3_FN),
932 PINMUX_DATA(BS_MARK, PSA8_1, PTJ3_FN),
933 PINMUX_DATA(A24_MARK, PTJ2_FN),
934 PINMUX_DATA(A23_MARK, PTJ1_FN),
935 PINMUX_DATA(A22_MARK, PTJ0_FN),
936
937 /* PTK FN */
938 PINMUX_DATA(VIO1_D5_MARK, PSB7_0, PSB6_0, PTK7_FN),
939 PINMUX_DATA(VIO1_D4_MARK, PSB7_0, PSB6_0, PTK6_FN),
940 PINMUX_DATA(VIO1_D3_MARK, PSB7_0, PSB6_0, PTK5_FN),
941 PINMUX_DATA(VIO1_D2_MARK, PSB7_0, PSB6_0, PTK4_FN),
942 PINMUX_DATA(VIO1_D1_MARK, PSB7_0, PSB6_0, PTK3_FN),
943 PINMUX_DATA(VIO1_D0_MARK, PSB7_0, PSB6_0, PTK2_FN),
944
945 PINMUX_DATA(VIO0_D13_MARK, PSB7_0, PSB6_1, PTK7_FN),
946 PINMUX_DATA(VIO0_D12_MARK, PSB7_0, PSB6_1, PTK6_FN),
947 PINMUX_DATA(VIO0_D11_MARK, PSB7_0, PSB6_1, PTK5_FN),
948 PINMUX_DATA(VIO0_D10_MARK, PSB7_0, PSB6_1, PTK4_FN),
949 PINMUX_DATA(VIO0_D9_MARK, PSB7_0, PSB6_1, PTK3_FN),
950 PINMUX_DATA(VIO0_D8_MARK, PSB7_0, PSB6_1, PTK2_FN),
951
952 PINMUX_DATA(IDED5_MARK, PSB7_1, PSB6_0, PTK7_FN),
953 PINMUX_DATA(IDED4_MARK, PSB7_1, PSB6_0, PTK6_FN),
954 PINMUX_DATA(IDED3_MARK, PSB7_1, PSB6_0, PTK5_FN),
955 PINMUX_DATA(IDED2_MARK, PSB7_1, PSB6_0, PTK4_FN),
956 PINMUX_DATA(IDED1_MARK, PSB7_1, PSB6_0, PTK3_FN),
957 PINMUX_DATA(IDED0_MARK, PSB7_1, PSB6_0, PTK2_FN),
958
959 PINMUX_DATA(VIO0_FLD_MARK, PTK1_FN),
960 PINMUX_DATA(VIO0_HD_MARK, PTK0_FN),
961
962 /* PTL FN */
963 PINMUX_DATA(DV_D5_MARK, PSB9_0, PSB8_0, PTL7_FN),
964 PINMUX_DATA(DV_D4_MARK, PSB9_0, PSB8_0, PTL6_FN),
965 PINMUX_DATA(DV_D3_MARK, PSE7_0, PSE6_0, PTL5_FN),
966 PINMUX_DATA(DV_D2_MARK, PSC9_0, PSC8_0, PTL4_FN),
967 PINMUX_DATA(DV_D1_MARK, PSC9_0, PSC8_0, PTL3_FN),
968 PINMUX_DATA(DV_D0_MARK, PSC9_0, PSC8_0, PTL2_FN),
969 PINMUX_DATA(DV_D15_MARK, PSD4_0, PTL1_FN),
970 PINMUX_DATA(DV_D14_MARK, PSE5_0, PSE4_0, PTL0_FN),
971
972 PINMUX_DATA(SCIF3_V_SCK_MARK, PSB9_0, PSB8_1, PTL7_FN),
973 PINMUX_DATA(SCIF3_V_RXD_MARK, PSB9_0, PSB8_1, PTL6_FN),
974 PINMUX_DATA(SCIF3_V_TXD_MARK, PSE7_0, PSE6_1, PTL5_FN),
975 PINMUX_DATA(SCIF1_SCK_MARK, PSC9_0, PSC8_1, PTL4_FN),
976 PINMUX_DATA(SCIF1_RXD_MARK, PSC9_0, PSC8_1, PTL3_FN),
977 PINMUX_DATA(SCIF1_TXD_MARK, PSC9_0, PSC8_1, PTL2_FN),
978
979 PINMUX_DATA(RMII_RXD0_MARK, PSB9_1, PSB8_0, PTL7_FN),
980 PINMUX_DATA(RMII_RXD1_MARK, PSB9_1, PSB8_0, PTL6_FN),
981 PINMUX_DATA(RMII_REF_CLK_MARK, PSE7_1, PSE6_0, PTL5_FN),
982 PINMUX_DATA(RMII_TX_EN_MARK, PSC9_1, PSC8_0, PTL4_FN),
983 PINMUX_DATA(RMII_TXD0_MARK, PSC9_1, PSC8_0, PTL3_FN),
984 PINMUX_DATA(RMII_TXD1_MARK, PSC9_1, PSC8_0, PTL2_FN),
985
986 PINMUX_DATA(MSIOF0_MCK_MARK, PSE5_0, PSE4_1, PTL0_FN),
987
988 /* PTM FN */
989 PINMUX_DATA(DV_D13_MARK, PSC13_0, PSC12_0, PTM7_FN),
990 PINMUX_DATA(DV_D12_MARK, PSC13_0, PSC12_0, PTM6_FN),
991 PINMUX_DATA(DV_D11_MARK, PSC13_0, PSC12_0, PTM5_FN),
992 PINMUX_DATA(DV_D10_MARK, PSC13_0, PSC12_0, PTM4_FN),
993 PINMUX_DATA(DV_D9_MARK, PSC11_0, PSC10_0, PTM3_FN),
994 PINMUX_DATA(DV_D8_MARK, PSC11_0, PSC10_0, PTM2_FN),
995
996 PINMUX_DATA(MSIOF0_TSCK_MARK, PSC13_0, PSC12_1, PTM7_FN),
997 PINMUX_DATA(MSIOF0_RXD_MARK, PSC13_0, PSC12_1, PTM6_FN),
998 PINMUX_DATA(MSIOF0_TXD_MARK, PSC13_0, PSC12_1, PTM5_FN),
999 PINMUX_DATA(MSIOF0_TSYNC_MARK, PSC13_0, PSC12_1, PTM4_FN),
1000 PINMUX_DATA(MSIOF0_SS1_MARK, PSC11_0, PSC10_1, PTM3_FN),
1001 PINMUX_DATA(MSIOF0_RSCK_MARK, PSC11_1, PSC10_0, PTM3_FN),
1002 PINMUX_DATA(MSIOF0_SS2_MARK, PSC11_0, PSC10_1, PTM2_FN),
1003 PINMUX_DATA(MSIOF0_RSYNC_MARK, PSC11_1, PSC10_0, PTM2_FN),
1004
1005 PINMUX_DATA(LCDVCPWC_MARK, PSA6_0, PTM1_FN),
1006 PINMUX_DATA(LCDRD_MARK, PSA7_0, PTM0_FN),
1007
1008 PINMUX_DATA(SCIF0_RXD_MARK, PSA6_1, PTM1_FN),
1009 PINMUX_DATA(SCIF0_SCK_MARK, PSA7_1, PTM0_FN),
1010
1011 /* PTN FN */
1012 PINMUX_DATA(VIO0_D1_MARK, PTN7_FN),
1013 PINMUX_DATA(VIO0_D0_MARK, PTN6_FN),
1014
1015 PINMUX_DATA(DV_CLKI_MARK, PSD11_0, PTN5_FN),
1016 PINMUX_DATA(DV_CLK_MARK, PSD13_0, PSD12_0, PTN4_FN),
1017 PINMUX_DATA(DV_VSYNC_MARK, PSD15_0, PSD14_0, PTN3_FN),
1018 PINMUX_DATA(DV_HSYNC_MARK, PSB5_0, PSB4_0, PTN2_FN),
1019 PINMUX_DATA(DV_D7_MARK, PSB3_0, PSB2_0, PTN1_FN),
1020 PINMUX_DATA(DV_D6_MARK, PSB1_0, PSB0_0, PTN0_FN),
1021
1022 PINMUX_DATA(SCIF2_V_SCK_MARK, PSD13_0, PSD12_1, PTN4_FN),
1023 PINMUX_DATA(SCIF2_V_RXD_MARK, PSD15_0, PSD14_1, PTN3_FN),
1024 PINMUX_DATA(SCIF2_V_TXD_MARK, PSB5_0, PSB4_1, PTN2_FN),
1025 PINMUX_DATA(SCIF3_V_CTS_MARK, PSB3_0, PSB2_1, PTN1_FN),
1026 PINMUX_DATA(SCIF3_V_RTS_MARK, PSB1_0, PSB0_1, PTN0_FN),
1027
1028 PINMUX_DATA(RMII_RX_ER_MARK, PSB3_1, PSB2_0, PTN1_FN),
1029 PINMUX_DATA(RMII_CRS_DV_MARK, PSB1_1, PSB0_0, PTN0_FN),
1030
1031 /* PTQ FN */
1032 PINMUX_DATA(D7_MARK, PTQ7_FN),
1033 PINMUX_DATA(D6_MARK, PTQ6_FN),
1034 PINMUX_DATA(D5_MARK, PTQ5_FN),
1035 PINMUX_DATA(D4_MARK, PTQ4_FN),
1036 PINMUX_DATA(D3_MARK, PTQ3_FN),
1037 PINMUX_DATA(D2_MARK, PTQ2_FN),
1038 PINMUX_DATA(D1_MARK, PTQ1_FN),
1039 PINMUX_DATA(D0_MARK, PTQ0_FN),
1040
1041 /* PTR FN */
1042 PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN),
1043 PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN),
1044 PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN),
1045 PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN),
1046 PINMUX_DATA(IOIS16_MARK, PSA5_0, PTR3_FN),
1047 PINMUX_DATA(WAIT_MARK, PTR2_FN),
1048 PINMUX_DATA(WE3_ICIOWR_MARK, PSA1_0, PSA0_0, PTR1_FN),
1049 PINMUX_DATA(WE2_ICIORD_MARK, PSD1_0, PSD0_0, PTR0_FN),
1050
1051 PINMUX_DATA(LCDLCLK_MARK, PSA5_1, PTR3_FN),
1052
1053 PINMUX_DATA(IDEA2_MARK, PSD1_1, PSD0_0, PTR0_FN),
1054
1055 PINMUX_DATA(TPUTO3_MARK, PSA1_0, PSA0_1, PTR1_FN),
1056 PINMUX_DATA(TPUTI3_MARK, PSA1_1, PSA0_0, PTR1_FN),
1057 PINMUX_DATA(TPUTO2_MARK, PSD1_0, PSD0_1, PTR0_FN),
1058
1059 /* PTS FN */
1060 PINMUX_DATA(VIO_CKO_MARK, PTS6_FN),
1061
1062 PINMUX_DATA(TPUTI2_MARK, PSE9_0, PSE8_1, PTS5_FN),
1063
1064 PINMUX_DATA(IDEIORDY_MARK, PSE9_1, PSE8_0, PTS5_FN),
1065
1066 PINMUX_DATA(VIO1_FLD_MARK, PSE9_0, PSE8_0, PTS5_FN),
1067 PINMUX_DATA(VIO1_HD_MARK, PSA10_0, PTS4_FN),
1068 PINMUX_DATA(VIO1_VD_MARK, PSA9_0, PTS3_FN),
1069 PINMUX_DATA(VIO1_CLK_MARK, PSA9_0, PTS2_FN),
1070 PINMUX_DATA(VIO1_D7_MARK, PSB7_0, PSB6_0, PTS1_FN),
1071 PINMUX_DATA(VIO1_D6_MARK, PSB7_0, PSB6_0, PTS0_FN),
1072
1073 PINMUX_DATA(SCIF5_SCK_MARK, PSA10_1, PTS4_FN),
1074 PINMUX_DATA(SCIF5_RXD_MARK, PSA9_1, PTS3_FN),
1075 PINMUX_DATA(SCIF5_TXD_MARK, PSA9_1, PTS2_FN),
1076
1077 PINMUX_DATA(VIO0_D15_MARK, PSB7_0, PSB6_1, PTS1_FN),
1078 PINMUX_DATA(VIO0_D14_MARK, PSB7_0, PSB6_1, PTS0_FN),
1079
1080 PINMUX_DATA(IDED7_MARK, PSB7_1, PSB6_0, PTS1_FN),
1081 PINMUX_DATA(IDED6_MARK, PSB7_1, PSB6_0, PTS0_FN),
1082
1083 /* PTT FN */
1084 PINMUX_DATA(D15_MARK, PTT7_FN),
1085 PINMUX_DATA(D14_MARK, PTT6_FN),
1086 PINMUX_DATA(D13_MARK, PTT5_FN),
1087 PINMUX_DATA(D12_MARK, PTT4_FN),
1088 PINMUX_DATA(D11_MARK, PTT3_FN),
1089 PINMUX_DATA(D10_MARK, PTT2_FN),
1090 PINMUX_DATA(D9_MARK, PTT1_FN),
1091 PINMUX_DATA(D8_MARK, PTT0_FN),
1092
1093 /* PTU FN */
1094 PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN),
1095 PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN),
1096
1097 PINMUX_DATA(FSIOASD_MARK, PSE1_0, PTU5_FN),
1098 PINMUX_DATA(FSIIABCK_MARK, PSE1_0, PTU4_FN),
1099 PINMUX_DATA(FSIIALRCK_MARK, PSE1_0, PTU3_FN),
1100 PINMUX_DATA(FSIOABCK_MARK, PSE1_0, PTU2_FN),
1101 PINMUX_DATA(FSIOALRCK_MARK, PSE1_0, PTU1_FN),
1102 PINMUX_DATA(CLKAUDIOAO_MARK, PSE0_0, PTU0_FN),
1103
1104 /* PTV FN */
1105 PINMUX_DATA(FSIIBSD_MARK, PSD7_0, PSD6_0, PTV7_FN),
1106 PINMUX_DATA(FSIOBSD_MARK, PSD7_0, PSD6_0, PTV6_FN),
1107 PINMUX_DATA(FSIIBBCK_MARK, PSC15_0, PSC14_0, PTV5_FN),
1108 PINMUX_DATA(FSIIBLRCK_MARK, PSC15_0, PSC14_0, PTV4_FN),
1109 PINMUX_DATA(FSIOBBCK_MARK, PSC15_0, PSC14_0, PTV3_FN),
1110 PINMUX_DATA(FSIOBLRCK_MARK, PSC15_0, PSC14_0, PTV2_FN),
1111 PINMUX_DATA(CLKAUDIOBO_MARK, PSE3_0, PSE2_0, PTV1_FN),
1112 PINMUX_DATA(FSIIASD_MARK, PSE10_0, PTV0_FN),
1113
1114 PINMUX_DATA(MSIOF1_SS2_MARK, PSD7_0, PSD6_1, PTV7_FN),
1115 PINMUX_DATA(MSIOF1_RSYNC_MARK, PSD7_1, PSD6_0, PTV7_FN),
1116 PINMUX_DATA(MSIOF1_SS1_MARK, PSD7_0, PSD6_1, PTV6_FN),
1117 PINMUX_DATA(MSIOF1_RSCK_MARK, PSD7_1, PSD6_0, PTV6_FN),
1118 PINMUX_DATA(MSIOF1_RXD_MARK, PSC15_0, PSC14_1, PTV5_FN),
1119 PINMUX_DATA(MSIOF1_TSYNC_MARK, PSC15_0, PSC14_1, PTV4_FN),
1120 PINMUX_DATA(MSIOF1_TSCK_MARK, PSC15_0, PSC14_1, PTV3_FN),
1121 PINMUX_DATA(MSIOF1_TXD_MARK, PSC15_0, PSC14_1, PTV2_FN),
1122 PINMUX_DATA(MSIOF1_MCK_MARK, PSE3_0, PSE2_1, PTV1_FN),
1123
1124 /* PTW FN */
1125 PINMUX_DATA(MMC_D7_MARK, PSE13_0, PSE12_0, PTW7_FN),
1126 PINMUX_DATA(MMC_D6_MARK, PSE13_0, PSE12_0, PTW6_FN),
1127 PINMUX_DATA(MMC_D5_MARK, PSE13_0, PSE12_0, PTW5_FN),
1128 PINMUX_DATA(MMC_D4_MARK, PSE13_0, PSE12_0, PTW4_FN),
1129 PINMUX_DATA(MMC_D3_MARK, PSA13_0, PTW3_FN),
1130 PINMUX_DATA(MMC_D2_MARK, PSA13_0, PTW2_FN),
1131 PINMUX_DATA(MMC_D1_MARK, PSA13_0, PTW1_FN),
1132 PINMUX_DATA(MMC_D0_MARK, PSA13_0, PTW0_FN),
1133
1134 PINMUX_DATA(SDHI1CD_MARK, PSE13_0, PSE12_1, PTW7_FN),
1135 PINMUX_DATA(SDHI1WP_MARK, PSE13_0, PSE12_1, PTW6_FN),
1136 PINMUX_DATA(SDHI1D3_MARK, PSE13_0, PSE12_1, PTW5_FN),
1137 PINMUX_DATA(SDHI1D2_MARK, PSE13_0, PSE12_1, PTW4_FN),
1138 PINMUX_DATA(SDHI1D1_MARK, PSA13_1, PTW3_FN),
1139 PINMUX_DATA(SDHI1D0_MARK, PSA13_1, PTW2_FN),
1140 PINMUX_DATA(SDHI1CMD_MARK, PSA13_1, PTW1_FN),
1141 PINMUX_DATA(SDHI1CLK_MARK, PSA13_1, PTW0_FN),
1142
1143 PINMUX_DATA(IODACK_MARK, PSE13_1, PSE12_0, PTW7_FN),
1144 PINMUX_DATA(IDERST_MARK, PSE13_1, PSE12_0, PTW6_FN),
1145 PINMUX_DATA(EXBUF_ENB_MARK, PSE13_1, PSE12_0, PTW5_FN),
1146 PINMUX_DATA(DIRECTION_MARK, PSE13_1, PSE12_0, PTW4_FN),
1147
1148 /* PTX FN */
1149 PINMUX_DATA(DMAC_DACK1_MARK, PSA12_0, PTX7_FN),
1150 PINMUX_DATA(DMAC_DREQ1_MARK, PSA12_0, PTX6_FN),
1151
1152 PINMUX_DATA(IRDA_OUT_MARK, PSA12_1, PTX7_FN),
1153 PINMUX_DATA(IRDA_IN_MARK, PSA12_1, PTX6_FN),
1154
1155 PINMUX_DATA(TSIF_TS0_SDAT_MARK, PSC0_0, PTX5_FN),
1156 PINMUX_DATA(TSIF_TS0_SCK_MARK, PSC1_0, PTX4_FN),
1157 PINMUX_DATA(TSIF_TS0_SDEN_MARK, PSC2_0, PTX3_FN),
1158 PINMUX_DATA(TSIF_TS0_SPSYNC_MARK, PTX2_FN),
1159
1160 PINMUX_DATA(LNKSTA_MARK, PSC0_1, PTX5_FN),
1161 PINMUX_DATA(MDIO_MARK, PSC1_1, PTX4_FN),
1162 PINMUX_DATA(MDC_MARK, PSC2_1, PTX3_FN),
1163
1164 PINMUX_DATA(MMC_CLK_MARK, PTX1_FN),
1165 PINMUX_DATA(MMC_CMD_MARK, PTX0_FN),
1166
1167 /* PTY FN */
1168 PINMUX_DATA(SDHI0CD_MARK, PTY7_FN),
1169 PINMUX_DATA(SDHI0WP_MARK, PTY6_FN),
1170 PINMUX_DATA(SDHI0D3_MARK, PTY5_FN),
1171 PINMUX_DATA(SDHI0D2_MARK, PTY4_FN),
1172 PINMUX_DATA(SDHI0D1_MARK, PTY3_FN),
1173 PINMUX_DATA(SDHI0D0_MARK, PTY2_FN),
1174 PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN),
1175 PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN),
1176
1177 /* PTZ FN */
1178 PINMUX_DATA(INTC_IRQ7_MARK, PSB10_0, PTZ7_FN),
1179 PINMUX_DATA(INTC_IRQ6_MARK, PSB11_0, PTZ6_FN),
1180 PINMUX_DATA(INTC_IRQ5_MARK, PSB12_0, PTZ5_FN),
1181 PINMUX_DATA(INTC_IRQ4_MARK, PSB13_0, PTZ4_FN),
1182 PINMUX_DATA(INTC_IRQ3_MARK, PSB14_0, PTZ3_FN),
1183 PINMUX_DATA(INTC_IRQ2_MARK, PTZ2_FN),
1184 PINMUX_DATA(INTC_IRQ1_MARK, PTZ1_FN),
1185 PINMUX_DATA(INTC_IRQ0_MARK, PTZ0_FN),
1186
1187 PINMUX_DATA(SCIF3_I_CTS_MARK, PSB10_1, PTZ7_FN),
1188 PINMUX_DATA(SCIF3_I_RTS_MARK, PSB11_1, PTZ6_FN),
1189 PINMUX_DATA(SCIF3_I_SCK_MARK, PSB12_1, PTZ5_FN),
1190 PINMUX_DATA(SCIF3_I_RXD_MARK, PSB13_1, PTZ4_FN),
1191 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
1192};
1193
1194static struct pinmux_gpio pinmux_gpios[] = {
1195 /* PTA */
1196 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1197 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
1198 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
1199 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
1200 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
1201 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
1202 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
1203 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
1204
1205 /* PTB */
1206 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
1207 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
1208 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
1209 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
1210 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
1211 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
1212 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
1213 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
1214
1215 /* PTC */
1216 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
1217 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
1218 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
1219 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
1220 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
1221 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
1222 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
1223 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
1224
1225 /* PTD */
1226 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
1227 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
1228 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
1229 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
1230 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
1231 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
1232 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
1233 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
1234
1235 /* PTE */
1236 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
1237 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
1238 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
1239 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
1240 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
1241 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
1242 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
1243 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
1244
1245 /* PTF */
1246 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
1247 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
1248 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
1249 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
1250 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
1251 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
1252 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
1253 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
1254
1255 /* PTG */
1256 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
1257 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
1258 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
1259 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
1260 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
1261 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
1262
1263 /* PTH */
1264 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
1265 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
1266 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
1267 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
1268 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
1269 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
1270 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1271 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1272
1273 /* PTJ */
1274 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1275 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1276 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1277 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1278 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1279 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1280 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1281
1282 /* PTK */
1283 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1284 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1285 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1286 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1287 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1288 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1289 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1290 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1291
1292 /* PTL */
1293 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1294 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1295 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1296 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1297 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1298 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1299 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1300 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1301
1302 /* PTM */
1303 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1304 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1305 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1306 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1307 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1308 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1309 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1310 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1311
1312 /* PTN */
1313 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1314 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1315 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1316 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1317 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1318 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1319 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1320 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1321
1322 /* PTQ */
1323 PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA),
1324 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
1325 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
1326 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
1327 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1328 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1329 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1330 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1331
1332 /* PTR */
1333 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1334 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1335 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1336 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1337 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1338 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1339 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1340 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1341
1342 /* PTS */
1343 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1344 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1345 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1346 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1347 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1348 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1349 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1350
1351 /* PTT */
1352 PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
1353 PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
1354 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1355 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1356 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1357 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1358 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1359 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1360
1361 /* PTU */
1362 PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
1363 PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
1364 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1365 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1366 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1367 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1368 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1369 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1370
1371 /* PTV */
1372 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1373 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1374 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1375 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1376 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1377 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1378 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1379 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1380
1381 /* PTW */
1382 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1383 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1384 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1385 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1386 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1387 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1388 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1389 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1390
1391 /* PTX */
1392 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1393 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1394 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1395 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1396 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1397 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1398 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1399 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1400
1401 /* PTY */
1402 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1403 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1404 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1405 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1406 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1407 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1408 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1409 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1410
1411 /* PTZ */
1412 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1413 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1414 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1415 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1416 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1417 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1418 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1419 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1420
1421 /* BSC */
1422 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
1423 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
1424 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
1425 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
1426 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
1427 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
1428 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
1429 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
1430 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
1431 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
1432 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
1433 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
1434 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
1435 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
1436 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
1437 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
1438 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1439 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1440 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1441 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1442 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1443 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1444 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1445 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1446 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1447 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1448 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1449 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1450 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1451 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1452 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1453 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1454 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1455 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1456 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1457 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
1459 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
1460 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
1461 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
1462 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
1463 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
1464 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1465 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1466 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1467
1468 /* KEYSC */
1469 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
1470 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
1471 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
1472 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
1473 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
1474 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
1475 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
1476 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
1477 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
1478 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
1479 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
1480
1481 /* ATAPI */
1482 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
1483 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
1484 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
1485 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
1486 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
1487 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
1488 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
1489 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
1490 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
1491 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
1492 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
1493 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
1494 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
1495 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
1496 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
1497 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
1498 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
1499 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
1500 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
1501 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
1502 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
1503 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
1504 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
1505 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
1506 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
1507 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
1508 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
1509 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
1510 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
1511 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
1512
1513 /* TPU */
1514 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
1515 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
1516 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
1517 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
1518 PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK),
1519 PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK),
1520
1521 /* LCDC */
1522 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
1523 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
1524 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
1525 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
1526 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
1527 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
1528 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
1529 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
1530 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
1531 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
1532 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
1533 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
1534 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
1535 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
1536 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
1537 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
1538 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
1539 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
1540 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
1541 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
1542 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
1543 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
1544 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
1545 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
1546 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
1547 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
1548 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
1549 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
1550 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
1551 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
1552 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
1553 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
1554 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
1555 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
1556 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
1557 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
1558
1559 /* SCIF0 */
1560 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
1561 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
1562 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
1563
1564 /* SCIF1 */
1565 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
1566 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
1567 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
1568
1569 /* SCIF2 */
1570 PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK),
1571 PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK),
1572 PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK),
1573 PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK),
1574 PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK),
1575 PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK),
1576
1577 /* SCIF3 */
1578 PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK),
1579 PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK),
1580 PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK),
1581 PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK),
1582 PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK),
1583 PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK),
1584 PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK),
1585 PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK),
1586 PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK),
1587 PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK),
1588
1589 /* SCIF4 */
1590 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
1591 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
1592 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
1593
1594 /* SCIF5 */
1595 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
1596 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
1597 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
1598
1599 /* FSI */
1600 PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK),
1601 PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK),
1602 PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK),
1603 PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK),
1604 PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK),
1605 PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK),
1606 PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK),
1607 PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
1608 PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK),
1609 PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK),
1610 PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK),
1611 PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK),
1612 PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK),
1613 PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK),
1614 PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
1615 PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK),
1616
1617 /* AUD */
1618 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1619 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1620 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1621 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1622 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1623 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1624
1625 /* VIO */
1626 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
1627
1628 /* VIO0 */
1629 PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK),
1630 PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK),
1631 PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK),
1632 PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK),
1633 PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK),
1634 PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK),
1635 PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK),
1636 PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK),
1637 PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK),
1638 PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK),
1639 PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK),
1640 PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK),
1641 PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK),
1642 PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK),
1643 PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK),
1644 PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK),
1645 PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK),
1646 PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK),
1647 PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK),
1648 PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK),
1649
1650 /* VIO1 */
1651 PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK),
1652 PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK),
1653 PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK),
1654 PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK),
1655 PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK),
1656 PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK),
1657 PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK),
1658 PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK),
1659 PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK),
1660 PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK),
1661 PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK),
1662 PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK),
1663
1664 /* Eth */
1665 PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK),
1666 PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK),
1667 PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK),
1668 PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK),
1669 PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK),
1670 PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK),
1671 PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK),
1672 PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK),
1673 PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK),
1674 PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK),
1675 PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK),
1676
1677 /* System */
1678 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
1679 PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK),
1680 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1681
1682 /* VOU */
1683 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
1684 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
1685 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
1686 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
1687 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
1688 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
1689 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
1690 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
1691 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
1692 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
1693 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
1694 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
1695 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
1696 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
1697 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
1698 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
1699 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
1700 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1701 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1702 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1703
1704 /* MSIOF0 */
1705 PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK),
1706 PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK),
1707 PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK),
1708 PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK),
1709 PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK),
1710 PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK),
1711 PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK),
1712 PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK),
1713 PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK),
1714
1715 /* MSIOF1 */
1716 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
1717 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
1718 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
1719 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
1720 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
1721 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
1722 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
1723 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
1724 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
1725
1726 /* DMAC */
1727 PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
1728 PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
1729 PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
1730 PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
1731
1732 /* SDHI0 */
1733 PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK),
1734 PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK),
1735 PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK),
1736 PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK),
1737 PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK),
1738 PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK),
1739 PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK),
1740 PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK),
1741
1742 /* SDHI1 */
1743 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
1744 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
1745 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
1746 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
1747 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
1748 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
1749 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
1750 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
1751
1752 /* MMC */
1753 PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK),
1754 PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK),
1755 PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK),
1756 PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK),
1757 PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK),
1758 PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK),
1759 PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK),
1760 PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK),
1761 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
1762 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
1763
1764 /* IrDA */
1765 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
1766 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
1767
1768 /* TSIF */
1769 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK),
1770 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK),
1771 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK),
1772 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK),
1773
1774 /* IRQ */
1775 PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK),
1776 PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK),
1777 PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK),
1778 PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK),
1779 PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK),
1780 PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK),
1781 PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK),
1782 PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK),
1783 };
1784
1785static struct pinmux_cfg_reg pinmux_config_regs[] = {
1786 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1787 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
1788 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
1789 PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
1790 PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
1791 PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
1792 PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
1793 PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
1794 PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
1795 },
1796 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1797 PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
1798 PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
1799 PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
1800 PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
1801 PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
1802 PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
1803 PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
1804 PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
1805 },
1806 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1807 PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
1808 PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
1809 PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
1810 PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
1811 PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
1812 PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
1813 PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
1814 PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
1815 },
1816 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1817 PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
1818 PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
1819 PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
1820 PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
1821 PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
1822 PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
1823 PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
1824 PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
1825 },
1826 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1827 PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN,
1828 PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN,
1829 PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN,
1830 PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
1831 PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
1832 PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
1833 PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
1834 PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
1835 },
1836 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1837 PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN,
1838 PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN,
1839 PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN,
1840 PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN,
1841 PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN,
1842 PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN,
1843 PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN,
1844 PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN }
1845 },
1846 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1847 0, 0, 0, 0,
1848 0, 0, 0, 0,
1849 PTG5_FN, PTG5_OUT, 0, 0,
1850 PTG4_FN, PTG4_OUT, 0, 0,
1851 PTG3_FN, PTG3_OUT, 0, 0,
1852 PTG2_FN, PTG2_OUT, 0, 0,
1853 PTG1_FN, PTG1_OUT, 0, 0,
1854 PTG0_FN, PTG0_OUT, 0, 0 }
1855 },
1856 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1857 PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN,
1858 PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
1859 PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
1860 PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
1861 PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
1862 PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
1863 PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
1864 PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
1865 },
1866 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1867 PTJ7_FN, PTJ7_OUT, 0, 0,
1868 PTJ6_FN, PTJ6_OUT, 0, 0,
1869 PTJ5_FN, PTJ5_OUT, 0, 0,
1870 0, 0, 0, 0,
1871 PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
1872 PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
1873 PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
1874 PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
1875 },
1876 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1877 PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN,
1878 PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN,
1879 PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN,
1880 PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN,
1881 PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
1882 PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
1883 PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
1884 PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
1885 },
1886 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1887 PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
1888 PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
1889 PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
1890 PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
1891 PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
1892 PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN,
1893 PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN,
1894 PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN }
1895 },
1896 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1897 PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
1898 PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
1899 PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
1900 PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
1901 PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
1902 PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
1903 PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
1904 PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
1905 },
1906 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
1907 PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN,
1908 PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN,
1909 PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN,
1910 PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN,
1911 PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN,
1912 PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN,
1913 PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN,
1914 PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN }
1915 },
1916 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
1917 PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN,
1918 PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN,
1919 PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN,
1920 PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN,
1921 PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN,
1922 PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN,
1923 PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN,
1924 PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
1925 },
1926 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
1927 PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
1928 PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
1929 PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
1930 PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
1931 PTR3_FN, 0, PTR3_IN_PU, PTR3_IN,
1932 PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
1933 PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
1934 PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
1935 },
1936 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
1937 0, 0, 0, 0,
1938 PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN,
1939 PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN,
1940 PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
1941 PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
1942 PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
1943 PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
1944 PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
1945 },
1946 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
1947 PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN,
1948 PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN,
1949 PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN,
1950 PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
1951 PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
1952 PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
1953 PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
1954 PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
1955 },
1956 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
1957 PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN,
1958 PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN,
1959 PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN,
1960 PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
1961 PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
1962 PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
1963 PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
1964 PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
1965 },
1966 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
1967 PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN,
1968 PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN,
1969 PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN,
1970 PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
1971 PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
1972 PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
1973 PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
1974 PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
1975 },
1976 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
1977 PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN,
1978 PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN,
1979 PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN,
1980 PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN,
1981 PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN,
1982 PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN,
1983 PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN,
1984 PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN }
1985 },
1986 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
1987 PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN,
1988 PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
1989 PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN,
1990 PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN,
1991 PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN,
1992 PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN,
1993 PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN,
1994 PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN }
1995 },
1996 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
1997 PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN,
1998 PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN,
1999 PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
2000 PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
2001 PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
2002 PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
2003 PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN,
2004 PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
2005 },
2006 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
2007 PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN,
2008 PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN,
2009 PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN,
2010 PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN,
2011 PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN,
2012 PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN,
2013 PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN,
2014 PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN }
2015 },
2016 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
2017 PSA15_0, PSA15_1,
2018 PSA14_0, PSA14_1,
2019 PSA13_0, PSA13_1,
2020 PSA12_0, PSA12_1,
2021 0, 0,
2022 PSA10_0, PSA10_1,
2023 PSA9_0, PSA9_1,
2024 PSA8_0, PSA8_1,
2025 PSA7_0, PSA7_1,
2026 PSA6_0, PSA6_1,
2027 PSA5_0, PSA5_1,
2028 0, 0,
2029 PSA3_0, PSA3_1,
2030 PSA2_0, PSA2_1,
2031 PSA1_0, PSA1_1,
2032 PSA0_0, PSA0_1}
2033 },
2034 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
2035 0, 0,
2036 PSB14_0, PSB14_1,
2037 PSB13_0, PSB13_1,
2038 PSB12_0, PSB12_1,
2039 PSB11_0, PSB11_1,
2040 PSB10_0, PSB10_1,
2041 PSB9_0, PSB9_1,
2042 PSB8_0, PSB8_1,
2043 PSB7_0, PSB7_1,
2044 PSB6_0, PSB6_1,
2045 PSB5_0, PSB5_1,
2046 PSB4_0, PSB4_1,
2047 PSB3_0, PSB3_1,
2048 PSB2_0, PSB2_1,
2049 PSB1_0, PSB1_1,
2050 PSB0_0, PSB0_1}
2051 },
2052 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
2053 PSC15_0, PSC15_1,
2054 PSC14_0, PSC14_1,
2055 PSC13_0, PSC13_1,
2056 PSC12_0, PSC12_1,
2057 PSC11_0, PSC11_1,
2058 PSC10_0, PSC10_1,
2059 PSC9_0, PSC9_1,
2060 PSC8_0, PSC8_1,
2061 PSC7_0, PSC7_1,
2062 PSC6_0, PSC6_1,
2063 PSC5_0, PSC5_1,
2064 PSC4_0, PSC4_1,
2065 0, 0,
2066 PSC2_0, PSC2_1,
2067 PSC1_0, PSC1_1,
2068 PSC0_0, PSC0_1}
2069 },
2070 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
2071 PSD15_0, PSD15_1,
2072 PSD14_0, PSD14_1,
2073 PSD13_0, PSD13_1,
2074 PSD12_0, PSD12_1,
2075 PSD11_0, PSD11_1,
2076 PSD10_0, PSD10_1,
2077 PSD9_0, PSD9_1,
2078 PSD8_0, PSD8_1,
2079 PSD7_0, PSD7_1,
2080 PSD6_0, PSD6_1,
2081 PSD5_0, PSD5_1,
2082 PSD4_0, PSD4_1,
2083 PSD3_0, PSD3_1,
2084 PSD2_0, PSD2_1,
2085 PSD1_0, PSD1_1,
2086 PSD0_0, PSD0_1}
2087 },
2088 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
2089 PSE15_0, PSE15_1,
2090 PSE14_0, PSE14_1,
2091 PSE13_0, PSE13_1,
2092 PSE12_0, PSE12_1,
2093 PSE11_0, PSE11_1,
2094 PSE10_0, PSE10_1,
2095 PSE9_0, PSE9_1,
2096 PSE8_0, PSE8_1,
2097 PSE7_0, PSE7_1,
2098 PSE6_0, PSE6_1,
2099 PSE5_0, PSE5_1,
2100 PSE4_0, PSE4_1,
2101 PSE3_0, PSE3_1,
2102 PSE2_0, PSE2_1,
2103 PSE1_0, PSE1_1,
2104 PSE0_0, PSE0_1}
2105 },
2106 {}
2107};
2108
2109static struct pinmux_data_reg pinmux_data_regs[] = {
2110 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
2111 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2112 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
2113 },
2114 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
2115 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
2116 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
2117 },
2118 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
2119 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
2120 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
2121 },
2122 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
2123 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
2124 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
2125 },
2126 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
2127 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
2128 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
2129 },
2130 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
2131 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
2132 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
2133 },
2134 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
2135 0, 0, PTG5_DATA, PTG4_DATA,
2136 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
2137 },
2138 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
2139 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
2140 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
2141 },
2142 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
2143 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
2144 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
2145 },
2146 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
2147 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
2148 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
2149 },
2150 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
2151 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
2152 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
2153 },
2154 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
2155 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
2156 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
2157 },
2158 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
2159 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
2160 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
2161 },
2162 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
2163 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
2164 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
2165 },
2166 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
2167 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
2168 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
2169 },
2170 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
2171 0, PTS6_DATA, PTS5_DATA, PTS4_DATA,
2172 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
2173 },
2174 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
2175 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
2176 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
2177 },
2178 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
2179 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
2180 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
2181 },
2182 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
2183 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
2184 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
2185 },
2186 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
2187 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
2188 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
2189 },
2190 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
2191 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
2192 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
2193 },
2194 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
2195 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
2196 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
2197 },
2198 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
2199 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
2200 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
2201 },
2202 { },
2203};
2204
2205static struct pinmux_info sh7724_pinmux_info = {
2206 .name = "sh7724_pfc",
2207 .reserved_id = PINMUX_RESERVED,
2208 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2209 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2210 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2211 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2212 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2213 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2214
2215 .first_gpio = GPIO_PTA7,
2216 .last_gpio = GPIO_FN_INTC_IRQ0,
2217
2218 .gpios = pinmux_gpios,
2219 .cfg_regs = pinmux_config_regs,
2220 .data_regs = pinmux_data_regs,
2221
2222 .gpio_data = pinmux_data,
2223 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2224};
2225
2226static int __init plat_pinmux_setup(void)
2227{
2228 return register_pinmux(&sh7724_pinmux_info);
2229}
2230arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index c1549382c87c..51204dc7ca21 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -12,7 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/uio_driver.h> 14#include <linux/uio_driver.h>
15#include <linux/sh_cmt.h> 15#include <linux/sh_timer.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17 17
18static struct resource iic0_resources[] = { 18static struct resource iic0_resources[] = {
@@ -141,7 +141,7 @@ static struct platform_device jpu_device = {
141 .num_resources = ARRAY_SIZE(jpu_resources), 141 .num_resources = ARRAY_SIZE(jpu_resources),
142}; 142};
143 143
144static struct sh_cmt_config cmt_platform_data = { 144static struct sh_timer_config cmt_platform_data = {
145 .name = "CMT", 145 .name = "CMT",
146 .channel_offset = 0x60, 146 .channel_offset = 0x60,
147 .timer_bit = 5, 147 .timer_bit = 5,
@@ -173,27 +173,123 @@ static struct platform_device cmt_device = {
173 .num_resources = ARRAY_SIZE(cmt_resources), 173 .num_resources = ARRAY_SIZE(cmt_resources),
174}; 174};
175 175
176static struct sh_timer_config tmu0_platform_data = {
177 .name = "TMU0",
178 .channel_offset = 0x04,
179 .timer_bit = 0,
180 .clk = "tmu0",
181 .clockevent_rating = 200,
182};
183
184static struct resource tmu0_resources[] = {
185 [0] = {
186 .name = "TMU0",
187 .start = 0xffd80008,
188 .end = 0xffd80013,
189 .flags = IORESOURCE_MEM,
190 },
191 [1] = {
192 .start = 16,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static struct platform_device tmu0_device = {
198 .name = "sh_tmu",
199 .id = 0,
200 .dev = {
201 .platform_data = &tmu0_platform_data,
202 },
203 .resource = tmu0_resources,
204 .num_resources = ARRAY_SIZE(tmu0_resources),
205};
206
207static struct sh_timer_config tmu1_platform_data = {
208 .name = "TMU1",
209 .channel_offset = 0x10,
210 .timer_bit = 1,
211 .clk = "tmu0",
212 .clocksource_rating = 200,
213};
214
215static struct resource tmu1_resources[] = {
216 [0] = {
217 .name = "TMU1",
218 .start = 0xffd80014,
219 .end = 0xffd8001f,
220 .flags = IORESOURCE_MEM,
221 },
222 [1] = {
223 .start = 17,
224 .flags = IORESOURCE_IRQ,
225 },
226};
227
228static struct platform_device tmu1_device = {
229 .name = "sh_tmu",
230 .id = 1,
231 .dev = {
232 .platform_data = &tmu1_platform_data,
233 },
234 .resource = tmu1_resources,
235 .num_resources = ARRAY_SIZE(tmu1_resources),
236};
237
238static struct sh_timer_config tmu2_platform_data = {
239 .name = "TMU2",
240 .channel_offset = 0x1c,
241 .timer_bit = 2,
242 .clk = "tmu0",
243};
244
245static struct resource tmu2_resources[] = {
246 [0] = {
247 .name = "TMU2",
248 .start = 0xffd80020,
249 .end = 0xffd8002b,
250 .flags = IORESOURCE_MEM,
251 },
252 [1] = {
253 .start = 18,
254 .flags = IORESOURCE_IRQ,
255 },
256};
257
258static struct platform_device tmu2_device = {
259 .name = "sh_tmu",
260 .id = 2,
261 .dev = {
262 .platform_data = &tmu2_platform_data,
263 },
264 .resource = tmu2_resources,
265 .num_resources = ARRAY_SIZE(tmu2_resources),
266};
267
176static struct plat_sci_port sci_platform_data[] = { 268static struct plat_sci_port sci_platform_data[] = {
177 { 269 {
178 .mapbase = 0xffe00000, 270 .mapbase = 0xffe00000,
179 .flags = UPF_BOOT_AUTOCONF, 271 .flags = UPF_BOOT_AUTOCONF,
180 .type = PORT_SCIF, 272 .type = PORT_SCIF,
181 .irqs = { 80, 80, 80, 80 }, 273 .irqs = { 80, 80, 80, 80 },
274 .clk = "scif0",
182 }, { 275 }, {
183 .mapbase = 0xffe10000, 276 .mapbase = 0xffe10000,
184 .flags = UPF_BOOT_AUTOCONF, 277 .flags = UPF_BOOT_AUTOCONF,
185 .type = PORT_SCIF, 278 .type = PORT_SCIF,
186 .irqs = { 81, 81, 81, 81 }, 279 .irqs = { 81, 81, 81, 81 },
280 .clk = "scif1",
187 }, { 281 }, {
188 .mapbase = 0xffe20000, 282 .mapbase = 0xffe20000,
189 .flags = UPF_BOOT_AUTOCONF, 283 .flags = UPF_BOOT_AUTOCONF,
190 .type = PORT_SCIF, 284 .type = PORT_SCIF,
191 .irqs = { 82, 82, 82, 82 }, 285 .irqs = { 82, 82, 82, 82 },
286 .clk = "scif2",
192 }, { 287 }, {
193 .mapbase = 0xffe30000, 288 .mapbase = 0xffe30000,
194 .flags = UPF_BOOT_AUTOCONF, 289 .flags = UPF_BOOT_AUTOCONF,
195 .type = PORT_SCIF, 290 .type = PORT_SCIF,
196 .irqs = { 83, 83, 83, 83 }, 291 .irqs = { 83, 83, 83, 83 },
292 .clk = "scif3",
197 }, { 293 }, {
198 .flags = 0, 294 .flags = 0,
199 } 295 }
@@ -209,6 +305,9 @@ static struct platform_device sci_device = {
209 305
210static struct platform_device *sh7343_devices[] __initdata = { 306static struct platform_device *sh7343_devices[] __initdata = {
211 &cmt_device, 307 &cmt_device,
308 &tmu0_device,
309 &tmu1_device,
310 &tmu2_device,
212 &iic0_device, 311 &iic0_device,
213 &iic1_device, 312 &iic1_device,
214 &sci_device, 313 &sci_device,
@@ -234,6 +333,19 @@ static int __init sh7343_devices_setup(void)
234} 333}
235__initcall(sh7343_devices_setup); 334__initcall(sh7343_devices_setup);
236 335
336static struct platform_device *sh7343_early_devices[] __initdata = {
337 &cmt_device,
338 &tmu0_device,
339 &tmu1_device,
340 &tmu2_device,
341};
342
343void __init plat_early_device_setup(void)
344{
345 early_platform_add_devices(sh7343_early_devices,
346 ARRAY_SIZE(sh7343_early_devices));
347}
348
237enum { 349enum {
238 UNUSED = 0, 350 UNUSED = 0,
239 351
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 93ecf8ed5c6c..04de0fa85120 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -14,7 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
17#include <linux/sh_cmt.h> 17#include <linux/sh_timer.h>
18#include <asm/clock.h> 18#include <asm/clock.h>
19 19
20static struct resource iic_resources[] = { 20static struct resource iic_resources[] = {
@@ -148,7 +148,7 @@ static struct platform_device veu1_device = {
148 .num_resources = ARRAY_SIZE(veu1_resources), 148 .num_resources = ARRAY_SIZE(veu1_resources),
149}; 149};
150 150
151static struct sh_cmt_config cmt_platform_data = { 151static struct sh_timer_config cmt_platform_data = {
152 .name = "CMT", 152 .name = "CMT",
153 .channel_offset = 0x60, 153 .channel_offset = 0x60,
154 .timer_bit = 5, 154 .timer_bit = 5,
@@ -180,12 +180,105 @@ static struct platform_device cmt_device = {
180 .num_resources = ARRAY_SIZE(cmt_resources), 180 .num_resources = ARRAY_SIZE(cmt_resources),
181}; 181};
182 182
183static struct sh_timer_config tmu0_platform_data = {
184 .name = "TMU0",
185 .channel_offset = 0x04,
186 .timer_bit = 0,
187 .clk = "tmu0",
188 .clockevent_rating = 200,
189};
190
191static struct resource tmu0_resources[] = {
192 [0] = {
193 .name = "TMU0",
194 .start = 0xffd80008,
195 .end = 0xffd80013,
196 .flags = IORESOURCE_MEM,
197 },
198 [1] = {
199 .start = 16,
200 .flags = IORESOURCE_IRQ,
201 },
202};
203
204static struct platform_device tmu0_device = {
205 .name = "sh_tmu",
206 .id = 0,
207 .dev = {
208 .platform_data = &tmu0_platform_data,
209 },
210 .resource = tmu0_resources,
211 .num_resources = ARRAY_SIZE(tmu0_resources),
212};
213
214static struct sh_timer_config tmu1_platform_data = {
215 .name = "TMU1",
216 .channel_offset = 0x10,
217 .timer_bit = 1,
218 .clk = "tmu0",
219 .clocksource_rating = 200,
220};
221
222static struct resource tmu1_resources[] = {
223 [0] = {
224 .name = "TMU1",
225 .start = 0xffd80014,
226 .end = 0xffd8001f,
227 .flags = IORESOURCE_MEM,
228 },
229 [1] = {
230 .start = 17,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct platform_device tmu1_device = {
236 .name = "sh_tmu",
237 .id = 1,
238 .dev = {
239 .platform_data = &tmu1_platform_data,
240 },
241 .resource = tmu1_resources,
242 .num_resources = ARRAY_SIZE(tmu1_resources),
243};
244
245static struct sh_timer_config tmu2_platform_data = {
246 .name = "TMU2",
247 .channel_offset = 0x1c,
248 .timer_bit = 2,
249 .clk = "tmu0",
250};
251
252static struct resource tmu2_resources[] = {
253 [0] = {
254 .name = "TMU2",
255 .start = 0xffd80020,
256 .end = 0xffd8002b,
257 .flags = IORESOURCE_MEM,
258 },
259 [1] = {
260 .start = 18,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device tmu2_device = {
266 .name = "sh_tmu",
267 .id = 2,
268 .dev = {
269 .platform_data = &tmu2_platform_data,
270 },
271 .resource = tmu2_resources,
272 .num_resources = ARRAY_SIZE(tmu2_resources),
273};
274
183static struct plat_sci_port sci_platform_data[] = { 275static struct plat_sci_port sci_platform_data[] = {
184 { 276 {
185 .mapbase = 0xffe00000, 277 .mapbase = 0xffe00000,
186 .flags = UPF_BOOT_AUTOCONF, 278 .flags = UPF_BOOT_AUTOCONF,
187 .type = PORT_SCIF, 279 .type = PORT_SCIF,
188 .irqs = { 80, 80, 80, 80 }, 280 .irqs = { 80, 80, 80, 80 },
281 .clk = "scif0",
189 }, { 282 }, {
190 .flags = 0, 283 .flags = 0,
191 } 284 }
@@ -201,6 +294,9 @@ static struct platform_device sci_device = {
201 294
202static struct platform_device *sh7366_devices[] __initdata = { 295static struct platform_device *sh7366_devices[] __initdata = {
203 &cmt_device, 296 &cmt_device,
297 &tmu0_device,
298 &tmu1_device,
299 &tmu2_device,
204 &iic_device, 300 &iic_device,
205 &sci_device, 301 &sci_device,
206 &usb_host_device, 302 &usb_host_device,
@@ -226,6 +322,19 @@ static int __init sh7366_devices_setup(void)
226} 322}
227__initcall(sh7366_devices_setup); 323__initcall(sh7366_devices_setup);
228 324
325static struct platform_device *sh7366_early_devices[] __initdata = {
326 &cmt_device,
327 &tmu0_device,
328 &tmu1_device,
329 &tmu2_device,
330};
331
332void __init plat_early_device_setup(void)
333{
334 early_platform_add_devices(sh7366_early_devices,
335 ARRAY_SIZE(sh7366_early_devices));
336}
337
229enum { 338enum {
230 UNUSED=0, 339 UNUSED=0,
231 340
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 406747f07dc0..5d6247fecd63 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,7 +13,7 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h> 16#include <linux/sh_timer.h>
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/mmzone.h> 18#include <asm/mmzone.h>
19 19
@@ -177,13 +177,13 @@ static struct platform_device jpu_device = {
177 .num_resources = ARRAY_SIZE(jpu_resources), 177 .num_resources = ARRAY_SIZE(jpu_resources),
178}; 178};
179 179
180static struct sh_cmt_config cmt_platform_data = { 180static struct sh_timer_config cmt_platform_data = {
181 .name = "CMT", 181 .name = "CMT",
182 .channel_offset = 0x60, 182 .channel_offset = 0x60,
183 .timer_bit = 5, 183 .timer_bit = 5,
184 .clk = "cmt0", 184 .clk = "cmt0",
185 .clockevent_rating = 125, 185 .clockevent_rating = 125,
186 .clocksource_rating = 200, 186 .clocksource_rating = 125,
187}; 187};
188 188
189static struct resource cmt_resources[] = { 189static struct resource cmt_resources[] = {
@@ -209,24 +209,119 @@ static struct platform_device cmt_device = {
209 .num_resources = ARRAY_SIZE(cmt_resources), 209 .num_resources = ARRAY_SIZE(cmt_resources),
210}; 210};
211 211
212static struct sh_timer_config tmu0_platform_data = {
213 .name = "TMU0",
214 .channel_offset = 0x04,
215 .timer_bit = 0,
216 .clk = "tmu0",
217 .clockevent_rating = 200,
218};
219
220static struct resource tmu0_resources[] = {
221 [0] = {
222 .name = "TMU0",
223 .start = 0xffd80008,
224 .end = 0xffd80013,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = 16,
229 .flags = IORESOURCE_IRQ,
230 },
231};
232
233static struct platform_device tmu0_device = {
234 .name = "sh_tmu",
235 .id = 0,
236 .dev = {
237 .platform_data = &tmu0_platform_data,
238 },
239 .resource = tmu0_resources,
240 .num_resources = ARRAY_SIZE(tmu0_resources),
241};
242
243static struct sh_timer_config tmu1_platform_data = {
244 .name = "TMU1",
245 .channel_offset = 0x10,
246 .timer_bit = 1,
247 .clk = "tmu0",
248 .clocksource_rating = 200,
249};
250
251static struct resource tmu1_resources[] = {
252 [0] = {
253 .name = "TMU1",
254 .start = 0xffd80014,
255 .end = 0xffd8001f,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = 17,
260 .flags = IORESOURCE_IRQ,
261 },
262};
263
264static struct platform_device tmu1_device = {
265 .name = "sh_tmu",
266 .id = 1,
267 .dev = {
268 .platform_data = &tmu1_platform_data,
269 },
270 .resource = tmu1_resources,
271 .num_resources = ARRAY_SIZE(tmu1_resources),
272};
273
274static struct sh_timer_config tmu2_platform_data = {
275 .name = "TMU2",
276 .channel_offset = 0x1c,
277 .timer_bit = 2,
278 .clk = "tmu0",
279};
280
281static struct resource tmu2_resources[] = {
282 [0] = {
283 .name = "TMU2",
284 .start = 0xffd80020,
285 .end = 0xffd8002b,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = 18,
290 .flags = IORESOURCE_IRQ,
291 },
292};
293
294static struct platform_device tmu2_device = {
295 .name = "sh_tmu",
296 .id = 2,
297 .dev = {
298 .platform_data = &tmu2_platform_data,
299 },
300 .resource = tmu2_resources,
301 .num_resources = ARRAY_SIZE(tmu2_resources),
302};
303
212static struct plat_sci_port sci_platform_data[] = { 304static struct plat_sci_port sci_platform_data[] = {
213 { 305 {
214 .mapbase = 0xffe00000, 306 .mapbase = 0xffe00000,
215 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
216 .type = PORT_SCIF, 308 .type = PORT_SCIF,
217 .irqs = { 80, 80, 80, 80 }, 309 .irqs = { 80, 80, 80, 80 },
310 .clk = "scif0",
218 }, 311 },
219 { 312 {
220 .mapbase = 0xffe10000, 313 .mapbase = 0xffe10000,
221 .flags = UPF_BOOT_AUTOCONF, 314 .flags = UPF_BOOT_AUTOCONF,
222 .type = PORT_SCIF, 315 .type = PORT_SCIF,
223 .irqs = { 81, 81, 81, 81 }, 316 .irqs = { 81, 81, 81, 81 },
317 .clk = "scif1",
224 }, 318 },
225 { 319 {
226 .mapbase = 0xffe20000, 320 .mapbase = 0xffe20000,
227 .flags = UPF_BOOT_AUTOCONF, 321 .flags = UPF_BOOT_AUTOCONF,
228 .type = PORT_SCIF, 322 .type = PORT_SCIF,
229 .irqs = { 82, 82, 82, 82 }, 323 .irqs = { 82, 82, 82, 82 },
324 .clk = "scif2",
230 }, 325 },
231 { 326 {
232 .flags = 0, 327 .flags = 0,
@@ -243,6 +338,9 @@ static struct platform_device sci_device = {
243 338
244static struct platform_device *sh7722_devices[] __initdata = { 339static struct platform_device *sh7722_devices[] __initdata = {
245 &cmt_device, 340 &cmt_device,
341 &tmu0_device,
342 &tmu1_device,
343 &tmu2_device,
246 &rtc_device, 344 &rtc_device,
247 &usbf_device, 345 &usbf_device,
248 &iic_device, 346 &iic_device,
@@ -269,6 +367,19 @@ static int __init sh7722_devices_setup(void)
269} 367}
270__initcall(sh7722_devices_setup); 368__initcall(sh7722_devices_setup);
271 369
370static struct platform_device *sh7722_early_devices[] __initdata = {
371 &cmt_device,
372 &tmu0_device,
373 &tmu1_device,
374 &tmu2_device,
375};
376
377void __init plat_early_device_setup(void)
378{
379 early_platform_add_devices(sh7722_early_devices,
380 ARRAY_SIZE(sh7722_early_devices));
381}
382
272enum { 383enum {
273 UNUSED=0, 384 UNUSED=0,
274 385
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a800466b938c..1429fc5e4286 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,7 +13,7 @@
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h> 16#include <linux/sh_timer.h>
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/mmzone.h> 18#include <asm/mmzone.h>
19 19
@@ -101,13 +101,13 @@ static struct platform_device veu1_device = {
101 .num_resources = ARRAY_SIZE(veu1_resources), 101 .num_resources = ARRAY_SIZE(veu1_resources),
102}; 102};
103 103
104static struct sh_cmt_config cmt_platform_data = { 104static struct sh_timer_config cmt_platform_data = {
105 .name = "CMT", 105 .name = "CMT",
106 .channel_offset = 0x60, 106 .channel_offset = 0x60,
107 .timer_bit = 5, 107 .timer_bit = 5,
108 .clk = "cmt0", 108 .clk = "cmt0",
109 .clockevent_rating = 125, 109 .clockevent_rating = 125,
110 .clocksource_rating = 200, 110 .clocksource_rating = 125,
111}; 111};
112 112
113static struct resource cmt_resources[] = { 113static struct resource cmt_resources[] = {
@@ -133,37 +133,225 @@ static struct platform_device cmt_device = {
133 .num_resources = ARRAY_SIZE(cmt_resources), 133 .num_resources = ARRAY_SIZE(cmt_resources),
134}; 134};
135 135
136static struct sh_timer_config tmu0_platform_data = {
137 .name = "TMU0",
138 .channel_offset = 0x04,
139 .timer_bit = 0,
140 .clk = "tmu0",
141 .clockevent_rating = 200,
142};
143
144static struct resource tmu0_resources[] = {
145 [0] = {
146 .name = "TMU0",
147 .start = 0xffd80008,
148 .end = 0xffd80013,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = 16,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device tmu0_device = {
158 .name = "sh_tmu",
159 .id = 0,
160 .dev = {
161 .platform_data = &tmu0_platform_data,
162 },
163 .resource = tmu0_resources,
164 .num_resources = ARRAY_SIZE(tmu0_resources),
165};
166
167static struct sh_timer_config tmu1_platform_data = {
168 .name = "TMU1",
169 .channel_offset = 0x10,
170 .timer_bit = 1,
171 .clk = "tmu0",
172 .clocksource_rating = 200,
173};
174
175static struct resource tmu1_resources[] = {
176 [0] = {
177 .name = "TMU1",
178 .start = 0xffd80014,
179 .end = 0xffd8001f,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .start = 17,
184 .flags = IORESOURCE_IRQ,
185 },
186};
187
188static struct platform_device tmu1_device = {
189 .name = "sh_tmu",
190 .id = 1,
191 .dev = {
192 .platform_data = &tmu1_platform_data,
193 },
194 .resource = tmu1_resources,
195 .num_resources = ARRAY_SIZE(tmu1_resources),
196};
197
198static struct sh_timer_config tmu2_platform_data = {
199 .name = "TMU2",
200 .channel_offset = 0x1c,
201 .timer_bit = 2,
202 .clk = "tmu0",
203};
204
205static struct resource tmu2_resources[] = {
206 [0] = {
207 .name = "TMU2",
208 .start = 0xffd80020,
209 .end = 0xffd8002b,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = 18,
214 .flags = IORESOURCE_IRQ,
215 },
216};
217
218static struct platform_device tmu2_device = {
219 .name = "sh_tmu",
220 .id = 2,
221 .dev = {
222 .platform_data = &tmu2_platform_data,
223 },
224 .resource = tmu2_resources,
225 .num_resources = ARRAY_SIZE(tmu2_resources),
226};
227
228static struct sh_timer_config tmu3_platform_data = {
229 .name = "TMU3",
230 .channel_offset = 0x04,
231 .timer_bit = 0,
232 .clk = "tmu1",
233};
234
235static struct resource tmu3_resources[] = {
236 [0] = {
237 .name = "TMU3",
238 .start = 0xffd90008,
239 .end = 0xffd90013,
240 .flags = IORESOURCE_MEM,
241 },
242 [1] = {
243 .start = 57,
244 .flags = IORESOURCE_IRQ,
245 },
246};
247
248static struct platform_device tmu3_device = {
249 .name = "sh_tmu",
250 .id = 3,
251 .dev = {
252 .platform_data = &tmu3_platform_data,
253 },
254 .resource = tmu3_resources,
255 .num_resources = ARRAY_SIZE(tmu3_resources),
256};
257
258static struct sh_timer_config tmu4_platform_data = {
259 .name = "TMU4",
260 .channel_offset = 0x10,
261 .timer_bit = 1,
262 .clk = "tmu1",
263};
264
265static struct resource tmu4_resources[] = {
266 [0] = {
267 .name = "TMU4",
268 .start = 0xffd90014,
269 .end = 0xffd9001f,
270 .flags = IORESOURCE_MEM,
271 },
272 [1] = {
273 .start = 58,
274 .flags = IORESOURCE_IRQ,
275 },
276};
277
278static struct platform_device tmu4_device = {
279 .name = "sh_tmu",
280 .id = 4,
281 .dev = {
282 .platform_data = &tmu4_platform_data,
283 },
284 .resource = tmu4_resources,
285 .num_resources = ARRAY_SIZE(tmu4_resources),
286};
287
288static struct sh_timer_config tmu5_platform_data = {
289 .name = "TMU5",
290 .channel_offset = 0x1c,
291 .timer_bit = 2,
292 .clk = "tmu1",
293};
294
295static struct resource tmu5_resources[] = {
296 [0] = {
297 .name = "TMU5",
298 .start = 0xffd90020,
299 .end = 0xffd9002b,
300 .flags = IORESOURCE_MEM,
301 },
302 [1] = {
303 .start = 57,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308static struct platform_device tmu5_device = {
309 .name = "sh_tmu",
310 .id = 5,
311 .dev = {
312 .platform_data = &tmu5_platform_data,
313 },
314 .resource = tmu5_resources,
315 .num_resources = ARRAY_SIZE(tmu5_resources),
316};
317
136static struct plat_sci_port sci_platform_data[] = { 318static struct plat_sci_port sci_platform_data[] = {
137 { 319 {
138 .mapbase = 0xffe00000, 320 .mapbase = 0xffe00000,
139 .flags = UPF_BOOT_AUTOCONF, 321 .flags = UPF_BOOT_AUTOCONF,
140 .type = PORT_SCIF, 322 .type = PORT_SCIF,
141 .irqs = { 80, 80, 80, 80 }, 323 .irqs = { 80, 80, 80, 80 },
324 .clk = "scif0",
142 },{ 325 },{
143 .mapbase = 0xffe10000, 326 .mapbase = 0xffe10000,
144 .flags = UPF_BOOT_AUTOCONF, 327 .flags = UPF_BOOT_AUTOCONF,
145 .type = PORT_SCIF, 328 .type = PORT_SCIF,
146 .irqs = { 81, 81, 81, 81 }, 329 .irqs = { 81, 81, 81, 81 },
330 .clk = "scif1",
147 },{ 331 },{
148 .mapbase = 0xffe20000, 332 .mapbase = 0xffe20000,
149 .flags = UPF_BOOT_AUTOCONF, 333 .flags = UPF_BOOT_AUTOCONF,
150 .type = PORT_SCIF, 334 .type = PORT_SCIF,
151 .irqs = { 82, 82, 82, 82 }, 335 .irqs = { 82, 82, 82, 82 },
336 .clk = "scif2",
152 },{ 337 },{
153 .mapbase = 0xa4e30000, 338 .mapbase = 0xa4e30000,
154 .flags = UPF_BOOT_AUTOCONF, 339 .flags = UPF_BOOT_AUTOCONF,
155 .type = PORT_SCIFA, 340 .type = PORT_SCIFA,
156 .irqs = { 56, 56, 56, 56 }, 341 .irqs = { 56, 56, 56, 56 },
342 .clk = "scif3",
157 },{ 343 },{
158 .mapbase = 0xa4e40000, 344 .mapbase = 0xa4e40000,
159 .flags = UPF_BOOT_AUTOCONF, 345 .flags = UPF_BOOT_AUTOCONF,
160 .type = PORT_SCIFA, 346 .type = PORT_SCIFA,
161 .irqs = { 88, 88, 88, 88 }, 347 .irqs = { 88, 88, 88, 88 },
348 .clk = "scif4",
162 },{ 349 },{
163 .mapbase = 0xa4e50000, 350 .mapbase = 0xa4e50000,
164 .flags = UPF_BOOT_AUTOCONF, 351 .flags = UPF_BOOT_AUTOCONF,
165 .type = PORT_SCIFA, 352 .type = PORT_SCIFA,
166 .irqs = { 109, 109, 109, 109 }, 353 .irqs = { 109, 109, 109, 109 },
354 .clk = "scif5",
167 }, { 355 }, {
168 .flags = 0, 356 .flags = 0,
169 } 357 }
@@ -255,6 +443,12 @@ static struct platform_device iic_device = {
255 443
256static struct platform_device *sh7723_devices[] __initdata = { 444static struct platform_device *sh7723_devices[] __initdata = {
257 &cmt_device, 445 &cmt_device,
446 &tmu0_device,
447 &tmu1_device,
448 &tmu2_device,
449 &tmu3_device,
450 &tmu4_device,
451 &tmu5_device,
258 &sci_device, 452 &sci_device,
259 &rtc_device, 453 &rtc_device,
260 &iic_device, 454 &iic_device,
@@ -280,6 +474,22 @@ static int __init sh7723_devices_setup(void)
280} 474}
281__initcall(sh7723_devices_setup); 475__initcall(sh7723_devices_setup);
282 476
477static struct platform_device *sh7723_early_devices[] __initdata = {
478 &cmt_device,
479 &tmu0_device,
480 &tmu1_device,
481 &tmu2_device,
482 &tmu3_device,
483 &tmu4_device,
484 &tmu5_device,
485};
486
487void __init plat_early_device_setup(void)
488{
489 early_platform_add_devices(sh7723_early_devices,
490 ARRAY_SIZE(sh7723_early_devices));
491}
492
283enum { 493enum {
284 UNUSED=0, 494 UNUSED=0,
285 495
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
new file mode 100644
index 000000000000..852f8104f03a
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -0,0 +1,757 @@
1/*
2 * SH7724 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/mm.h>
19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h>
21#include <linux/sh_timer.h>
22#include <linux/io.h>
23#include <asm/clock.h>
24#include <asm/mmzone.h>
25
26/* Serial */
27static struct plat_sci_port sci_platform_data[] = {
28 {
29 .mapbase = 0xffe00000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCIF,
32 .irqs = { 80, 80, 80, 80 },
33 .clk = "scif0",
34 }, {
35 .mapbase = 0xffe10000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 81, 81, 81, 81 },
39 .clk = "scif1",
40 }, {
41 .mapbase = 0xffe20000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 82, 82, 82, 82 },
45 .clk = "scif2",
46 }, {
47 .mapbase = 0xa4e30000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIFA,
50 .irqs = { 56, 56, 56, 56 },
51 .clk = "scif3",
52 }, {
53 .mapbase = 0xa4e40000,
54 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIFA,
56 .irqs = { 88, 88, 88, 88 },
57 .clk = "scif4",
58 }, {
59 .mapbase = 0xa4e50000,
60 .flags = UPF_BOOT_AUTOCONF,
61 .type = PORT_SCIFA,
62 .irqs = { 109, 109, 109, 109 },
63 .clk = "scif5",
64 }, {
65 .flags = 0,
66 }
67};
68
69static struct platform_device sci_device = {
70 .name = "sh-sci",
71 .id = -1,
72 .dev = {
73 .platform_data = sci_platform_data,
74 },
75};
76
77/* RTC */
78static struct resource rtc_resources[] = {
79 [0] = {
80 .start = 0xa465fec0,
81 .end = 0xa465fec0 + 0x58 - 1,
82 .flags = IORESOURCE_IO,
83 },
84 [1] = {
85 /* Period IRQ */
86 .start = 69,
87 .flags = IORESOURCE_IRQ,
88 },
89 [2] = {
90 /* Carry IRQ */
91 .start = 70,
92 .flags = IORESOURCE_IRQ,
93 },
94 [3] = {
95 /* Alarm IRQ */
96 .start = 68,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static struct platform_device rtc_device = {
102 .name = "sh-rtc",
103 .id = -1,
104 .num_resources = ARRAY_SIZE(rtc_resources),
105 .resource = rtc_resources,
106};
107
108/* I2C0 */
109static struct resource iic0_resources[] = {
110 [0] = {
111 .name = "IIC0",
112 .start = 0x04470000,
113 .end = 0x04470018 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = 96,
118 .end = 99,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct platform_device iic0_device = {
124 .name = "i2c-sh_mobile",
125 .id = 0, /* "i2c0" clock */
126 .num_resources = ARRAY_SIZE(iic0_resources),
127 .resource = iic0_resources,
128};
129
130/* I2C1 */
131static struct resource iic1_resources[] = {
132 [0] = {
133 .name = "IIC1",
134 .start = 0x04750000,
135 .end = 0x04750018 - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = 92,
140 .end = 95,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static struct platform_device iic1_device = {
146 .name = "i2c-sh_mobile",
147 .id = 1, /* "i2c1" clock */
148 .num_resources = ARRAY_SIZE(iic1_resources),
149 .resource = iic1_resources,
150};
151
152/* VPU */
153static struct uio_info vpu_platform_data = {
154 .name = "VPU5F",
155 .version = "0",
156 .irq = 60,
157};
158
159static struct resource vpu_resources[] = {
160 [0] = {
161 .name = "VPU",
162 .start = 0xfe900000,
163 .end = 0xfe902807,
164 .flags = IORESOURCE_MEM,
165 },
166 [1] = {
167 /* place holder for contiguous memory */
168 },
169};
170
171static struct platform_device vpu_device = {
172 .name = "uio_pdrv_genirq",
173 .id = 0,
174 .dev = {
175 .platform_data = &vpu_platform_data,
176 },
177 .resource = vpu_resources,
178 .num_resources = ARRAY_SIZE(vpu_resources),
179};
180
181/* VEU0 */
182static struct uio_info veu0_platform_data = {
183 .name = "VEU3F0",
184 .version = "0",
185 .irq = 83,
186};
187
188static struct resource veu0_resources[] = {
189 [0] = {
190 .name = "VEU3F0",
191 .start = 0xfe920000,
192 .end = 0xfe9200cb - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 /* place holder for contiguous memory */
197 },
198};
199
200static struct platform_device veu0_device = {
201 .name = "uio_pdrv_genirq",
202 .id = 1,
203 .dev = {
204 .platform_data = &veu0_platform_data,
205 },
206 .resource = veu0_resources,
207 .num_resources = ARRAY_SIZE(veu0_resources),
208};
209
210/* VEU1 */
211static struct uio_info veu1_platform_data = {
212 .name = "VEU3F1",
213 .version = "0",
214 .irq = 54,
215};
216
217static struct resource veu1_resources[] = {
218 [0] = {
219 .name = "VEU3F1",
220 .start = 0xfe924000,
221 .end = 0xfe9240cb - 1,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 /* place holder for contiguous memory */
226 },
227};
228
229static struct platform_device veu1_device = {
230 .name = "uio_pdrv_genirq",
231 .id = 2,
232 .dev = {
233 .platform_data = &veu1_platform_data,
234 },
235 .resource = veu1_resources,
236 .num_resources = ARRAY_SIZE(veu1_resources),
237};
238
239static struct sh_timer_config cmt_platform_data = {
240 .name = "CMT",
241 .channel_offset = 0x60,
242 .timer_bit = 5,
243 .clk = "cmt0",
244 .clockevent_rating = 125,
245 .clocksource_rating = 200,
246};
247
248static struct resource cmt_resources[] = {
249 [0] = {
250 .name = "CMT",
251 .start = 0x044a0060,
252 .end = 0x044a006b,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .start = 104,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device cmt_device = {
262 .name = "sh_cmt",
263 .id = 0,
264 .dev = {
265 .platform_data = &cmt_platform_data,
266 },
267 .resource = cmt_resources,
268 .num_resources = ARRAY_SIZE(cmt_resources),
269};
270
271static struct sh_timer_config tmu0_platform_data = {
272 .name = "TMU0",
273 .channel_offset = 0x04,
274 .timer_bit = 0,
275 .clk = "tmu0",
276 .clockevent_rating = 200,
277};
278
279static struct resource tmu0_resources[] = {
280 [0] = {
281 .name = "TMU0",
282 .start = 0xffd80008,
283 .end = 0xffd80013,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 .start = 16,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device tmu0_device = {
293 .name = "sh_tmu",
294 .id = 0,
295 .dev = {
296 .platform_data = &tmu0_platform_data,
297 },
298 .resource = tmu0_resources,
299 .num_resources = ARRAY_SIZE(tmu0_resources),
300};
301
302static struct sh_timer_config tmu1_platform_data = {
303 .name = "TMU1",
304 .channel_offset = 0x10,
305 .timer_bit = 1,
306 .clk = "tmu0",
307 .clocksource_rating = 200,
308};
309
310static struct resource tmu1_resources[] = {
311 [0] = {
312 .name = "TMU1",
313 .start = 0xffd80014,
314 .end = 0xffd8001f,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = 17,
319 .flags = IORESOURCE_IRQ,
320 },
321};
322
323static struct platform_device tmu1_device = {
324 .name = "sh_tmu",
325 .id = 1,
326 .dev = {
327 .platform_data = &tmu1_platform_data,
328 },
329 .resource = tmu1_resources,
330 .num_resources = ARRAY_SIZE(tmu1_resources),
331};
332
333static struct sh_timer_config tmu2_platform_data = {
334 .name = "TMU2",
335 .channel_offset = 0x1c,
336 .timer_bit = 2,
337 .clk = "tmu0",
338};
339
340static struct resource tmu2_resources[] = {
341 [0] = {
342 .name = "TMU2",
343 .start = 0xffd80020,
344 .end = 0xffd8002b,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = 18,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
353static struct platform_device tmu2_device = {
354 .name = "sh_tmu",
355 .id = 2,
356 .dev = {
357 .platform_data = &tmu2_platform_data,
358 },
359 .resource = tmu2_resources,
360 .num_resources = ARRAY_SIZE(tmu2_resources),
361};
362
363
364static struct sh_timer_config tmu3_platform_data = {
365 .name = "TMU3",
366 .channel_offset = 0x04,
367 .timer_bit = 0,
368 .clk = "tmu1",
369};
370
371static struct resource tmu3_resources[] = {
372 [0] = {
373 .name = "TMU3",
374 .start = 0xffd90008,
375 .end = 0xffd90013,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = 57,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device tmu3_device = {
385 .name = "sh_tmu",
386 .id = 3,
387 .dev = {
388 .platform_data = &tmu3_platform_data,
389 },
390 .resource = tmu3_resources,
391 .num_resources = ARRAY_SIZE(tmu3_resources),
392};
393
394static struct sh_timer_config tmu4_platform_data = {
395 .name = "TMU4",
396 .channel_offset = 0x10,
397 .timer_bit = 1,
398 .clk = "tmu1",
399};
400
401static struct resource tmu4_resources[] = {
402 [0] = {
403 .name = "TMU4",
404 .start = 0xffd90014,
405 .end = 0xffd9001f,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = 58,
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device tmu4_device = {
415 .name = "sh_tmu",
416 .id = 4,
417 .dev = {
418 .platform_data = &tmu4_platform_data,
419 },
420 .resource = tmu4_resources,
421 .num_resources = ARRAY_SIZE(tmu4_resources),
422};
423
424static struct sh_timer_config tmu5_platform_data = {
425 .name = "TMU5",
426 .channel_offset = 0x1c,
427 .timer_bit = 2,
428 .clk = "tmu1",
429};
430
431static struct resource tmu5_resources[] = {
432 [0] = {
433 .name = "TMU5",
434 .start = 0xffd90020,
435 .end = 0xffd9002b,
436 .flags = IORESOURCE_MEM,
437 },
438 [1] = {
439 .start = 57,
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct platform_device tmu5_device = {
445 .name = "sh_tmu",
446 .id = 5,
447 .dev = {
448 .platform_data = &tmu5_platform_data,
449 },
450 .resource = tmu5_resources,
451 .num_resources = ARRAY_SIZE(tmu5_resources),
452};
453
454static struct platform_device *sh7724_devices[] __initdata = {
455 &cmt_device,
456 &tmu0_device,
457 &tmu1_device,
458 &tmu2_device,
459 &tmu3_device,
460 &tmu4_device,
461 &tmu5_device,
462 &sci_device,
463 &rtc_device,
464 &iic0_device,
465 &iic1_device,
466 &vpu_device,
467 &veu0_device,
468 &veu1_device,
469};
470
471static int __init sh7724_devices_setup(void)
472{
473 clk_always_enable("vpu0"); /* VPU */
474 clk_always_enable("veu1"); /* VEU3F1 */
475 clk_always_enable("veu0"); /* VEU3F0 */
476
477 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
478 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
479 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
480
481 return platform_add_devices(sh7724_devices,
482 ARRAY_SIZE(sh7724_devices));
483}
484device_initcall(sh7724_devices_setup);
485
486static struct platform_device *sh7724_early_devices[] __initdata = {
487 &cmt_device,
488 &tmu0_device,
489 &tmu1_device,
490 &tmu2_device,
491 &tmu3_device,
492 &tmu4_device,
493 &tmu5_device,
494};
495
496void __init plat_early_device_setup(void)
497{
498 early_platform_add_devices(sh7724_early_devices,
499 ARRAY_SIZE(sh7724_early_devices));
500}
501
502enum {
503 UNUSED = 0,
504
505 /* interrupt sources */
506 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
507 HUDI,
508 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
509 _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
510 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
511 VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
512 SCIFA_SCIFA0,
513 VPU_VPUI,
514 TPU_TPUI,
515 CEU21I,
516 BEU21I,
517 USB_USI0,
518 ATAPI,
519 RTC_ATI, RTC_PRI, RTC_CUI,
520 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
521 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
522 KEYSC_KEYI,
523 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
524 VEU3F0I,
525 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
526 SPU_SPUI0, SPU_SPUI1,
527 SCIFA_SCIFA1,
528/* ICB_ICBI, */
529 ETHI,
530 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
531 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
532 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
533 CMT_CMTI,
534 TSIF_TSIFI,
535/* ICB_LMBI, */
536 FSI_FSI,
537 SCIFA_SCIFA2,
538 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
539 IRDA_IRDAI,
540 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
541 JPU_JPUI,
542 MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
543 LCDC_LCDCI,
544 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
545
546 /* interrupt groups */
547 DMAC1A, _2DG, DMAC0A, VIO, RTC,
548 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
549};
550
551static struct intc_vect vectors[] __initdata = {
552 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
553 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
554 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
555 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
556
557 INTC_VECT(DMAC1A_DEI0, 0x700),
558 INTC_VECT(DMAC1A_DEI1, 0x720),
559 INTC_VECT(DMAC1A_DEI2, 0x740),
560 INTC_VECT(DMAC1A_DEI3, 0x760),
561
562 INTC_VECT(_2DG_TRI, 0x780),
563 INTC_VECT(_2DG_INI, 0x7A0),
564 INTC_VECT(_2DG_CEI, 0x7C0),
565 INTC_VECT(_2DG_BRK, 0x7E0),
566
567 INTC_VECT(DMAC0A_DEI0, 0x800),
568 INTC_VECT(DMAC0A_DEI1, 0x820),
569 INTC_VECT(DMAC0A_DEI2, 0x840),
570 INTC_VECT(DMAC0A_DEI3, 0x860),
571
572 INTC_VECT(VIO_CEU20I, 0x880),
573 INTC_VECT(VIO_BEU20I, 0x8A0),
574 INTC_VECT(VIO_VEU3F1, 0x8C0),
575 INTC_VECT(VIO_VOUI, 0x8E0),
576
577 INTC_VECT(SCIFA_SCIFA0, 0x900),
578 INTC_VECT(VPU_VPUI, 0x980),
579 INTC_VECT(TPU_TPUI, 0x9A0),
580 INTC_VECT(CEU21I, 0x9E0),
581 INTC_VECT(BEU21I, 0xA00),
582 INTC_VECT(USB_USI0, 0xA20),
583 INTC_VECT(ATAPI, 0xA60),
584
585 INTC_VECT(RTC_ATI, 0xA80),
586 INTC_VECT(RTC_PRI, 0xAA0),
587 INTC_VECT(RTC_CUI, 0xAC0),
588
589 INTC_VECT(DMAC1B_DEI4, 0xB00),
590 INTC_VECT(DMAC1B_DEI5, 0xB20),
591 INTC_VECT(DMAC1B_DADERR, 0xB40),
592
593 INTC_VECT(DMAC0B_DEI4, 0xB80),
594 INTC_VECT(DMAC0B_DEI5, 0xBA0),
595 INTC_VECT(DMAC0B_DADERR, 0xBC0),
596
597 INTC_VECT(KEYSC_KEYI, 0xBE0),
598 INTC_VECT(SCIF_SCIF0, 0xC00),
599 INTC_VECT(SCIF_SCIF1, 0xC20),
600 INTC_VECT(SCIF_SCIF2, 0xC40),
601 INTC_VECT(VEU3F0I, 0xC60),
602 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
603 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
604 INTC_VECT(SPU_SPUI0, 0xCC0),
605 INTC_VECT(SPU_SPUI1, 0xCE0),
606 INTC_VECT(SCIFA_SCIFA1, 0xD00),
607
608/* INTC_VECT(ICB_ICBI, 0xD20), */
609 INTC_VECT(ETHI, 0xD60),
610
611 INTC_VECT(I2C1_ALI, 0xD80),
612 INTC_VECT(I2C1_TACKI, 0xDA0),
613 INTC_VECT(I2C1_WAITI, 0xDC0),
614 INTC_VECT(I2C1_DTEI, 0xDE0),
615
616 INTC_VECT(I2C0_ALI, 0xE00),
617 INTC_VECT(I2C0_TACKI, 0xE20),
618 INTC_VECT(I2C0_WAITI, 0xE40),
619 INTC_VECT(I2C0_DTEI, 0xE60),
620
621 INTC_VECT(SDHI0_SDHII0, 0xE80),
622 INTC_VECT(SDHI0_SDHII1, 0xEA0),
623 INTC_VECT(SDHI0_SDHII2, 0xEC0),
624
625 INTC_VECT(CMT_CMTI, 0xF00),
626 INTC_VECT(TSIF_TSIFI, 0xF20),
627/* INTC_VECT(ICB_LMBI, 0xF60), */
628 INTC_VECT(FSI_FSI, 0xF80),
629 INTC_VECT(SCIFA_SCIFA2, 0xFA0),
630
631 INTC_VECT(TMU0_TUNI0, 0x400),
632 INTC_VECT(TMU0_TUNI1, 0x420),
633 INTC_VECT(TMU0_TUNI2, 0x440),
634
635 INTC_VECT(IRDA_IRDAI, 0x480),
636
637 INTC_VECT(SDHI1_SDHII0, 0x4E0),
638 INTC_VECT(SDHI1_SDHII1, 0x500),
639 INTC_VECT(SDHI1_SDHII2, 0x520),
640
641 INTC_VECT(JPU_JPUI, 0x560),
642
643 INTC_VECT(MMC_MMCI0, 0x580),
644 INTC_VECT(MMC_MMCI1, 0x5A0),
645 INTC_VECT(MMC_MMCI2, 0x5C0),
646
647 INTC_VECT(LCDC_LCDCI, 0xF40),
648
649 INTC_VECT(TMU1_TUNI0, 0x920),
650 INTC_VECT(TMU1_TUNI1, 0x940),
651 INTC_VECT(TMU1_TUNI2, 0x960),
652};
653
654static struct intc_group groups[] __initdata = {
655 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
656 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
657 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
658 INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
659 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
660 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
661 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
662 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
663 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
664 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
665 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
666 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
667 INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
668};
669
670/* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
671/* very bad manual !! */
672static struct intc_mask_reg mask_registers[] __initdata = {
673 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
674 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
675 /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
676 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
677 { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
678 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
679 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
680 { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
681 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
682 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
683 SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
684 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
685 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
686 JPU_JPUI, 0, 0, LCDC_LCDCI } },
687 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
688 { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
689 VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
690 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
691 { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
692 CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
693 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
694 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
695 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
696 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
697 { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
698 0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
699 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
700 { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
701 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
702 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
703 0, RTC_ATI, RTC_PRI, RTC_CUI } },
704 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
705 { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
706 0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
707 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
708 { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
709 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
710 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
711};
712
713static struct intc_prio_reg prio_registers[] __initdata = {
714 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
715 TMU0_TUNI2, IRDA_IRDAI } },
716 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
717 DMAC1A, BEU21I } },
718 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
719 TMU1_TUNI2, SPU } },
720 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
721 { 0xa4080010, 0, 16, 4, /* IPRE */
722 { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
723 VPU_VPUI } },
724 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
725 USB_USI0, CMT_CMTI } },
726 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
727 SCIF_SCIF2, VEU3F0I } },
728 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
729 I2C1, I2C0 } },
730 { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
731 TSIF_TSIFI, _2DG/*ICB?*/ } },
732 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
733 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
734 { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
735 TPU_TPUI, /*2DDMAC*/0 } },
736 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
737 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
738};
739
740static struct intc_sense_reg sense_registers[] __initdata = {
741 { 0xa414001c, 16, 2, /* ICR1 */
742 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
743};
744
745static struct intc_mask_reg ack_registers[] __initdata = {
746 { 0xa4140024, 0, 8, /* INTREQ00 */
747 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
748};
749
750static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
751 mask_registers, prio_registers, sense_registers,
752 ack_registers);
753
754void __init plat_irq_setup(void)
755{
756 register_intc_controller(&intc_desc);
757}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index bdf0f61ae1ed..c91f34c9aa83 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -12,6 +12,7 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/sh_timer.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/serial_sci.h> 17#include <linux/serial_sci.h>
17 18
@@ -113,7 +114,195 @@ static struct platform_device usbf_device = {
113 .resource = usbf_resources, 114 .resource = usbf_resources,
114}; 115};
115 116
117static struct sh_timer_config tmu0_platform_data = {
118 .name = "TMU0",
119 .channel_offset = 0x04,
120 .timer_bit = 0,
121 .clk = "module_clk",
122 .clockevent_rating = 200,
123};
124
125static struct resource tmu0_resources[] = {
126 [0] = {
127 .name = "TMU0",
128 .start = 0xffd80008,
129 .end = 0xffd80013,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = 28,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device tmu0_device = {
139 .name = "sh_tmu",
140 .id = 0,
141 .dev = {
142 .platform_data = &tmu0_platform_data,
143 },
144 .resource = tmu0_resources,
145 .num_resources = ARRAY_SIZE(tmu0_resources),
146};
147
148static struct sh_timer_config tmu1_platform_data = {
149 .name = "TMU1",
150 .channel_offset = 0x10,
151 .timer_bit = 1,
152 .clk = "module_clk",
153 .clocksource_rating = 200,
154};
155
156static struct resource tmu1_resources[] = {
157 [0] = {
158 .name = "TMU1",
159 .start = 0xffd80014,
160 .end = 0xffd8001f,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 29,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device tmu1_device = {
170 .name = "sh_tmu",
171 .id = 1,
172 .dev = {
173 .platform_data = &tmu1_platform_data,
174 },
175 .resource = tmu1_resources,
176 .num_resources = ARRAY_SIZE(tmu1_resources),
177};
178
179static struct sh_timer_config tmu2_platform_data = {
180 .name = "TMU2",
181 .channel_offset = 0x1c,
182 .timer_bit = 2,
183 .clk = "module_clk",
184};
185
186static struct resource tmu2_resources[] = {
187 [0] = {
188 .name = "TMU2",
189 .start = 0xffd80020,
190 .end = 0xffd8002f,
191 .flags = IORESOURCE_MEM,
192 },
193 [1] = {
194 .start = 30,
195 .flags = IORESOURCE_IRQ,
196 },
197};
198
199static struct platform_device tmu2_device = {
200 .name = "sh_tmu",
201 .id = 2,
202 .dev = {
203 .platform_data = &tmu2_platform_data,
204 },
205 .resource = tmu2_resources,
206 .num_resources = ARRAY_SIZE(tmu2_resources),
207};
208
209static struct sh_timer_config tmu3_platform_data = {
210 .name = "TMU3",
211 .channel_offset = 0x04,
212 .timer_bit = 0,
213 .clk = "module_clk",
214};
215
216static struct resource tmu3_resources[] = {
217 [0] = {
218 .name = "TMU3",
219 .start = 0xffd88008,
220 .end = 0xffd88013,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = 96,
225 .flags = IORESOURCE_IRQ,
226 },
227};
228
229static struct platform_device tmu3_device = {
230 .name = "sh_tmu",
231 .id = 3,
232 .dev = {
233 .platform_data = &tmu3_platform_data,
234 },
235 .resource = tmu3_resources,
236 .num_resources = ARRAY_SIZE(tmu3_resources),
237};
238
239static struct sh_timer_config tmu4_platform_data = {
240 .name = "TMU4",
241 .channel_offset = 0x10,
242 .timer_bit = 1,
243 .clk = "module_clk",
244};
245
246static struct resource tmu4_resources[] = {
247 [0] = {
248 .name = "TMU4",
249 .start = 0xffd88014,
250 .end = 0xffd8801f,
251 .flags = IORESOURCE_MEM,
252 },
253 [1] = {
254 .start = 97,
255 .flags = IORESOURCE_IRQ,
256 },
257};
258
259static struct platform_device tmu4_device = {
260 .name = "sh_tmu",
261 .id = 4,
262 .dev = {
263 .platform_data = &tmu4_platform_data,
264 },
265 .resource = tmu4_resources,
266 .num_resources = ARRAY_SIZE(tmu4_resources),
267};
268
269static struct sh_timer_config tmu5_platform_data = {
270 .name = "TMU5",
271 .channel_offset = 0x1c,
272 .timer_bit = 2,
273 .clk = "module_clk",
274};
275
276static struct resource tmu5_resources[] = {
277 [0] = {
278 .name = "TMU5",
279 .start = 0xffd88020,
280 .end = 0xffd8802b,
281 .flags = IORESOURCE_MEM,
282 },
283 [1] = {
284 .start = 98,
285 .flags = IORESOURCE_IRQ,
286 },
287};
288
289static struct platform_device tmu5_device = {
290 .name = "sh_tmu",
291 .id = 5,
292 .dev = {
293 .platform_data = &tmu5_platform_data,
294 },
295 .resource = tmu5_resources,
296 .num_resources = ARRAY_SIZE(tmu5_resources),
297};
298
116static struct platform_device *sh7763_devices[] __initdata = { 299static struct platform_device *sh7763_devices[] __initdata = {
300 &tmu0_device,
301 &tmu1_device,
302 &tmu2_device,
303 &tmu3_device,
304 &tmu4_device,
305 &tmu5_device,
117 &rtc_device, 306 &rtc_device,
118 &sci_device, 307 &sci_device,
119 &usb_ohci_device, 308 &usb_ohci_device,
@@ -127,6 +316,21 @@ static int __init sh7763_devices_setup(void)
127} 316}
128__initcall(sh7763_devices_setup); 317__initcall(sh7763_devices_setup);
129 318
319static struct platform_device *sh7763_early_devices[] __initdata = {
320 &tmu0_device,
321 &tmu1_device,
322 &tmu2_device,
323 &tmu3_device,
324 &tmu4_device,
325 &tmu5_device,
326};
327
328void __init plat_early_device_setup(void)
329{
330 early_platform_add_devices(sh7763_early_devices,
331 ARRAY_SIZE(sh7763_early_devices));
332}
333
130enum { 334enum {
131 UNUSED = 0, 335 UNUSED = 0,
132 336
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index b73578ee295d..0feba41d218d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -11,6 +11,8 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
15#include <linux/io.h>
14 16
15static struct plat_sci_port sci_platform_data[] = { 17static struct plat_sci_port sci_platform_data[] = {
16 { 18 {
@@ -76,7 +78,288 @@ static struct platform_device sci_device = {
76 }, 78 },
77}; 79};
78 80
81static struct sh_timer_config tmu0_platform_data = {
82 .name = "TMU0",
83 .channel_offset = 0x04,
84 .timer_bit = 0,
85 .clk = "module_clk",
86 .clockevent_rating = 200,
87};
88
89static struct resource tmu0_resources[] = {
90 [0] = {
91 .name = "TMU0",
92 .start = 0xffd80008,
93 .end = 0xffd80013,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = 16,
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102static struct platform_device tmu0_device = {
103 .name = "sh_tmu",
104 .id = 0,
105 .dev = {
106 .platform_data = &tmu0_platform_data,
107 },
108 .resource = tmu0_resources,
109 .num_resources = ARRAY_SIZE(tmu0_resources),
110};
111
112static struct sh_timer_config tmu1_platform_data = {
113 .name = "TMU1",
114 .channel_offset = 0x10,
115 .timer_bit = 1,
116 .clk = "module_clk",
117 .clocksource_rating = 200,
118};
119
120static struct resource tmu1_resources[] = {
121 [0] = {
122 .name = "TMU1",
123 .start = 0xffd80014,
124 .end = 0xffd8001f,
125 .flags = IORESOURCE_MEM,
126 },
127 [1] = {
128 .start = 17,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct platform_device tmu1_device = {
134 .name = "sh_tmu",
135 .id = 1,
136 .dev = {
137 .platform_data = &tmu1_platform_data,
138 },
139 .resource = tmu1_resources,
140 .num_resources = ARRAY_SIZE(tmu1_resources),
141};
142
143static struct sh_timer_config tmu2_platform_data = {
144 .name = "TMU2",
145 .channel_offset = 0x1c,
146 .timer_bit = 2,
147 .clk = "module_clk",
148};
149
150static struct resource tmu2_resources[] = {
151 [0] = {
152 .name = "TMU2",
153 .start = 0xffd80020,
154 .end = 0xffd8002f,
155 .flags = IORESOURCE_MEM,
156 },
157 [1] = {
158 .start = 18,
159 .flags = IORESOURCE_IRQ,
160 },
161};
162
163static struct platform_device tmu2_device = {
164 .name = "sh_tmu",
165 .id = 2,
166 .dev = {
167 .platform_data = &tmu2_platform_data,
168 },
169 .resource = tmu2_resources,
170 .num_resources = ARRAY_SIZE(tmu2_resources),
171};
172
173static struct sh_timer_config tmu3_platform_data = {
174 .name = "TMU3",
175 .channel_offset = 0x04,
176 .timer_bit = 0,
177 .clk = "module_clk",
178};
179
180static struct resource tmu3_resources[] = {
181 [0] = {
182 .name = "TMU3",
183 .start = 0xffd81008,
184 .end = 0xffd81013,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = 19,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static struct platform_device tmu3_device = {
194 .name = "sh_tmu",
195 .id = 3,
196 .dev = {
197 .platform_data = &tmu3_platform_data,
198 },
199 .resource = tmu3_resources,
200 .num_resources = ARRAY_SIZE(tmu3_resources),
201};
202
203static struct sh_timer_config tmu4_platform_data = {
204 .name = "TMU4",
205 .channel_offset = 0x10,
206 .timer_bit = 1,
207 .clk = "module_clk",
208};
209
210static struct resource tmu4_resources[] = {
211 [0] = {
212 .name = "TMU4",
213 .start = 0xffd81014,
214 .end = 0xffd8101f,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = 20,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device tmu4_device = {
224 .name = "sh_tmu",
225 .id = 4,
226 .dev = {
227 .platform_data = &tmu4_platform_data,
228 },
229 .resource = tmu4_resources,
230 .num_resources = ARRAY_SIZE(tmu4_resources),
231};
232
233static struct sh_timer_config tmu5_platform_data = {
234 .name = "TMU5",
235 .channel_offset = 0x1c,
236 .timer_bit = 2,
237 .clk = "module_clk",
238};
239
240static struct resource tmu5_resources[] = {
241 [0] = {
242 .name = "TMU5",
243 .start = 0xffd81020,
244 .end = 0xffd8102f,
245 .flags = IORESOURCE_MEM,
246 },
247 [1] = {
248 .start = 21,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device tmu5_device = {
254 .name = "sh_tmu",
255 .id = 5,
256 .dev = {
257 .platform_data = &tmu5_platform_data,
258 },
259 .resource = tmu5_resources,
260 .num_resources = ARRAY_SIZE(tmu5_resources),
261};
262
263static struct sh_timer_config tmu6_platform_data = {
264 .name = "TMU6",
265 .channel_offset = 0x04,
266 .timer_bit = 0,
267 .clk = "module_clk",
268};
269
270static struct resource tmu6_resources[] = {
271 [0] = {
272 .name = "TMU6",
273 .start = 0xffd82008,
274 .end = 0xffd82013,
275 .flags = IORESOURCE_MEM,
276 },
277 [1] = {
278 .start = 22,
279 .flags = IORESOURCE_IRQ,
280 },
281};
282
283static struct platform_device tmu6_device = {
284 .name = "sh_tmu",
285 .id = 6,
286 .dev = {
287 .platform_data = &tmu6_platform_data,
288 },
289 .resource = tmu6_resources,
290 .num_resources = ARRAY_SIZE(tmu6_resources),
291};
292
293static struct sh_timer_config tmu7_platform_data = {
294 .name = "TMU7",
295 .channel_offset = 0x10,
296 .timer_bit = 1,
297 .clk = "module_clk",
298};
299
300static struct resource tmu7_resources[] = {
301 [0] = {
302 .name = "TMU7",
303 .start = 0xffd82014,
304 .end = 0xffd8201f,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
308 .start = 23,
309 .flags = IORESOURCE_IRQ,
310 },
311};
312
313static struct platform_device tmu7_device = {
314 .name = "sh_tmu",
315 .id = 7,
316 .dev = {
317 .platform_data = &tmu7_platform_data,
318 },
319 .resource = tmu7_resources,
320 .num_resources = ARRAY_SIZE(tmu7_resources),
321};
322
323static struct sh_timer_config tmu8_platform_data = {
324 .name = "TMU8",
325 .channel_offset = 0x1c,
326 .timer_bit = 2,
327 .clk = "module_clk",
328};
329
330static struct resource tmu8_resources[] = {
331 [0] = {
332 .name = "TMU8",
333 .start = 0xffd82020,
334 .end = 0xffd8202b,
335 .flags = IORESOURCE_MEM,
336 },
337 [1] = {
338 .start = 24,
339 .flags = IORESOURCE_IRQ,
340 },
341};
342
343static struct platform_device tmu8_device = {
344 .name = "sh_tmu",
345 .id = 8,
346 .dev = {
347 .platform_data = &tmu8_platform_data,
348 },
349 .resource = tmu8_resources,
350 .num_resources = ARRAY_SIZE(tmu8_resources),
351};
352
79static struct platform_device *sh7770_devices[] __initdata = { 353static struct platform_device *sh7770_devices[] __initdata = {
354 &tmu0_device,
355 &tmu1_device,
356 &tmu2_device,
357 &tmu3_device,
358 &tmu4_device,
359 &tmu5_device,
360 &tmu6_device,
361 &tmu7_device,
362 &tmu8_device,
80 &sci_device, 363 &sci_device,
81}; 364};
82 365
@@ -87,6 +370,269 @@ static int __init sh7770_devices_setup(void)
87} 370}
88__initcall(sh7770_devices_setup); 371__initcall(sh7770_devices_setup);
89 372
373static struct platform_device *sh7770_early_devices[] __initdata = {
374 &tmu0_device,
375 &tmu1_device,
376 &tmu2_device,
377 &tmu3_device,
378 &tmu4_device,
379 &tmu5_device,
380 &tmu6_device,
381 &tmu7_device,
382 &tmu8_device,
383};
384
385void __init plat_early_device_setup(void)
386{
387 early_platform_add_devices(sh7770_early_devices,
388 ARRAY_SIZE(sh7770_early_devices));
389}
390
391enum {
392 UNUSED = 0,
393
394 /* interrupt sources */
395 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
396 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
397 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
398 IRL_HHLL, IRL_HHLH, IRL_HHHL,
399
400 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
401
402 GPIO,
403 TMU0, TMU1, TMU2, TMU2_TICPI,
404 TMU3, TMU4, TMU5, TMU5_TICPI,
405 TMU6, TMU7, TMU8,
406 HAC, IPI, SPDIF, HUDI, I2C,
407 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
408 I2S0, I2S1, I2S2, I2S3,
409 SRC_RX, SRC_TX, SRC_SPDIF,
410 DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
411 GFX3D_MBX, GFX3D_DMAC,
412 EXBUS_ATA,
413 SPI0, SPI1,
414 SCIF089, SCIF1234, SCIF567,
415 ADC,
416 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
417 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
418 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
419
420 /* interrupt groups */
421 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
422};
423
424static struct intc_vect vectors[] __initdata = {
425 INTC_VECT(GPIO, 0x3e0),
426 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
427 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
428 INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
429 INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
430 INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
431 INTC_VECT(TMU8, 0x540),
432 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
433 INTC_VECT(SPDIF, 0x5e0),
434 INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
435 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
436 INTC_VECT(DMAC0_DMINT2, 0x680),
437 INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
438 INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
439 INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
440 INTC_VECT(SRC_SPDIF, 0x760),
441 INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
442 INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
443 INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
444 INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
445 INTC_VECT(GFX2D, 0x8c0),
446 INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
447 INTC_VECT(EXBUS_ATA, 0x940),
448 INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
449 INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
450 INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
451 INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
452 INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
453 INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
454 INTC_VECT(ADC, 0xb20),
455 INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
456 INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
457 INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
458 INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
459 INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
460 INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
461 INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
462 INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
463 INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
464 INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
465 INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
466 INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
467 INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
468 INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
469 INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
470 INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
471};
472
473static struct intc_group groups[] __initdata = {
474 INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
475 TMU5_TICPI, TMU6, TMU7, TMU8),
476 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
477 INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
478 INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
479 INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
480 INTC_GROUP(SPI, SPI0, SPI1),
481 INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
482 INTC_GROUP(BBDMAC,
483 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
484 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
485 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
486};
487
488static struct intc_mask_reg mask_registers[] __initdata = {
489 { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
490 { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
491 GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
492 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
493};
494
495static struct intc_prio_reg prio_registers[] __initdata = {
496 { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
497 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
498 { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
499 { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
500 { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
501 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
502 { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
503 { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
504 { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
505 { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
506 { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
507 { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
508 { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
509 { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
510 { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
511 { TMU1, TMU2, TMU2_TICPI, TMU3 } },
512 { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
513 { TMU4, TMU5, TMU5_TICPI, TMU6 } },
514 { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
515 { TMU7, TMU8 } },
516};
517
518static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
519 mask_registers, prio_registers, NULL);
520
521/* Support for external interrupt pins in IRQ mode */
522static struct intc_vect irq_vectors[] __initdata = {
523 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
524 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
525 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
526};
527
528static struct intc_mask_reg irq_mask_registers[] __initdata = {
529 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
530 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
531};
532
533static struct intc_prio_reg irq_prio_registers[] __initdata = {
534 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
535 IRQ4, IRQ5, } },
536};
537
538static struct intc_sense_reg irq_sense_registers[] __initdata = {
539 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
540 IRQ4, IRQ5, } },
541};
542
543static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
544 NULL, irq_mask_registers, irq_prio_registers,
545 irq_sense_registers);
546
547/* External interrupt pins in IRL mode */
548static struct intc_vect irl_vectors[] __initdata = {
549 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
550 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
551 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
552 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
553 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
554 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
555 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
556 INTC_VECT(IRL_HHHL, 0x3c0),
557};
558
559static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
560 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
561 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
562 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
563 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
564 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
565};
566
567static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
568 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
569 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
570 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
571 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
572 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
573 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
574};
575
576static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
577 NULL, irl7654_mask_registers, NULL, NULL);
578
579static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
580 NULL, irl3210_mask_registers, NULL, NULL);
581
582#define INTC_ICR0 0xffd00000
583#define INTC_INTMSK0 0xffd00044
584#define INTC_INTMSK1 0xffd00048
585#define INTC_INTMSK2 0xffd40080
586#define INTC_INTMSKCLR1 0xffd00068
587#define INTC_INTMSKCLR2 0xffd40084
588
90void __init plat_irq_setup(void) 589void __init plat_irq_setup(void)
91{ 590{
591 /* disable IRQ7-0 */
592 ctrl_outl(0xff000000, INTC_INTMSK0);
593
594 /* disable IRL3-0 + IRL7-4 */
595 ctrl_outl(0xc0000000, INTC_INTMSK1);
596 ctrl_outl(0xfffefffe, INTC_INTMSK2);
597
598 /* select IRL mode for IRL3-0 + IRL7-4 */
599 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
600
601 /* disable holding function, ie enable "SH-4 Mode" */
602 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
603
604 register_intc_controller(&intc_desc);
605}
606
607void __init plat_irq_setup_pins(int mode)
608{
609 switch (mode) {
610 case IRQ_MODE_IRQ:
611 /* select IRQ mode for IRL3-0 + IRL7-4 */
612 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
613 register_intc_controller(&intc_irq_desc);
614 break;
615 case IRQ_MODE_IRL7654:
616 /* enable IRL7-4 but don't provide any masking */
617 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
618 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
619 break;
620 case IRQ_MODE_IRL3210:
621 /* enable IRL0-3 but don't provide any masking */
622 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
623 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
624 break;
625 case IRQ_MODE_IRL7654_MASK:
626 /* enable IRL7-4 and mask using cpu intc controller */
627 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
628 register_intc_controller(&intc_irl7654_desc);
629 break;
630 case IRQ_MODE_IRL3210_MASK:
631 /* enable IRL0-3 and mask using cpu intc controller */
632 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
633 register_intc_controller(&intc_irl3210_desc);
634 break;
635 default:
636 BUG();
637 }
92} 638}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 6f7227cd65bf..f1df02095062 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -12,6 +12,189 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16
17static struct sh_timer_config tmu0_platform_data = {
18 .name = "TMU0",
19 .channel_offset = 0x04,
20 .timer_bit = 0,
21 .clk = "module_clk",
22 .clockevent_rating = 200,
23};
24
25static struct resource tmu0_resources[] = {
26 [0] = {
27 .name = "TMU0",
28 .start = 0xffd80008,
29 .end = 0xffd80013,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = 28,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38static struct platform_device tmu0_device = {
39 .name = "sh_tmu",
40 .id = 0,
41 .dev = {
42 .platform_data = &tmu0_platform_data,
43 },
44 .resource = tmu0_resources,
45 .num_resources = ARRAY_SIZE(tmu0_resources),
46};
47
48static struct sh_timer_config tmu1_platform_data = {
49 .name = "TMU1",
50 .channel_offset = 0x10,
51 .timer_bit = 1,
52 .clk = "module_clk",
53 .clocksource_rating = 200,
54};
55
56static struct resource tmu1_resources[] = {
57 [0] = {
58 .name = "TMU1",
59 .start = 0xffd80014,
60 .end = 0xffd8001f,
61 .flags = IORESOURCE_MEM,
62 },
63 [1] = {
64 .start = 29,
65 .flags = IORESOURCE_IRQ,
66 },
67};
68
69static struct platform_device tmu1_device = {
70 .name = "sh_tmu",
71 .id = 1,
72 .dev = {
73 .platform_data = &tmu1_platform_data,
74 },
75 .resource = tmu1_resources,
76 .num_resources = ARRAY_SIZE(tmu1_resources),
77};
78
79static struct sh_timer_config tmu2_platform_data = {
80 .name = "TMU2",
81 .channel_offset = 0x1c,
82 .timer_bit = 2,
83 .clk = "module_clk",
84};
85
86static struct resource tmu2_resources[] = {
87 [0] = {
88 .name = "TMU2",
89 .start = 0xffd80020,
90 .end = 0xffd8002f,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = 30,
95 .flags = IORESOURCE_IRQ,
96 },
97};
98
99static struct platform_device tmu2_device = {
100 .name = "sh_tmu",
101 .id = 2,
102 .dev = {
103 .platform_data = &tmu2_platform_data,
104 },
105 .resource = tmu2_resources,
106 .num_resources = ARRAY_SIZE(tmu2_resources),
107};
108
109static struct sh_timer_config tmu3_platform_data = {
110 .name = "TMU3",
111 .channel_offset = 0x04,
112 .timer_bit = 0,
113 .clk = "module_clk",
114};
115
116static struct resource tmu3_resources[] = {
117 [0] = {
118 .name = "TMU3",
119 .start = 0xffdc0008,
120 .end = 0xffdc0013,
121 .flags = IORESOURCE_MEM,
122 },
123 [1] = {
124 .start = 96,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device tmu3_device = {
130 .name = "sh_tmu",
131 .id = 3,
132 .dev = {
133 .platform_data = &tmu3_platform_data,
134 },
135 .resource = tmu3_resources,
136 .num_resources = ARRAY_SIZE(tmu3_resources),
137};
138
139static struct sh_timer_config tmu4_platform_data = {
140 .name = "TMU4",
141 .channel_offset = 0x10,
142 .timer_bit = 1,
143 .clk = "module_clk",
144};
145
146static struct resource tmu4_resources[] = {
147 [0] = {
148 .name = "TMU4",
149 .start = 0xffdc0014,
150 .end = 0xffdc001f,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = 97,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device tmu4_device = {
160 .name = "sh_tmu",
161 .id = 4,
162 .dev = {
163 .platform_data = &tmu4_platform_data,
164 },
165 .resource = tmu4_resources,
166 .num_resources = ARRAY_SIZE(tmu4_resources),
167};
168
169static struct sh_timer_config tmu5_platform_data = {
170 .name = "TMU5",
171 .channel_offset = 0x1c,
172 .timer_bit = 2,
173 .clk = "module_clk",
174};
175
176static struct resource tmu5_resources[] = {
177 [0] = {
178 .name = "TMU5",
179 .start = 0xffdc0020,
180 .end = 0xffdc002b,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = 98,
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device tmu5_device = {
190 .name = "sh_tmu",
191 .id = 5,
192 .dev = {
193 .platform_data = &tmu5_platform_data,
194 },
195 .resource = tmu5_resources,
196 .num_resources = ARRAY_SIZE(tmu5_resources),
197};
15 198
16static struct resource rtc_resources[] = { 199static struct resource rtc_resources[] = {
17 [0] = { 200 [0] = {
@@ -58,6 +241,12 @@ static struct platform_device sci_device = {
58}; 241};
59 242
60static struct platform_device *sh7780_devices[] __initdata = { 243static struct platform_device *sh7780_devices[] __initdata = {
244 &tmu0_device,
245 &tmu1_device,
246 &tmu2_device,
247 &tmu3_device,
248 &tmu4_device,
249 &tmu5_device,
61 &rtc_device, 250 &rtc_device,
62 &sci_device, 251 &sci_device,
63}; 252};
@@ -69,6 +258,21 @@ static int __init sh7780_devices_setup(void)
69} 258}
70__initcall(sh7780_devices_setup); 259__initcall(sh7780_devices_setup);
71 260
261static struct platform_device *sh7780_early_devices[] __initdata = {
262 &tmu0_device,
263 &tmu1_device,
264 &tmu2_device,
265 &tmu3_device,
266 &tmu4_device,
267 &tmu5_device,
268};
269
270void __init plat_early_device_setup(void)
271{
272 early_platform_add_devices(sh7780_early_devices,
273 ARRAY_SIZE(sh7780_early_devices));
274}
275
72enum { 276enum {
73 UNUSED = 0, 277 UNUSED = 0,
74 278
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index d80802a49dbd..dc5d3e507a21 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -13,8 +13,191 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_timer.h>
16#include <asm/mmzone.h> 17#include <asm/mmzone.h>
17 18
19static struct sh_timer_config tmu0_platform_data = {
20 .name = "TMU0",
21 .channel_offset = 0x04,
22 .timer_bit = 0,
23 .clk = "module_clk",
24 .clockevent_rating = 200,
25};
26
27static struct resource tmu0_resources[] = {
28 [0] = {
29 .name = "TMU0",
30 .start = 0xffd80008,
31 .end = 0xffd80013,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = 28,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static struct platform_device tmu0_device = {
41 .name = "sh_tmu",
42 .id = 0,
43 .dev = {
44 .platform_data = &tmu0_platform_data,
45 },
46 .resource = tmu0_resources,
47 .num_resources = ARRAY_SIZE(tmu0_resources),
48};
49
50static struct sh_timer_config tmu1_platform_data = {
51 .name = "TMU1",
52 .channel_offset = 0x10,
53 .timer_bit = 1,
54 .clk = "module_clk",
55 .clocksource_rating = 200,
56};
57
58static struct resource tmu1_resources[] = {
59 [0] = {
60 .name = "TMU1",
61 .start = 0xffd80014,
62 .end = 0xffd8001f,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .start = 29,
67 .flags = IORESOURCE_IRQ,
68 },
69};
70
71static struct platform_device tmu1_device = {
72 .name = "sh_tmu",
73 .id = 1,
74 .dev = {
75 .platform_data = &tmu1_platform_data,
76 },
77 .resource = tmu1_resources,
78 .num_resources = ARRAY_SIZE(tmu1_resources),
79};
80
81static struct sh_timer_config tmu2_platform_data = {
82 .name = "TMU2",
83 .channel_offset = 0x1c,
84 .timer_bit = 2,
85 .clk = "module_clk",
86};
87
88static struct resource tmu2_resources[] = {
89 [0] = {
90 .name = "TMU2",
91 .start = 0xffd80020,
92 .end = 0xffd8002f,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = 30,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static struct platform_device tmu2_device = {
102 .name = "sh_tmu",
103 .id = 2,
104 .dev = {
105 .platform_data = &tmu2_platform_data,
106 },
107 .resource = tmu2_resources,
108 .num_resources = ARRAY_SIZE(tmu2_resources),
109};
110
111static struct sh_timer_config tmu3_platform_data = {
112 .name = "TMU3",
113 .channel_offset = 0x04,
114 .timer_bit = 0,
115 .clk = "module_clk",
116};
117
118static struct resource tmu3_resources[] = {
119 [0] = {
120 .name = "TMU3",
121 .start = 0xffdc0008,
122 .end = 0xffdc0013,
123 .flags = IORESOURCE_MEM,
124 },
125 [1] = {
126 .start = 96,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct platform_device tmu3_device = {
132 .name = "sh_tmu",
133 .id = 3,
134 .dev = {
135 .platform_data = &tmu3_platform_data,
136 },
137 .resource = tmu3_resources,
138 .num_resources = ARRAY_SIZE(tmu3_resources),
139};
140
141static struct sh_timer_config tmu4_platform_data = {
142 .name = "TMU4",
143 .channel_offset = 0x10,
144 .timer_bit = 1,
145 .clk = "module_clk",
146};
147
148static struct resource tmu4_resources[] = {
149 [0] = {
150 .name = "TMU4",
151 .start = 0xffdc0014,
152 .end = 0xffdc001f,
153 .flags = IORESOURCE_MEM,
154 },
155 [1] = {
156 .start = 97,
157 .flags = IORESOURCE_IRQ,
158 },
159};
160
161static struct platform_device tmu4_device = {
162 .name = "sh_tmu",
163 .id = 4,
164 .dev = {
165 .platform_data = &tmu4_platform_data,
166 },
167 .resource = tmu4_resources,
168 .num_resources = ARRAY_SIZE(tmu4_resources),
169};
170
171static struct sh_timer_config tmu5_platform_data = {
172 .name = "TMU5",
173 .channel_offset = 0x1c,
174 .timer_bit = 2,
175 .clk = "module_clk",
176};
177
178static struct resource tmu5_resources[] = {
179 [0] = {
180 .name = "TMU5",
181 .start = 0xffdc0020,
182 .end = 0xffdc002b,
183 .flags = IORESOURCE_MEM,
184 },
185 [1] = {
186 .start = 98,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device tmu5_device = {
192 .name = "sh_tmu",
193 .id = 5,
194 .dev = {
195 .platform_data = &tmu5_platform_data,
196 },
197 .resource = tmu5_resources,
198 .num_resources = ARRAY_SIZE(tmu5_resources),
199};
200
18static struct plat_sci_port sci_platform_data[] = { 201static struct plat_sci_port sci_platform_data[] = {
19 { 202 {
20 .mapbase = 0xffea0000, 203 .mapbase = 0xffea0000,
@@ -60,6 +243,12 @@ static struct platform_device sci_device = {
60}; 243};
61 244
62static struct platform_device *sh7785_devices[] __initdata = { 245static struct platform_device *sh7785_devices[] __initdata = {
246 &tmu0_device,
247 &tmu1_device,
248 &tmu2_device,
249 &tmu3_device,
250 &tmu4_device,
251 &tmu5_device,
63 &sci_device, 252 &sci_device,
64}; 253};
65 254
@@ -70,6 +259,21 @@ static int __init sh7785_devices_setup(void)
70} 259}
71__initcall(sh7785_devices_setup); 260__initcall(sh7785_devices_setup);
72 261
262static struct platform_device *sh7785_early_devices[] __initdata = {
263 &tmu0_device,
264 &tmu1_device,
265 &tmu2_device,
266 &tmu3_device,
267 &tmu4_device,
268 &tmu5_device,
269};
270
271void __init plat_early_device_setup(void)
272{
273 early_platform_add_devices(sh7785_early_devices,
274 ARRAY_SIZE(sh7785_early_devices));
275}
276
73enum { 277enum {
74 UNUSED = 0, 278 UNUSED = 0,
75 279
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 90e8cfff55fd..2c464bf5a899 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com>
6 * 7 *
7 * Based on SH7785 Setup 8 * Based on SH7785 Setup
8 * 9 *
@@ -19,6 +20,7 @@
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/mm.h> 21#include <linux/mm.h>
21#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h>
22#include <asm/mmzone.h> 24#include <asm/mmzone.h>
23 25
24static struct plat_sci_port sci_platform_data[] = { 26static struct plat_sci_port sci_platform_data[] = {
@@ -69,6 +71,368 @@ static struct platform_device sci_device = {
69 }, 71 },
70}; 72};
71 73
74static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0",
76 .channel_offset = 0x04,
77 .timer_bit = 0,
78 .clk = "module_clk",
79 .clockevent_rating = 200,
80};
81
82static struct resource tmu0_resources[] = {
83 [0] = {
84 .name = "TMU0",
85 .start = 0xffd80008,
86 .end = 0xffd80013,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = 16,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device tmu0_device = {
96 .name = "sh_tmu",
97 .id = 0,
98 .dev = {
99 .platform_data = &tmu0_platform_data,
100 },
101 .resource = tmu0_resources,
102 .num_resources = ARRAY_SIZE(tmu0_resources),
103};
104
105static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1",
107 .channel_offset = 0x10,
108 .timer_bit = 1,
109 .clk = "module_clk",
110 .clocksource_rating = 200,
111};
112
113static struct resource tmu1_resources[] = {
114 [0] = {
115 .name = "TMU1",
116 .start = 0xffd80014,
117 .end = 0xffd8001f,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = 17,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device tmu1_device = {
127 .name = "sh_tmu",
128 .id = 1,
129 .dev = {
130 .platform_data = &tmu1_platform_data,
131 },
132 .resource = tmu1_resources,
133 .num_resources = ARRAY_SIZE(tmu1_resources),
134};
135
136static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2",
138 .channel_offset = 0x1c,
139 .timer_bit = 2,
140 .clk = "module_clk",
141};
142
143static struct resource tmu2_resources[] = {
144 [0] = {
145 .name = "TMU2",
146 .start = 0xffd80020,
147 .end = 0xffd8002f,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = 18,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device tmu2_device = {
157 .name = "sh_tmu",
158 .id = 2,
159 .dev = {
160 .platform_data = &tmu2_platform_data,
161 },
162 .resource = tmu2_resources,
163 .num_resources = ARRAY_SIZE(tmu2_resources),
164};
165
166static struct sh_timer_config tmu3_platform_data = {
167 .name = "TMU3",
168 .channel_offset = 0x04,
169 .timer_bit = 0,
170 .clk = "module_clk",
171};
172
173static struct resource tmu3_resources[] = {
174 [0] = {
175 .name = "TMU3",
176 .start = 0xffda0008,
177 .end = 0xffda0013,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = 20,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186static struct platform_device tmu3_device = {
187 .name = "sh_tmu",
188 .id = 3,
189 .dev = {
190 .platform_data = &tmu3_platform_data,
191 },
192 .resource = tmu3_resources,
193 .num_resources = ARRAY_SIZE(tmu3_resources),
194};
195
196static struct sh_timer_config tmu4_platform_data = {
197 .name = "TMU4",
198 .channel_offset = 0x10,
199 .timer_bit = 1,
200 .clk = "module_clk",
201};
202
203static struct resource tmu4_resources[] = {
204 [0] = {
205 .name = "TMU4",
206 .start = 0xffda0014,
207 .end = 0xffda001f,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = 21,
212 .flags = IORESOURCE_IRQ,
213 },
214};
215
216static struct platform_device tmu4_device = {
217 .name = "sh_tmu",
218 .id = 4,
219 .dev = {
220 .platform_data = &tmu4_platform_data,
221 },
222 .resource = tmu4_resources,
223 .num_resources = ARRAY_SIZE(tmu4_resources),
224};
225
226static struct sh_timer_config tmu5_platform_data = {
227 .name = "TMU5",
228 .channel_offset = 0x1c,
229 .timer_bit = 2,
230 .clk = "module_clk",
231};
232
233static struct resource tmu5_resources[] = {
234 [0] = {
235 .name = "TMU5",
236 .start = 0xffda0020,
237 .end = 0xffda002b,
238 .flags = IORESOURCE_MEM,
239 },
240 [1] = {
241 .start = 22,
242 .flags = IORESOURCE_IRQ,
243 },
244};
245
246static struct platform_device tmu5_device = {
247 .name = "sh_tmu",
248 .id = 5,
249 .dev = {
250 .platform_data = &tmu5_platform_data,
251 },
252 .resource = tmu5_resources,
253 .num_resources = ARRAY_SIZE(tmu5_resources),
254};
255
256static struct sh_timer_config tmu6_platform_data = {
257 .name = "TMU6",
258 .channel_offset = 0x04,
259 .timer_bit = 0,
260 .clk = "module_clk",
261};
262
263static struct resource tmu6_resources[] = {
264 [0] = {
265 .name = "TMU6",
266 .start = 0xffdc0008,
267 .end = 0xffdc0013,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = 45,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device tmu6_device = {
277 .name = "sh_tmu",
278 .id = 6,
279 .dev = {
280 .platform_data = &tmu6_platform_data,
281 },
282 .resource = tmu6_resources,
283 .num_resources = ARRAY_SIZE(tmu6_resources),
284};
285
286static struct sh_timer_config tmu7_platform_data = {
287 .name = "TMU7",
288 .channel_offset = 0x10,
289 .timer_bit = 1,
290 .clk = "module_clk",
291};
292
293static struct resource tmu7_resources[] = {
294 [0] = {
295 .name = "TMU7",
296 .start = 0xffdc0014,
297 .end = 0xffdc001f,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = 45,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu7_device = {
307 .name = "sh_tmu",
308 .id = 7,
309 .dev = {
310 .platform_data = &tmu7_platform_data,
311 },
312 .resource = tmu7_resources,
313 .num_resources = ARRAY_SIZE(tmu7_resources),
314};
315
316static struct sh_timer_config tmu8_platform_data = {
317 .name = "TMU8",
318 .channel_offset = 0x1c,
319 .timer_bit = 2,
320 .clk = "module_clk",
321};
322
323static struct resource tmu8_resources[] = {
324 [0] = {
325 .name = "TMU8",
326 .start = 0xffdc0020,
327 .end = 0xffdc002b,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = 45,
332 .flags = IORESOURCE_IRQ,
333 },
334};
335
336static struct platform_device tmu8_device = {
337 .name = "sh_tmu",
338 .id = 8,
339 .dev = {
340 .platform_data = &tmu8_platform_data,
341 },
342 .resource = tmu8_resources,
343 .num_resources = ARRAY_SIZE(tmu8_resources),
344};
345
346static struct sh_timer_config tmu9_platform_data = {
347 .name = "TMU9",
348 .channel_offset = 0x04,
349 .timer_bit = 0,
350 .clk = "module_clk",
351};
352
353static struct resource tmu9_resources[] = {
354 [0] = {
355 .name = "TMU9",
356 .start = 0xffde0008,
357 .end = 0xffde0013,
358 .flags = IORESOURCE_MEM,
359 },
360 [1] = {
361 .start = 46,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366static struct platform_device tmu9_device = {
367 .name = "sh_tmu",
368 .id = 9,
369 .dev = {
370 .platform_data = &tmu9_platform_data,
371 },
372 .resource = tmu9_resources,
373 .num_resources = ARRAY_SIZE(tmu9_resources),
374};
375
376static struct sh_timer_config tmu10_platform_data = {
377 .name = "TMU10",
378 .channel_offset = 0x10,
379 .timer_bit = 1,
380 .clk = "module_clk",
381};
382
383static struct resource tmu10_resources[] = {
384 [0] = {
385 .name = "TMU10",
386 .start = 0xffde0014,
387 .end = 0xffde001f,
388 .flags = IORESOURCE_MEM,
389 },
390 [1] = {
391 .start = 46,
392 .flags = IORESOURCE_IRQ,
393 },
394};
395
396static struct platform_device tmu10_device = {
397 .name = "sh_tmu",
398 .id = 10,
399 .dev = {
400 .platform_data = &tmu10_platform_data,
401 },
402 .resource = tmu10_resources,
403 .num_resources = ARRAY_SIZE(tmu10_resources),
404};
405
406static struct sh_timer_config tmu11_platform_data = {
407 .name = "TMU11",
408 .channel_offset = 0x1c,
409 .timer_bit = 2,
410 .clk = "module_clk",
411};
412
413static struct resource tmu11_resources[] = {
414 [0] = {
415 .name = "TMU11",
416 .start = 0xffde0020,
417 .end = 0xffde002b,
418 .flags = IORESOURCE_MEM,
419 },
420 [1] = {
421 .start = 46,
422 .flags = IORESOURCE_IRQ,
423 },
424};
425
426static struct platform_device tmu11_device = {
427 .name = "sh_tmu",
428 .id = 11,
429 .dev = {
430 .platform_data = &tmu11_platform_data,
431 },
432 .resource = tmu11_resources,
433 .num_resources = ARRAY_SIZE(tmu11_resources),
434};
435
72static struct resource usb_ohci_resources[] = { 436static struct resource usb_ohci_resources[] = {
73 [0] = { 437 [0] = {
74 .start = 0xffe70400, 438 .start = 0xffe70400,
@@ -94,6 +458,21 @@ static struct platform_device usb_ohci_device = {
94 .resource = usb_ohci_resources, 458 .resource = usb_ohci_resources,
95}; 459};
96 460
461static struct platform_device *sh7786_early_devices[] __initdata = {
462 &tmu0_device,
463 &tmu1_device,
464 &tmu2_device,
465 &tmu3_device,
466 &tmu4_device,
467 &tmu5_device,
468 &tmu6_device,
469 &tmu7_device,
470 &tmu8_device,
471 &tmu9_device,
472 &tmu10_device,
473 &tmu11_device,
474};
475
97static struct platform_device *sh7786_devices[] __initdata = { 476static struct platform_device *sh7786_devices[] __initdata = {
98 &sci_device, 477 &sci_device,
99 &usb_ohci_device, 478 &usb_ohci_device,
@@ -156,12 +535,26 @@ static void __init sh7786_usb_setup(void)
156 535
157static int __init sh7786_devices_setup(void) 536static int __init sh7786_devices_setup(void)
158{ 537{
538 int ret;
539
159 sh7786_usb_setup(); 540 sh7786_usb_setup();
541
542 ret = platform_add_devices(sh7786_early_devices,
543 ARRAY_SIZE(sh7786_early_devices));
544 if (unlikely(ret != 0))
545 return ret;
546
160 return platform_add_devices(sh7786_devices, 547 return platform_add_devices(sh7786_devices,
161 ARRAY_SIZE(sh7786_devices)); 548 ARRAY_SIZE(sh7786_devices));
162} 549}
163device_initcall(sh7786_devices_setup); 550device_initcall(sh7786_devices_setup);
164 551
552void __init plat_early_device_setup(void)
553{
554 early_platform_add_devices(sh7786_early_devices,
555 ARRAY_SIZE(sh7786_early_devices));
556}
557
165enum { 558enum {
166 UNUSED = 0, 559 UNUSED = 0,
167 560
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index bd35f32534b9..9d5185b42f13 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 Setup 2 * SH-X3 Prototype Setup
3 * 3 *
4 * Copyright (C) 2007 Paul Mundt 4 * Copyright (C) 2007 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -12,6 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h>
15#include <asm/mmzone.h> 16#include <asm/mmzone.h>
16 17
17static struct plat_sci_port sci_platform_data[] = { 18static struct plat_sci_port sci_platform_data[] = {
@@ -48,17 +49,221 @@ static struct platform_device sci_device = {
48 }, 49 },
49}; 50};
50 51
52static struct sh_timer_config tmu0_platform_data = {
53 .name = "TMU0",
54 .channel_offset = 0x04,
55 .timer_bit = 0,
56 .clk = "module_clk",
57 .clockevent_rating = 200,
58};
59
60static struct resource tmu0_resources[] = {
61 [0] = {
62 .name = "TMU0",
63 .start = 0xffc10008,
64 .end = 0xffc10013,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = {
68 .start = 16,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73static struct platform_device tmu0_device = {
74 .name = "sh_tmu",
75 .id = 0,
76 .dev = {
77 .platform_data = &tmu0_platform_data,
78 },
79 .resource = tmu0_resources,
80 .num_resources = ARRAY_SIZE(tmu0_resources),
81};
82
83static struct sh_timer_config tmu1_platform_data = {
84 .name = "TMU1",
85 .channel_offset = 0x10,
86 .timer_bit = 1,
87 .clk = "module_clk",
88 .clocksource_rating = 200,
89};
90
91static struct resource tmu1_resources[] = {
92 [0] = {
93 .name = "TMU1",
94 .start = 0xffc10014,
95 .end = 0xffc1001f,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = 17,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct platform_device tmu1_device = {
105 .name = "sh_tmu",
106 .id = 1,
107 .dev = {
108 .platform_data = &tmu1_platform_data,
109 },
110 .resource = tmu1_resources,
111 .num_resources = ARRAY_SIZE(tmu1_resources),
112};
113
114static struct sh_timer_config tmu2_platform_data = {
115 .name = "TMU2",
116 .channel_offset = 0x1c,
117 .timer_bit = 2,
118 .clk = "module_clk",
119};
120
121static struct resource tmu2_resources[] = {
122 [0] = {
123 .name = "TMU2",
124 .start = 0xffc10020,
125 .end = 0xffc1002f,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = 18,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct platform_device tmu2_device = {
135 .name = "sh_tmu",
136 .id = 2,
137 .dev = {
138 .platform_data = &tmu2_platform_data,
139 },
140 .resource = tmu2_resources,
141 .num_resources = ARRAY_SIZE(tmu2_resources),
142};
143
144static struct sh_timer_config tmu3_platform_data = {
145 .name = "TMU3",
146 .channel_offset = 0x04,
147 .timer_bit = 0,
148 .clk = "module_clk",
149};
150
151static struct resource tmu3_resources[] = {
152 [0] = {
153 .name = "TMU3",
154 .start = 0xffc20008,
155 .end = 0xffc20013,
156 .flags = IORESOURCE_MEM,
157 },
158 [1] = {
159 .start = 19,
160 .flags = IORESOURCE_IRQ,
161 },
162};
163
164static struct platform_device tmu3_device = {
165 .name = "sh_tmu",
166 .id = 3,
167 .dev = {
168 .platform_data = &tmu3_platform_data,
169 },
170 .resource = tmu3_resources,
171 .num_resources = ARRAY_SIZE(tmu3_resources),
172};
173
174static struct sh_timer_config tmu4_platform_data = {
175 .name = "TMU4",
176 .channel_offset = 0x10,
177 .timer_bit = 1,
178 .clk = "module_clk",
179};
180
181static struct resource tmu4_resources[] = {
182 [0] = {
183 .name = "TMU4",
184 .start = 0xffc20014,
185 .end = 0xffc2001f,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = 20,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device tmu4_device = {
195 .name = "sh_tmu",
196 .id = 4,
197 .dev = {
198 .platform_data = &tmu4_platform_data,
199 },
200 .resource = tmu4_resources,
201 .num_resources = ARRAY_SIZE(tmu4_resources),
202};
203
204static struct sh_timer_config tmu5_platform_data = {
205 .name = "TMU5",
206 .channel_offset = 0x1c,
207 .timer_bit = 2,
208 .clk = "module_clk",
209};
210
211static struct resource tmu5_resources[] = {
212 [0] = {
213 .name = "TMU5",
214 .start = 0xffc20020,
215 .end = 0xffc2002b,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = 21,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device tmu5_device = {
225 .name = "sh_tmu",
226 .id = 5,
227 .dev = {
228 .platform_data = &tmu5_platform_data,
229 },
230 .resource = tmu5_resources,
231 .num_resources = ARRAY_SIZE(tmu5_resources),
232};
233
234static struct platform_device *shx3_early_devices[] __initdata = {
235 &tmu0_device,
236 &tmu1_device,
237 &tmu2_device,
238 &tmu3_device,
239 &tmu4_device,
240 &tmu5_device,
241};
242
51static struct platform_device *shx3_devices[] __initdata = { 243static struct platform_device *shx3_devices[] __initdata = {
52 &sci_device, 244 &sci_device,
53}; 245};
54 246
55static int __init shx3_devices_setup(void) 247static int __init shx3_devices_setup(void)
56{ 248{
249 int ret;
250
251 ret = platform_add_devices(shx3_early_devices,
252 ARRAY_SIZE(shx3_early_devices));
253 if (unlikely(ret != 0))
254 return ret;
255
57 return platform_add_devices(shx3_devices, 256 return platform_add_devices(shx3_devices,
58 ARRAY_SIZE(shx3_devices)); 257 ARRAY_SIZE(shx3_devices));
59} 258}
60__initcall(shx3_devices_setup); 259__initcall(shx3_devices_setup);
61 260
261void __init plat_early_device_setup(void)
262{
263 early_platform_add_devices(shx3_early_devices,
264 ARRAY_SIZE(shx3_early_devices));
265}
266
62enum { 267enum {
63 UNUSED = 0, 268 UNUSED = 0,
64 269
diff --git a/arch/sh/kernel/cpu/sh5/Makefile b/arch/sh/kernel/cpu/sh5/Makefile
index ce4602ea23a8..a184a31e686e 100644
--- a/arch/sh/kernel/cpu/sh5/Makefile
+++ b/arch/sh/kernel/cpu/sh5/Makefile
@@ -6,6 +6,9 @@ obj-y := entry.o probe.o switchto.o
6obj-$(CONFIG_SH_FPU) += fpu.o 6obj-$(CONFIG_SH_FPU) += fpu.o
7obj-$(CONFIG_KALLSYMS) += unwind.o 7obj-$(CONFIG_KALLSYMS) += unwind.o
8 8
9# CPU subtype setup
10obj-$(CONFIG_CPU_SH5) += setup-sh5.o
11
9# Primary on-chip clocks (common) 12# Primary on-chip clocks (common)
10clock-$(CONFIG_CPU_SH5) := clock-sh5.o 13clock-$(CONFIG_CPU_SH5) := clock-sh5.o
11 14
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 52c49248833a..5486324880e1 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -71,7 +71,7 @@ static struct clk_ops *sh5_clk_ops[] = {
71 71
72void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 72void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
73{ 73{
74 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); 74 cprc_base = (unsigned long)ioremap_nocache(CPRC_BASE, 1024);
75 BUG_ON(!cprc_base); 75 BUG_ON(!cprc_base);
76 76
77 if (idx < ARRAY_SIZE(sh5_clk_ops)) 77 if (idx < ARRAY_SIZE(sh5_clk_ops))
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index 7e49cb812f8b..b0aacf675258 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -812,27 +812,6 @@ no_underflow:
812 ! exceptions 812 ! exceptions
813 add SP, ZERO, r14 813 add SP, ZERO, r14
814 814
815#ifdef CONFIG_POOR_MANS_STRACE
816 /* We've pushed all the registers now, so only r2-r4 hold anything
817 * useful. Move them into callee save registers */
818 or r2, ZERO, r28
819 or r3, ZERO, r29
820 or r4, ZERO, r30
821
822 /* Preserve r2 as the event code */
823 movi evt_debug, r3
824 ori r3, 1, r3
825 ptabs r3, tr0
826
827 or SP, ZERO, r6
828 getcon TRA, r5
829 blink tr0, LINK
830
831 or r28, ZERO, r2
832 or r29, ZERO, r3
833 or r30, ZERO, r4
834#endif
835
836 /* For syscall and debug race condition, get TRA now */ 815 /* For syscall and debug race condition, get TRA now */
837 getcon TRA, r5 816 getcon TRA, r5
838 817
@@ -887,11 +866,6 @@ no_underflow:
887 */ 866 */
888 .global ret_from_irq 867 .global ret_from_irq
889ret_from_irq: 868ret_from_irq:
890#ifdef CONFIG_POOR_MANS_STRACE
891 pta evt_debug_ret_from_irq, tr0
892 ori SP, 0, r2
893 blink tr0, LINK
894#endif
895 ld.q SP, FRAME_S(FSSR), r6 869 ld.q SP, FRAME_S(FSSR), r6
896 shlri r6, 30, r6 870 shlri r6, 30, r6
897 andi r6, 1, r6 871 andi r6, 1, r6
@@ -905,12 +879,6 @@ ret_from_irq:
905ret_from_exception: 879ret_from_exception:
906 preempt_stop() 880 preempt_stop()
907 881
908#ifdef CONFIG_POOR_MANS_STRACE
909 pta evt_debug_ret_from_exc, tr0
910 ori SP, 0, r2
911 blink tr0, LINK
912#endif
913
914 ld.q SP, FRAME_S(FSSR), r6 882 ld.q SP, FRAME_S(FSSR), r6
915 shlri r6, 30, r6 883 shlri r6, 30, r6
916 andi r6, 1, r6 884 andi r6, 1, r6
@@ -1236,18 +1204,6 @@ syscall_bad:
1236 .global syscall_ret 1204 .global syscall_ret
1237syscall_ret: 1205syscall_ret:
1238 st.q SP, FRAME_R(9), r2 /* Expecting SP back to BASIC frame */ 1206 st.q SP, FRAME_R(9), r2 /* Expecting SP back to BASIC frame */
1239
1240#ifdef CONFIG_POOR_MANS_STRACE
1241 /* nothing useful in registers at this point */
1242
1243 movi evt_debug2, r5
1244 ori r5, 1, r5
1245 ptabs r5, tr0
1246 ld.q SP, FRAME_R(9), r2
1247 or SP, ZERO, r3
1248 blink tr0, LINK
1249#endif
1250
1251 ld.q SP, FRAME_S(FSPC), r2 1207 ld.q SP, FRAME_S(FSPC), r2
1252 addi r2, 4, r2 /* Move PC, being pre-execution event */ 1208 addi r2, 4, r2 /* Move PC, being pre-execution event */
1253 st.q SP, FRAME_S(FSPC), r2 1209 st.q SP, FRAME_S(FSPC), r2
@@ -1268,25 +1224,12 @@ ret_from_fork:
1268 ptabs r5, tr0 1224 ptabs r5, tr0
1269 blink tr0, LINK 1225 blink tr0, LINK
1270 1226
1271#ifdef CONFIG_POOR_MANS_STRACE
1272 /* nothing useful in registers at this point */
1273
1274 movi evt_debug2, r5
1275 ori r5, 1, r5
1276 ptabs r5, tr0
1277 ld.q SP, FRAME_R(9), r2
1278 or SP, ZERO, r3
1279 blink tr0, LINK
1280#endif
1281
1282 ld.q SP, FRAME_S(FSPC), r2 1227 ld.q SP, FRAME_S(FSPC), r2
1283 addi r2, 4, r2 /* Move PC, being pre-execution event */ 1228 addi r2, 4, r2 /* Move PC, being pre-execution event */
1284 st.q SP, FRAME_S(FSPC), r2 1229 st.q SP, FRAME_S(FSPC), r2
1285 pta ret_from_syscall, tr0 1230 pta ret_from_syscall, tr0
1286 blink tr0, ZERO 1231 blink tr0, ZERO
1287 1232
1288
1289
1290syscall_allowed: 1233syscall_allowed:
1291 /* Use LINK to deflect the exit point, default is syscall_ret */ 1234 /* Use LINK to deflect the exit point, default is syscall_ret */
1292 pta syscall_ret, tr0 1235 pta syscall_ret, tr0
@@ -1410,8 +1353,8 @@ peek_real_address_q:
1410 r2(out) : result quadword 1353 r2(out) : result quadword
1411 1354
1412 This is provided as a cheapskate way of manipulating device 1355 This is provided as a cheapskate way of manipulating device
1413 registers for debugging (to avoid the need to onchip_remap the debug 1356 registers for debugging (to avoid the need to ioremap the debug
1414 module, and to avoid the need to onchip_remap the watchpoint 1357 module, and to avoid the need to ioremap the watchpoint
1415 controller in a way that identity maps sufficient bits to avoid the 1358 controller in a way that identity maps sufficient bits to avoid the
1416 SH5-101 cut2 silicon defect). 1359 SH5-101 cut2 silicon defect).
1417 1360
@@ -1459,8 +1402,8 @@ poke_real_address_q:
1459 r3 : quadword value to write. 1402 r3 : quadword value to write.
1460 1403
1461 This is provided as a cheapskate way of manipulating device 1404 This is provided as a cheapskate way of manipulating device
1462 registers for debugging (to avoid the need to onchip_remap the debug 1405 registers for debugging (to avoid the need to ioremap the debug
1463 module, and to avoid the need to onchip_remap the watchpoint 1406 module, and to avoid the need to ioremap the watchpoint
1464 controller in a way that identity maps sufficient bits to avoid the 1407 controller in a way that identity maps sufficient bits to avoid the
1465 SH5-101 cut2 silicon defect). 1408 SH5-101 cut2 silicon defect).
1466 1409
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
new file mode 100644
index 000000000000..678d69bdebba
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -0,0 +1,195 @@
1/*
2 * SH5-101/SH5-103 CPU Setup
3 *
4 * Copyright (C) 2009 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/io.h>
15#include <linux/mm.h>
16#include <linux/sh_timer.h>
17#include <asm/addrspace.h>
18
19static struct plat_sci_port sci_platform_data[] = {
20 {
21 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
22 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
23 .type = PORT_SCIF,
24 .irqs = { 39, 40, 42, 0 },
25 }, {
26 .flags = 0,
27 }
28};
29
30static struct platform_device sci_device = {
31 .name = "sh-sci",
32 .id = -1,
33 .dev = {
34 .platform_data = sci_platform_data,
35 },
36};
37
38static struct resource rtc_resources[] = {
39 [0] = {
40 .start = PHYS_PERIPHERAL_BLOCK + 0x01040000,
41 .end = PHYS_PERIPHERAL_BLOCK + 0x01040000 + 0x58 - 1,
42 .flags = IORESOURCE_IO,
43 },
44 [1] = {
45 /* Period IRQ */
46 .start = IRQ_PRI,
47 .flags = IORESOURCE_IRQ,
48 },
49 [2] = {
50 /* Carry IRQ */
51 .start = IRQ_CUI,
52 .flags = IORESOURCE_IRQ,
53 },
54 [3] = {
55 /* Alarm IRQ */
56 .start = IRQ_ATI,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device rtc_device = {
62 .name = "sh-rtc",
63 .id = -1,
64 .num_resources = ARRAY_SIZE(rtc_resources),
65 .resource = rtc_resources,
66};
67
68#define TMU_BLOCK_OFF 0x01020000
69#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
70#define TMU0_BASE (TMU_BASE + 0x8 + (0xc * 0x0))
71#define TMU1_BASE (TMU_BASE + 0x8 + (0xc * 0x1))
72#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
73
74static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0",
76 .channel_offset = 0x04,
77 .timer_bit = 0,
78 .clk = "module_clk",
79 .clockevent_rating = 200,
80};
81
82static struct resource tmu0_resources[] = {
83 [0] = {
84 .name = "TMU0",
85 .start = TMU0_BASE,
86 .end = TMU0_BASE + 0xc - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = IRQ_TUNI0,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device tmu0_device = {
96 .name = "sh_tmu",
97 .id = 0,
98 .dev = {
99 .platform_data = &tmu0_platform_data,
100 },
101 .resource = tmu0_resources,
102 .num_resources = ARRAY_SIZE(tmu0_resources),
103};
104
105static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1",
107 .channel_offset = 0x10,
108 .timer_bit = 1,
109 .clk = "module_clk",
110 .clocksource_rating = 200,
111};
112
113static struct resource tmu1_resources[] = {
114 [0] = {
115 .name = "TMU1",
116 .start = TMU1_BASE,
117 .end = TMU1_BASE + 0xc - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_TUNI1,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device tmu1_device = {
127 .name = "sh_tmu",
128 .id = 1,
129 .dev = {
130 .platform_data = &tmu1_platform_data,
131 },
132 .resource = tmu1_resources,
133 .num_resources = ARRAY_SIZE(tmu1_resources),
134};
135
136static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2",
138 .channel_offset = 0x1c,
139 .timer_bit = 2,
140 .clk = "module_clk",
141};
142
143static struct resource tmu2_resources[] = {
144 [0] = {
145 .name = "TMU2",
146 .start = TMU2_BASE,
147 .end = TMU2_BASE + 0xc - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = IRQ_TUNI2,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device tmu2_device = {
157 .name = "sh_tmu",
158 .id = 2,
159 .dev = {
160 .platform_data = &tmu2_platform_data,
161 },
162 .resource = tmu2_resources,
163 .num_resources = ARRAY_SIZE(tmu2_resources),
164};
165
166static struct platform_device *sh5_early_devices[] __initdata = {
167 &tmu0_device,
168 &tmu1_device,
169 &tmu2_device,
170};
171
172static struct platform_device *sh5_devices[] __initdata = {
173 &sci_device,
174 &rtc_device,
175};
176
177static int __init sh5_devices_setup(void)
178{
179 int ret;
180
181 ret = platform_add_devices(sh5_early_devices,
182 ARRAY_SIZE(sh5_early_devices));
183 if (unlikely(ret != 0))
184 return ret;
185
186 return platform_add_devices(sh5_devices,
187 ARRAY_SIZE(sh5_devices));
188}
189__initcall(sh5_devices_setup);
190
191void __init plat_early_device_setup(void)
192{
193 early_platform_add_devices(sh5_early_devices,
194 ARRAY_SIZE(sh5_early_devices));
195}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-24 05:15:15 -0400