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-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c38
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c91
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c304
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c234
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c120
8 files changed, 706 insertions, 95 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index e6a1fb5f8484..24539873943a 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -10,6 +10,9 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
11obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 11obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
12 12
13# SMP setup
14smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o
15
13# Primary on-chip clocks (common) 16# Primary on-chip clocks (common)
14clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 17clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
15clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 18clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
@@ -18,4 +21,5 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
18clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 21clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
19clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 22clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
20 23
21obj-y += $(clock-y) 24obj-y += $(clock-y)
25obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 91d61cf91ba1..c0a3f079dfdc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -41,3 +41,7 @@ static int __init sh7343_devices_setup(void)
41 ARRAY_SIZE(sh7343_devices)); 41 ARRAY_SIZE(sh7343_devices));
42} 42}
43__initcall(sh7343_devices_setup); 43__initcall(sh7343_devices_setup);
44
45void __init plat_irq_setup(void)
46{
47}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 25b913e07e2c..55f66104431d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -84,7 +84,7 @@ enum {
84 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 84 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
85}; 85};
86 86
87static struct intc_vect vectors[] = { 87static struct intc_vect vectors[] __initdata = {
88 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 88 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
89 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 89 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
90 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 90 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
@@ -117,7 +117,7 @@ static struct intc_vect vectors[] = {
117 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 117 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
118}; 118};
119 119
120static struct intc_group groups[] = { 120static struct intc_group groups[] __initdata = {
121 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 121 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
122 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 122 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
123 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 123 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
@@ -130,7 +130,7 @@ static struct intc_group groups[] = {
130 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 130 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
131}; 131};
132 132
133static struct intc_prio priorities[] = { 133static struct intc_prio priorities[] __initdata = {
134 INTC_PRIO(SCIF0, 3), 134 INTC_PRIO(SCIF0, 3),
135 INTC_PRIO(SCIF1, 3), 135 INTC_PRIO(SCIF1, 3),
136 INTC_PRIO(SCIF2, 3), 136 INTC_PRIO(SCIF2, 3),
@@ -138,7 +138,7 @@ static struct intc_prio priorities[] = {
138 INTC_PRIO(TMU1, 2), 138 INTC_PRIO(TMU1, 2),
139}; 139};
140 140
141static struct intc_mask_reg mask_registers[] = { 141static struct intc_mask_reg mask_registers[] __initdata = {
142 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 142 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
143 { } }, 143 { } },
144 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 144 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
@@ -168,24 +168,24 @@ static struct intc_mask_reg mask_registers[] = {
168 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 168 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
169}; 169};
170 170
171static struct intc_prio_reg prio_registers[] = { 171static struct intc_prio_reg prio_registers[] __initdata = {
172 { 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 172 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
173 { 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 173 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
174 { 0xa4080008, 16, 4, /* IPRC */ { } }, 174 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
175 { 0xa408000c, 16, 4, /* IPRD */ { } }, 175 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
176 { 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 176 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
177 { 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 177 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
178 { 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 178 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
179 { 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 179 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
180 { 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 180 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
181 { 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 181 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
182 { 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 182 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
183 { 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 183 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
184 { 0xa4140010, 32, 4, /* INTPRI00 */ 184 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
185 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 185 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
186}; 186};
187 187
188static struct intc_sense_reg sense_registers[] = { 188static struct intc_sense_reg sense_registers[] __initdata = {
189 { 0xa414001c, 16, 2, /* ICR1 */ 189 { 0xa414001c, 16, 2, /* ICR1 */
190 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 190 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
191}; 191};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 6a04cc5f5aca..32f4f59a837b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -51,3 +51,7 @@ static int __init sh7770_devices_setup(void)
51 ARRAY_SIZE(sh7770_devices)); 51 ARRAY_SIZE(sh7770_devices));
52} 52}
53__initcall(sh7770_devices_setup); 53__initcall(sh7770_devices_setup);
54
55void __init plat_irq_setup(void)
56{
57}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index a4127ec15203..e8fd33ff0605 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -10,6 +10,7 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h>
13#include <asm/sci.h> 14#include <asm/sci.h>
14 15
15static struct resource rtc_resources[] = { 16static struct resource rtc_resources[] = {
@@ -114,7 +115,7 @@ enum {
114 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO, 115 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
115}; 116};
116 117
117static struct intc_vect vectors[] = { 118static struct intc_vect vectors[] __initdata = {
118 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 119 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
119 INTC_VECT(RTC_CUI, 0x4c0), 120 INTC_VECT(RTC_CUI, 0x4c0),
120 INTC_VECT(WDT, 0x560), 121 INTC_VECT(WDT, 0x560),
@@ -150,7 +151,7 @@ static struct intc_vect vectors[] = {
150 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 151 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
151}; 152};
152 153
153static struct intc_group groups[] = { 154static struct intc_group groups[] __initdata = {
154 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 155 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
155 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 156 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
156 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, 157 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
@@ -167,12 +168,12 @@ static struct intc_group groups[] = {
167 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3), 168 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
168}; 169};
169 170
170static struct intc_prio priorities[] = { 171static struct intc_prio priorities[] __initdata = {
171 INTC_PRIO(SCIF0, 3), 172 INTC_PRIO(SCIF0, 3),
172 INTC_PRIO(SCIF1, 3), 173 INTC_PRIO(SCIF1, 3),
173}; 174};
174 175
175static struct intc_mask_reg mask_registers[] = { 176static struct intc_mask_reg mask_registers[] __initdata = {
176 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 177 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
177 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, 178 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
178 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, 179 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
@@ -180,16 +181,18 @@ static struct intc_mask_reg mask_registers[] = {
180 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, 181 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
181}; 182};
182 183
183static struct intc_prio_reg prio_registers[] = { 184static struct intc_prio_reg prio_registers[] __initdata = {
184 { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } }, 185 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
185 { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, 186 TMU2, TMU2_TICPI } },
186 { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, 187 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
187 { 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, 188 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
188 { 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } }, 189 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
189 { 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, 190 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
190 PCIINTD, PCIC5 } }, 191 PCISERR, PCIINTA, } },
191 { 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, 192 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
192 { 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, 193 PCIINTD, PCIC5 } },
194 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
195 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
193}; 196};
194 197
195static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities, 198static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
@@ -197,24 +200,24 @@ static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
197 200
198/* Support for external interrupt pins in IRQ mode */ 201/* Support for external interrupt pins in IRQ mode */
199 202
200static struct intc_vect irq_vectors[] = { 203static struct intc_vect irq_vectors[] __initdata = {
201 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), 204 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
202 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), 205 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
203 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), 206 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
204 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), 207 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
205}; 208};
206 209
207static struct intc_mask_reg irq_mask_registers[] = { 210static struct intc_mask_reg irq_mask_registers[] __initdata = {
208 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ 211 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
209 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 212 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
210}; 213};
211 214
212static struct intc_prio_reg irq_prio_registers[] = { 215static struct intc_prio_reg irq_prio_registers[] __initdata = {
213 { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 216 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
214 IRQ4, IRQ5, IRQ6, IRQ7 } }, 217 IRQ4, IRQ5, IRQ6, IRQ7 } },
215}; 218};
216 219
217static struct intc_sense_reg irq_sense_registers[] = { 220static struct intc_sense_reg irq_sense_registers[] __initdata = {
218 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 221 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
219 IRQ4, IRQ5, IRQ6, IRQ7 } }, 222 IRQ4, IRQ5, IRQ6, IRQ7 } },
220}; 223};
@@ -225,7 +228,7 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
225 228
226/* External interrupt pins in IRL mode */ 229/* External interrupt pins in IRL mode */
227 230
228static struct intc_vect irl_vectors[] = { 231static struct intc_vect irl_vectors[] __initdata = {
229 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 232 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
230 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 233 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
231 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 234 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
@@ -236,16 +239,16 @@ static struct intc_vect irl_vectors[] = {
236 INTC_VECT(IRL_HHHL, 0x3c0), 239 INTC_VECT(IRL_HHHL, 0x3c0),
237}; 240};
238 241
239static struct intc_mask_reg irl3210_mask_registers[] = { 242static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
240 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ 243 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
241 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 244 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
242 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 245 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
243 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, 246 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
244 IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, 247 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
245}; 248};
246 249
247static struct intc_mask_reg irl7654_mask_registers[] = { 250static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
248 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ 251 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
249 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 252 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 253 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
251 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, 254 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
@@ -259,8 +262,28 @@ static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
259static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, 262static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
260 NULL, NULL, irl3210_mask_registers, NULL, NULL); 263 NULL, NULL, irl3210_mask_registers, NULL, NULL);
261 264
265#define INTC_ICR0 0xffd00000
266#define INTC_INTMSK0 0xffd00044
267#define INTC_INTMSK1 0xffd00048
268#define INTC_INTMSK2 0xffd40080
269#define INTC_INTMSKCLR1 0xffd00068
270#define INTC_INTMSKCLR2 0xffd40084
271
262void __init plat_irq_setup(void) 272void __init plat_irq_setup(void)
263{ 273{
274 /* disable IRQ7-0 */
275 ctrl_outl(0xff000000, INTC_INTMSK0);
276
277 /* disable IRL3-0 + IRL7-4 */
278 ctrl_outl(0xc0000000, INTC_INTMSK1);
279 ctrl_outl(0xfffefffe, INTC_INTMSK2);
280
281 /* select IRL mode for IRL3-0 + IRL7-4 */
282 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
283
284 /* disable holding function, ie enable "SH-4 Mode" */
285 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
286
264 register_intc_controller(&intc_desc); 287 register_intc_controller(&intc_desc);
265} 288}
266 289
@@ -268,12 +291,28 @@ void __init plat_irq_setup_pins(int mode)
268{ 291{
269 switch (mode) { 292 switch (mode) {
270 case IRQ_MODE_IRQ: 293 case IRQ_MODE_IRQ:
294 /* select IRQ mode for IRL3-0 + IRL7-4 */
295 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
271 register_intc_controller(&intc_irq_desc); 296 register_intc_controller(&intc_irq_desc);
272 break; 297 break;
273 case IRQ_MODE_IRL7654: 298 case IRQ_MODE_IRL7654:
274 register_intc_controller(&intc_irl7654_desc); 299 /* enable IRL7-4 but don't provide any masking */
300 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
301 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
275 break; 302 break;
276 case IRQ_MODE_IRL3210: 303 case IRQ_MODE_IRL3210:
304 /* enable IRL0-3 but don't provide any masking */
305 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
306 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
307 break;
308 case IRQ_MODE_IRL7654_MASK:
309 /* enable IRL7-4 and mask using cpu intc controller */
310 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
311 register_intc_controller(&intc_irl7654_desc);
312 break;
313 case IRQ_MODE_IRL3210_MASK:
314 /* enable IRL0-3 and mask using cpu intc controller */
315 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
277 register_intc_controller(&intc_irl3210_desc); 316 register_intc_controller(&intc_irl3210_desc);
278 break; 317 break;
279 default: 318 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index cf047562e43f..39b215d6cee5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -10,6 +10,9 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h>
14#include <linux/mm.h>
15#include <asm/mmzone.h>
13#include <asm/sci.h> 16#include <asm/sci.h>
14 17
15static struct plat_sci_port sci_platform_data[] = { 18static struct plat_sci_port sci_platform_data[] = {
@@ -72,46 +75,281 @@ static int __init sh7785_devices_setup(void)
72} 75}
73__initcall(sh7785_devices_setup); 76__initcall(sh7785_devices_setup);
74 77
75static struct intc2_data intc2_irq_table[] = { 78enum {
76 { 28, 0, 24, 0, 0, 2 }, /* TMU0 */ 79 UNUSED = 0,
77 80
78 { 40, 8, 24, 0, 2, 3 }, /* SCIF0 ERI */ 81 /* interrupt sources */
79 { 41, 8, 24, 0, 2, 3 }, /* SCIF0 RXI */ 82
80 { 42, 8, 24, 0, 2, 3 }, /* SCIF0 BRI */ 83 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
81 { 43, 8, 24, 0, 2, 3 }, /* SCIF0 TXI */ 84 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
82 85 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
83 { 44, 8, 16, 0, 3, 3 }, /* SCIF1 ERI */ 86 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
84 { 45, 8, 16, 0, 3, 3 }, /* SCIF1 RXI */ 87
85 { 46, 8, 16, 0, 3, 3 }, /* SCIF1 BRI */ 88 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
86 { 47, 8, 16, 0, 3, 3 }, /* SCIF1 TXI */ 89 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
87 90 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
88 { 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */ 91 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
89 { 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */ 92
90 { 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */ 93 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
91 { 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */ 94 WDT,
92 { 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */ 95 TMU0, TMU1, TMU2, TMU2_TICPI,
93 96 HUDI,
94 { 60, 8, 8, 0, 4, 3 }, /* SCIF2 ERI, RXI, BRI, TXI */ 97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
95 { 60, 8, 0, 0, 5, 3 }, /* SCIF3 ERI, RXI, BRI, TXI */ 98 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
96 { 60, 12, 24, 0, 6, 3 }, /* SCIF4 ERI, RXI, BRI, TXI */ 99 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
97 { 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */ 100 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
101 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
102 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
103 HSPI,
104 SCIF2, SCIF3, SCIF4, SCIF5,
105 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
106 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
107 SIOF,
108 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
109 DU,
110 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
111 TMU3, TMU4, TMU5,
112 SSI0, SSI1,
113 HAC0, HAC1,
114 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
115 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
116
117 /* interrupt groups */
118
119 TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
120 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
98}; 121};
99 122
100static struct intc2_desc intc2_irq_desc __read_mostly = { 123static struct intc_vect vectors[] __initdata = {
101 .prio_base = 0xffd40000, 124 INTC_VECT(WDT, 0x560),
102 .msk_base = 0xffd40038, 125 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
103 .mskclr_base = 0xffd4003c, 126 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
127 INTC_VECT(HUDI, 0x600),
128 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
129 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
130 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
131 INTC_VECT(DMAC0_DMAE, 0x6e0),
132 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
133 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
134 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
135 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
136 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
137 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
138 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
139 INTC_VECT(DMAC1_DMAE, 0x940),
140 INTC_VECT(HSPI, 0x960),
141 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
142 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
143 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
144 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
145 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
146 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
147 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
148 INTC_VECT(SIOF, 0xc00),
149 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
150 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
151 INTC_VECT(DU, 0xd80),
152 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
153 INTC_VECT(GDTA_GAERI, 0xde0),
154 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
155 INTC_VECT(TMU5, 0xe40),
156 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
157 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
158 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
159 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
160 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
161 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
162};
104 163
105 .intc2_data = intc2_irq_table, 164static struct intc_group groups[] __initdata = {
106 .nr_irqs = ARRAY_SIZE(intc2_irq_table), 165 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
166 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
167 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
168 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
169 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
170 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
171 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
172 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
173 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
174 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
175 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
176 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
177 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
178 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
179};
107 180
108 .chip = { 181static struct intc_prio priorities[] __initdata = {
109 .name = "INTC2-sh7785", 182 INTC_PRIO(SCIF0, 3),
110 }, 183 INTC_PRIO(SCIF1, 3),
184 INTC_PRIO(SCIF2, 3),
185 INTC_PRIO(SCIF3, 3),
186 INTC_PRIO(SCIF4, 3),
187 INTC_PRIO(SCIF5, 3),
188};
189
190static struct intc_mask_reg mask_registers[] __initdata = {
191 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
192 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
193
194 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
195 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
196 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
197 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
198 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
199 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
200 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
201 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
202 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
203
204 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
205 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
206 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
207 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
208 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
209};
210
211static struct intc_prio_reg prio_registers[] __initdata = {
212 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
213 IRQ4, IRQ5, IRQ6, IRQ7 } },
214 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
215 TMU2, TMU2_TICPI } },
216 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
217 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
218 SCIF2, SCIF3 } },
219 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
220 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
221 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
222 PCISERR, PCIINTA } },
223 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
224 PCIINTD, PCIC5 } },
225 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
226 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
227 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
111}; 228};
112 229
230static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
231 mask_registers, prio_registers, NULL);
232
233/* Support for external interrupt pins in IRQ mode */
234
235static struct intc_vect vectors_irq0123[] __initdata = {
236 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
237 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
238};
239
240static struct intc_vect vectors_irq4567[] __initdata = {
241 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
242 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
243};
244
245static struct intc_sense_reg sense_registers[] __initdata = {
246 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
247 IRQ4, IRQ5, IRQ6, IRQ7 } },
248};
249
250static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
251 NULL, NULL, mask_registers, prio_registers,
252 sense_registers);
253
254static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
255 NULL, NULL, mask_registers, prio_registers,
256 sense_registers);
257
258/* External interrupt pins in IRL mode */
259
260static struct intc_vect vectors_irl0123[] __initdata = {
261 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
262 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
263 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
264 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
265 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
266 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
267 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
268 INTC_VECT(IRL0_HHHL, 0x3c0),
269};
270
271static struct intc_vect vectors_irl4567[] __initdata = {
272 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
273 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
274 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
275 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
276 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
277 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
278 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
279 INTC_VECT(IRL4_HHHL, 0xcc0),
280};
281
282static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
283 NULL, NULL, mask_registers, NULL, NULL);
284
285static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
286 NULL, NULL, mask_registers, NULL, NULL);
287
288#define INTC_ICR0 0xffd00000
289#define INTC_INTMSK0 0xffd00044
290#define INTC_INTMSK1 0xffd00048
291#define INTC_INTMSK2 0xffd40080
292#define INTC_INTMSKCLR1 0xffd00068
293#define INTC_INTMSKCLR2 0xffd40084
294
113void __init plat_irq_setup(void) 295void __init plat_irq_setup(void)
114{ 296{
115 register_intc2_controller(&intc2_irq_desc); 297 /* disable IRQ3-0 + IRQ7-4 */
298 ctrl_outl(0xff000000, INTC_INTMSK0);
299
300 /* disable IRL3-0 + IRL7-4 */
301 ctrl_outl(0xc0000000, INTC_INTMSK1);
302 ctrl_outl(0xfffefffe, INTC_INTMSK2);
303
304 /* select IRL mode for IRL3-0 + IRL7-4 */
305 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
306
307 /* disable holding function, ie enable "SH-4 Mode" */
308 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
309
310 register_intc_controller(&intc_desc);
311}
312
313void __init plat_irq_setup_pins(int mode)
314{
315 switch (mode) {
316 case IRQ_MODE_IRQ7654:
317 /* select IRQ mode for IRL7-4 */
318 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
319 register_intc_controller(&intc_desc_irq4567);
320 break;
321 case IRQ_MODE_IRQ3210:
322 /* select IRQ mode for IRL3-0 */
323 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
324 register_intc_controller(&intc_desc_irq0123);
325 break;
326 case IRQ_MODE_IRL7654:
327 /* enable IRL7-4 but don't provide any masking */
328 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
329 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
330 break;
331 case IRQ_MODE_IRL3210:
332 /* enable IRL0-3 but don't provide any masking */
333 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
334 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
335 break;
336 case IRQ_MODE_IRL7654_MASK:
337 /* enable IRL7-4 and mask using cpu intc controller */
338 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
339 register_intc_controller(&intc_desc_irl4567);
340 break;
341 case IRQ_MODE_IRL3210_MASK:
342 /* enable IRL0-3 and mask using cpu intc controller */
343 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
344 register_intc_controller(&intc_desc_irl0123);
345 break;
346 default:
347 BUG();
348 }
116} 349}
117 350
351void __init plat_mem_setup(void)
352{
353 /* Register the URAM space as Node 1 */
354 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
355}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 704c064f70dc..c6cdd7e3b049 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <asm/mmzone.h>
14#include <asm/sci.h> 15#include <asm/sci.h>
15 16
16static struct plat_sci_port sci_platform_data[] = { 17static struct plat_sci_port sci_platform_data[] = {
@@ -58,28 +59,229 @@ static int __init shx3_devices_setup(void)
58} 59}
59__initcall(shx3_devices_setup); 60__initcall(shx3_devices_setup);
60 61
61static struct intc2_data intc2_irq_table[] = { 62enum {
62 { 16, 0, 0, 0, 1, 2 }, /* TMU0 */ 63 UNUSED = 0,
63 { 40, 4, 0, 0x20, 0, 3 }, /* SCIF0 ERI */ 64
64 { 41, 4, 0, 0x20, 1, 3 }, /* SCIF0 RXI */ 65 /* interrupt sources */
65 { 42, 4, 0, 0x20, 2, 3 }, /* SCIF0 BRI */ 66 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
66 { 43, 4, 0, 0x20, 3, 3 }, /* SCIF0 TXI */ 67 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
68 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
69 IRL_HHLL, IRL_HHLH, IRL_HHHL,
70 IRQ0, IRQ1, IRQ2, IRQ3,
71 HUDII,
72 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
73 PCII0, PCII1, PCII2, PCII3, PCII4,
74 PCII5, PCII6, PCII7, PCII8, PCII9,
75 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
76 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
77 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
78 SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
79 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
80 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
81 DU,
82 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
83 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
84 IIC, VIN0, VIN1, VCORE0, ATAPI,
85 DTU0_TEND, DTU0_AE, DTU0_TMISS,
86 DTU1_TEND, DTU1_AE, DTU1_TMISS,
87 DTU2_TEND, DTU2_AE, DTU2_TMISS,
88 DTU3_TEND, DTU3_AE, DTU3_TMISS,
89 FE0, FE1,
90 GPIO0, GPIO1, GPIO2, GPIO3,
91 PAM, IRM,
92 INTICI0, INTICI1, INTICI2, INTICI3,
93 INTICI4, INTICI5, INTICI6, INTICI7,
94
95 /* interrupt groups */
96 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
97 DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
98};
99
100static struct intc_vect vectors[] __initdata = {
101 INTC_VECT(HUDII, 0x3e0),
102 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
103 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
104 INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
105 INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
106 INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
107 INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
108 INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
109 INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
110 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
111 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
112 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
113 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
114 INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
115 INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
116 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
117 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
118 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
119 INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
120 INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
121 INTC_VECT(DMAC0_DMAE, 0x9c0),
122 INTC_VECT(DU, 0x9e0),
123 INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
124 INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
125 INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
126 INTC_VECT(DMAC1_DMAE, 0xac0),
127 INTC_VECT(IIC, 0xae0),
128 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
129 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
130 INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
131 INTC_VECT(DTU0_TMISS, 0xc40),
132 INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
133 INTC_VECT(DTU1_TMISS, 0xca0),
134 INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
135 INTC_VECT(DTU2_TMISS, 0xd00),
136 INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
137 INTC_VECT(DTU3_TMISS, 0xd60),
138 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
139 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
140 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
141 INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
142 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
143 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
144 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
145 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
67}; 146};
68 147
69static struct intc2_desc intc2_irq_desc __read_mostly = { 148static struct intc_group groups[] __initdata = {
70 .prio_base = 0xfe410000, 149 INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
71 .msk_base = 0xfe410820, 150 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
72 .mskclr_base = 0xfe410850, 151 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
152 IRL_HHLL, IRL_HHLH, IRL_HHHL),
153 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
154 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
155 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
156 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
157 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
158 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
159 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
160 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
161 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
162 INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
163 INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
164 INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
165 INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
166};
73 167
74 .intc2_data = intc2_irq_table, 168static struct intc_prio priorities[] __initdata = {
75 .nr_irqs = ARRAY_SIZE(intc2_irq_table), 169 INTC_PRIO(SCIF0, 3),
170 INTC_PRIO(SCIF1, 3),
171 INTC_PRIO(SCIF2, 3),
172 INTC_PRIO(SCIF3, 3),
173};
76 174
77 .chip = { 175static struct intc_mask_reg mask_registers[] __initdata = {
78 .name = "INTC2-SHX3", 176 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
79 }, 177 { IRQ0, IRQ1, IRQ2, IRQ3 } },
178 { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
179 { IRL } },
180 { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
181 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
182 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
183 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
184 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
185 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
186 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
187 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
188 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
189 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
190 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
191 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
192 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
193 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
195 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
196 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
197 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
198};
199
200static struct intc_prio_reg prio_registers[] __initdata = {
201 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
202
203 { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
204 TMU3, TMU2, TMU1, TMU0 } },
205 { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
206 SCIF3, SCIF2,
207 SCIF1, SCIF0 } },
208 { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
209 PCII56789, PCII4,
210 PCII3, PCII2,
211 PCII1, PCII0 } },
212 { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
213 VIN1, VIN0, IIC, DU} },
214 { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
215 GPIO2, GPIO1, GPIO0, IRM } },
216 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
217 { INTICI7, INTICI6, INTICI5, INTICI4,
218 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
219};
220
221static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
222 mask_registers, prio_registers, NULL);
223
224/* Support for external interrupt pins in IRQ mode */
225static struct intc_vect vectors_irq[] __initdata = {
226 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
227 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
228};
229
230static struct intc_sense_reg sense_registers[] __initdata = {
231 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
80}; 232};
81 233
234static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
235 priorities, mask_registers, prio_registers,
236 sense_registers);
237
238/* External interrupt pins in IRL mode */
239static struct intc_vect vectors_irl[] __initdata = {
240 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
241 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
242 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
243 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
244 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
245 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
246 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
247 INTC_VECT(IRL_HHHL, 0x3c0),
248};
249
250static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
251 priorities, mask_registers, prio_registers, NULL);
252
253void __init plat_irq_setup_pins(int mode)
254{
255 switch (mode) {
256 case IRQ_MODE_IRQ:
257 register_intc_controller(&intc_desc_irq);
258 break;
259 case IRQ_MODE_IRL3210:
260 register_intc_controller(&intc_desc_irl);
261 break;
262 default:
263 BUG();
264 }
265}
266
82void __init plat_irq_setup(void) 267void __init plat_irq_setup(void)
83{ 268{
84 register_intc2_controller(&intc2_irq_desc); 269 register_intc_controller(&intc_desc);
270}
271
272void __init plat_mem_setup(void)
273{
274 unsigned int nid = 1;
275
276 /* Register CPU#0 URAM space as Node 1 */
277 setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */
278
279#if 0
280 /* XXX: Not yet.. */
281 setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */
282 setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */
283 setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */
284#endif
285
286 setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */
85} 287}
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
new file mode 100644
index 000000000000..e5e06845fa43
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -0,0 +1,120 @@
1/*
2 * SH-X3 SMP
3 *
4 * Copyright (C) 2007 Paul Mundt
5 * Copyright (C) 2007 Magnus Damm
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/init.h>
12#include <linux/cpumask.h>
13#include <linux/smp.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16
17void __init plat_smp_setup(void)
18{
19 unsigned int cpu = 0;
20 int i, num;
21
22 cpus_clear(cpu_possible_map);
23 cpu_set(cpu, cpu_possible_map);
24
25 __cpu_number_map[0] = 0;
26 __cpu_logical_map[0] = 0;
27
28 /*
29 * Do this stupidly for now.. we don't have an easy way to probe
30 * for the total number of cores.
31 */
32 for (i = 1, num = 0; i < NR_CPUS; i++) {
33 cpu_set(i, cpu_possible_map);
34 __cpu_number_map[i] = ++num;
35 __cpu_logical_map[num] = i;
36 }
37
38 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
39}
40
41void __init plat_prepare_cpus(unsigned int max_cpus)
42{
43}
44
45#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
46#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
47
48#define STBCR_MSTP 0x00000001
49#define STBCR_RESET 0x00000002
50#define STBCR_LTSLP 0x80000000
51
52#define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP)
53
54void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
55{
56 ctrl_outl(entry_point, RESET_REG(cpu));
57
58 if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
59 ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
60
61 while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
62 ;
63
64 /* Start up secondary processor by sending a reset */
65 ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
66}
67
68int plat_smp_processor_id(void)
69{
70 return ctrl_inl(0xff000048); /* CPIDR */
71}
72
73void plat_send_ipi(unsigned int cpu, unsigned int message)
74{
75 unsigned long addr = 0xfe410070 + (cpu * 4);
76
77 BUG_ON(cpu >= 4);
78 BUG_ON(message >= SMP_MSG_NR);
79
80 ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
81}
82
83struct ipi_data {
84 void (*handler)(void *);
85 void *arg;
86 unsigned int message;
87};
88
89static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
90{
91 struct ipi_data *id = arg;
92 unsigned int cpu = hard_smp_processor_id();
93 unsigned int offs = 4 * cpu;
94 unsigned int x;
95
96 x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
97 x &= (1 << (id->message << 2));
98 ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
99
100 id->handler(id->arg);
101
102 return IRQ_HANDLED;
103}
104
105static struct ipi_data ipi_handlers[SMP_MSG_NR];
106
107int plat_register_ipi_handler(unsigned int message,
108 void (*handler)(void *), void *arg)
109{
110 struct ipi_data *id = &ipi_handlers[message];
111
112 BUG_ON(SMP_MSG_NR >= 8);
113 BUG_ON(message >= SMP_MSG_NR);
114
115 id->handler = handler;
116 id->arg = arg;
117 id->message = message;
118
119 return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id);
120}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 04:41:39 -0500