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-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c199
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c225
-rw-r--r--arch/sh/kernel/cpu/sh4a/intc-shx3.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/perf_event.c20
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c1582
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-shx3.c587
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c66
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c222
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c126
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c42
12 files changed, 2148 insertions, 962 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index b144e8af89dc..cc122b1d3035 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -8,13 +8,13 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
18 18
19# SMP setup 19# SMP setup
20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o 20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
@@ -40,6 +40,7 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o 40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
43pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o
43 44
44obj-y += $(clock-y) 45obj-y += $(clock-y)
45obj-$(CONFIG_SMP) += $(smp-y) 46obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 0a752bd324ac..ce39a2ae8c6c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7757 support for the clock framework 4 * SH7757 support for the clock framework
5 * 5 *
6 * Copyright (C) 2009 Renesas Solutions Corp. 6 * Copyright (C) 2009-2010 Renesas Solutions Corp.
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -16,124 +16,147 @@
16#include <asm/clock.h> 16#include <asm/clock.h>
17#include <asm/freq.h> 17#include <asm/freq.h>
18 18
19static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 19/*
20 16, 1, 1, 32, 1, 1, 1, 1 }; 20 * Default rate for the root input clock, reset this with clk_set_rate()
21static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 21 * from the platform code.
22 16, 1, 1, 32, 1, 1, 1, 1 }; 22 */
23static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 23static struct clk extal_clk = {
24 16, 1, 1, 32, 1, 1, 1, 1 }; 24 .rate = 48000000,
25static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, 25};
26 16, 1, 1, 32, 1, 1, 1, 1 };
27 26
28static void master_clk_init(struct clk *clk) 27static unsigned long pll_recalc(struct clk *clk)
29{ 28{
30 clk->rate = CONFIG_SH_PCLK_FREQ * 16; 29 int multiplier;
31}
32 30
33static struct clk_ops sh7757_master_clk_ops = { 31 multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
34 .init = master_clk_init,
35};
36 32
37static void module_clk_recalc(struct clk *clk) 33 return clk->parent->rate * multiplier;
38{
39 int idx = __raw_readl(FRQCR) & 0x0000000f;
40 clk->rate = clk->parent->rate / p1fc_divisors[idx];
41} 34}
42 35
43static struct clk_ops sh7757_module_clk_ops = { 36static struct clk_ops pll_clk_ops = {
44 .recalc = module_clk_recalc, 37 .recalc = pll_recalc,
45}; 38};
46 39
47static void bus_clk_recalc(struct clk *clk) 40static struct clk pll_clk = {
48{ 41 .ops = &pll_clk_ops,
49 int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f; 42 .parent = &extal_clk,
50 clk->rate = clk->parent->rate / bfc_divisors[idx]; 43 .flags = CLK_ENABLE_ON_INIT,
51} 44};
52 45
53static struct clk_ops sh7757_bus_clk_ops = { 46static struct clk *clks[] = {
54 .recalc = bus_clk_recalc, 47 &extal_clk,
48 &pll_clk,
55}; 49};
56 50
57static void cpu_clk_recalc(struct clk *clk) 51static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
58{ 52 1, 1, 1, 16, 1, 24, 1, 1 };
59 int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
60 clk->rate = clk->parent->rate / ifc_divisors[idx];
61}
62 53
63static struct clk_ops sh7757_cpu_clk_ops = { 54static struct clk_div_mult_table div4_div_mult_table = {
64 .recalc = cpu_clk_recalc, 55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
65}; 57};
66 58
67static struct clk_ops *sh7757_clk_ops[] = { 59static struct clk_div4_table div4_table = {
68 &sh7757_master_clk_ops, 60 .div_mult_table = &div4_div_mult_table,
69 &sh7757_module_clk_ops,
70 &sh7757_bus_clk_ops,
71 &sh7757_cpu_clk_ops,
72}; 61};
73 62
74void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 63enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
75{
76 if (idx < ARRAY_SIZE(sh7757_clk_ops))
77 *ops = sh7757_clk_ops[idx];
78}
79 64
80static void shyway_clk_recalc(struct clk *clk) 65#define DIV4(_bit, _mask, _flags) \
81{ 66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
82 int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
83 clk->rate = clk->parent->rate / sfc_divisors[idx];
84}
85
86static struct clk_ops sh7757_shyway_clk_ops = {
87 .recalc = shyway_clk_recalc,
88};
89 67
90static struct clk sh7757_shyway_clk = { 68struct clk div4_clks[DIV4_NR] = {
91 .flags = CLK_ENABLE_ON_INIT, 69 /*
92 .ops = &sh7757_shyway_clk_ops, 70 * P clock is always enable, because some P clock modules is used
71 * by Host PC.
72 */
73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
93}; 76};
94 77
95/* 78#define MSTPCR0 0xffc80030
96 * Additional sh7757-specific on-chip clocks that aren't already part of the 79#define MSTPCR1 0xffc80034
97 * clock framework 80
98 */ 81enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
99static struct clk *sh7757_onchip_clocks[] = { 82 MSTP111, MSTP110, MSTP103, MSTP102,
100 &sh7757_shyway_clk, 83 MSTP_NR };
84
85static struct clk mstp_clks[MSTP_NR] = {
86 /* MSTPCR0 */
87 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
88 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
89
90 /* MSTPCR1 */
91 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
92 [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
93 [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
94 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
95 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
96 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
97 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
101}; 98};
102 99
103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
104 101
105static struct clk_lookup lookups[] = { 102static struct clk_lookup lookups[] = {
106 /* main clocks */ 103 /* main clocks */
107 CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk), 104 CLKDEV_CON_ID("extal", &extal_clk),
105 CLKDEV_CON_ID("pll_clk", &pll_clk),
106
107 /* DIV4 clocks */
108 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
109 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
110 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
111
112 /* MSTP32 clocks */
113 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
114 CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
115 {
116 /* TMU0 */
117 .dev_id = "sh_tmu.0",
118 .con_id = "tmu_fck",
119 .clk = &mstp_clks[MSTP113],
120 }, {
121 /* TMU1 */
122 .dev_id = "sh_tmu.1",
123 .con_id = "tmu_fck",
124 .clk = &mstp_clks[MSTP114],
125 },
126 {
127 /* SCIF4 (But, ID is 2) */
128 .dev_id = "sh-sci.2",
129 .con_id = "sci_fck",
130 .clk = &mstp_clks[MSTP112],
131 }, {
132 /* SCIF3 */
133 .dev_id = "sh-sci.1",
134 .con_id = "sci_fck",
135 .clk = &mstp_clks[MSTP111],
136 }, {
137 /* SCIF2 */
138 .dev_id = "sh-sci.0",
139 .con_id = "sci_fck",
140 .clk = &mstp_clks[MSTP110],
141 },
142 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
108}; 143};
109 144
110static int __init sh7757_clk_init(void) 145int __init arch_clk_init(void)
111{ 146{
112 struct clk *clk = clk_get(NULL, "master_clk"); 147 int i, ret = 0;
113 int i;
114
115 for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
116 struct clk *clkp = sh7757_onchip_clocks[i];
117 148
118 clkp->parent = clk; 149 for (i = 0; i < ARRAY_SIZE(clks); i++)
119 clk_register(clkp); 150 ret |= clk_register(clks[i]);
120 clk_enable(clkp); 151 for (i = 0; i < ARRAY_SIZE(lookups); i++)
121 } 152 clkdev_add(&lookups[i]);
122 153
123 /* 154 if (!ret)
124 * Now that we have the rest of the clocks registered, we need to 155 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
125 * force the parent clock to propagate so that these clocks will 156 &div4_table);
126 * automatically figure out their rate. We cheat by handing the 157 if (!ret)
127 * parent clock its current rate and forcing child propagation. 158 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
128 */
129 clk_set_rate(clk, clk_get_rate(clk));
130 159
131 clk_put(clk); 160 return ret;
132
133 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
134
135 return 0;
136} 161}
137 162
138arch_initcall(sh7757_clk_init);
139
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 236a6282d778..4f70df6b6169 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2006-2007 Renesas Technology Corp. 6 * Copyright (C) 2006-2007 Renesas Technology Corp.
7 * Copyright (C) 2006-2007 Renesas Solutions Corp. 7 * Copyright (C) 2006-2007 Renesas Solutions Corp.
8 * Copyright (C) 2006-2007 Paul Mundt 8 * Copyright (C) 2006-2010 Paul Mundt
9 * 9 *
10 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
@@ -18,120 +18,179 @@
18#include <asm/clock.h> 18#include <asm/clock.h>
19#include <asm/freq.h> 19#include <asm/freq.h>
20 20
21static int ifc_divisors[] = { 1, 2, 4 ,6 }; 21/*
22static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; 22 * Default rate for the root input clock, reset this with clk_set_rate()
23static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 }; 23 * from the platform code.
24static int cfc_divisors[] = { 1, 1, 4, 6 }; 24 */
25 25static struct clk extal_clk = {
26#define IFC_POS 28 26 .rate = 16666666,
27#define IFC_MSK 0x0003
28#define BFC_MSK 0x000f
29#define PFC_MSK 0x000f
30#define CFC_MSK 0x0003
31#define BFC_POS 16
32#define PFC_POS 0
33#define CFC_POS 20
34
35static void master_clk_init(struct clk *clk)
36{
37 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
38}
39
40static struct clk_ops shx3_master_clk_ops = {
41 .init = master_clk_init,
42}; 27};
43 28
44static unsigned long module_clk_recalc(struct clk *clk) 29static unsigned long pll_recalc(struct clk *clk)
45{ 30{
46 int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK); 31 /* PLL1 has a fixed x72 multiplier. */
47 return clk->parent->rate / pfc_divisors[idx]; 32 return clk->parent->rate * 72;
48} 33}
49 34
50static struct clk_ops shx3_module_clk_ops = { 35static struct clk_ops pll_clk_ops = {
51 .recalc = module_clk_recalc, 36 .recalc = pll_recalc,
52}; 37};
53 38
54static unsigned long bus_clk_recalc(struct clk *clk) 39static struct clk pll_clk = {
55{ 40 .ops = &pll_clk_ops,
56 int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK); 41 .parent = &extal_clk,
57 return clk->parent->rate / bfc_divisors[idx]; 42 .flags = CLK_ENABLE_ON_INIT,
58} 43};
59 44
60static struct clk_ops shx3_bus_clk_ops = { 45static struct clk *clks[] = {
61 .recalc = bus_clk_recalc, 46 &extal_clk,
47 &pll_clk,
62}; 48};
63 49
64static unsigned long cpu_clk_recalc(struct clk *clk) 50static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
65{ 51 24, 32, 36, 48 };
66 int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
67 return clk->parent->rate / ifc_divisors[idx];
68}
69 52
70static struct clk_ops shx3_cpu_clk_ops = { 53static struct clk_div_mult_table div4_div_mult_table = {
71 .recalc = cpu_clk_recalc, 54 .divisors = div2,
55 .nr_divisors = ARRAY_SIZE(div2),
72}; 56};
73 57
74static struct clk_ops *shx3_clk_ops[] = { 58static struct clk_div4_table div4_table = {
75 &shx3_master_clk_ops, 59 .div_mult_table = &div4_div_mult_table,
76 &shx3_module_clk_ops,
77 &shx3_bus_clk_ops,
78 &shx3_cpu_clk_ops,
79}; 60};
80 61
81void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 62enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
82{
83 if (idx < ARRAY_SIZE(shx3_clk_ops))
84 *ops = shx3_clk_ops[idx];
85}
86 63
87static unsigned long shyway_clk_recalc(struct clk *clk) 64#define DIV4(_bit, _mask, _flags) \
88{ 65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
89 int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
90 return clk->parent->rate / cfc_divisors[idx];
91}
92 66
93static struct clk_ops shx3_shyway_clk_ops = { 67struct clk div4_clks[DIV4_NR] = {
94 .recalc = shyway_clk_recalc, 68 [DIV4_P] = DIV4(0, 0x0f80, 0),
69 [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
95}; 74};
96 75
97static struct clk shx3_shyway_clk = { 76#define MSTPCR0 0xffc00030
98 .flags = CLK_ENABLE_ON_INIT, 77#define MSTPCR1 0xffc00034
99 .ops = &shx3_shyway_clk_ops, 78
100}; 79enum { MSTP027, MSTP026, MSTP025, MSTP024,
101 80 MSTP009, MSTP008, MSTP003, MSTP002,
102/* 81 MSTP001, MSTP000, MSTP119, MSTP105,
103 * Additional SHx3-specific on-chip clocks that aren't already part of the 82 MSTP104, MSTP_NR };
104 * clock framework 83
105 */ 84static struct clk mstp_clks[MSTP_NR] = {
106static struct clk *shx3_onchip_clocks[] = { 85 /* MSTPCR0 */
107 &shx3_shyway_clk, 86 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
87 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
88 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
89 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
90 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
91 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
92 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
93 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
94 [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
95 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
96
97 /* MSTPCR1 */
98 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
99 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
108}; 101};
109 102
110#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
111 104
112static struct clk_lookup lookups[] = { 105static struct clk_lookup lookups[] = {
113 /* main clocks */ 106 /* main clocks */
114 CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk), 107 CLKDEV_CON_ID("extal", &extal_clk),
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
109
110 /* DIV4 clocks */
111 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
112 CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
113 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
114 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
115 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
116 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
117
118 /* MSTP32 clocks */
119 {
120 /* SCIF3 */
121 .dev_id = "sh-sci.3",
122 .con_id = "sci_fck",
123 .clk = &mstp_clks[MSTP027],
124 }, {
125 /* SCIF2 */
126 .dev_id = "sh-sci.2",
127 .con_id = "sci_fck",
128 .clk = &mstp_clks[MSTP026],
129 }, {
130 /* SCIF1 */
131 .dev_id = "sh-sci.1",
132 .con_id = "sci_fck",
133 .clk = &mstp_clks[MSTP025],
134 }, {
135 /* SCIF0 */
136 .dev_id = "sh-sci.0",
137 .con_id = "sci_fck",
138 .clk = &mstp_clks[MSTP024],
139 },
140 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
141 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
142 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
143 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
144 {
145 /* TMU0 */
146 .dev_id = "sh_tmu.0",
147 .con_id = "tmu_fck",
148 .clk = &mstp_clks[MSTP008],
149 }, {
150 /* TMU1 */
151 .dev_id = "sh_tmu.1",
152 .con_id = "tmu_fck",
153 .clk = &mstp_clks[MSTP008],
154 }, {
155 /* TMU2 */
156 .dev_id = "sh_tmu.2",
157 .con_id = "tmu_fck",
158 .clk = &mstp_clks[MSTP008],
159 }, {
160 /* TMU3 */
161 .dev_id = "sh_tmu.3",
162 .con_id = "tmu_fck",
163 .clk = &mstp_clks[MSTP009],
164 }, {
165 /* TMU4 */
166 .dev_id = "sh_tmu.4",
167 .con_id = "tmu_fck",
168 .clk = &mstp_clks[MSTP009],
169 }, {
170 /* TMU5 */
171 .dev_id = "sh_tmu.5",
172 .con_id = "tmu_fck",
173 .clk = &mstp_clks[MSTP009],
174 },
175 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
176 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
177 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
115}; 178};
116 179
117int __init arch_clk_init(void) 180int __init arch_clk_init(void)
118{ 181{
119 struct clk *clk;
120 int i, ret = 0; 182 int i, ret = 0;
121 183
122 cpg_clk_init(); 184 for (i = 0; i < ARRAY_SIZE(clks); i++)
123 185 ret |= clk_register(clks[i]);
124 clk = clk_get(NULL, "master_clk"); 186 for (i = 0; i < ARRAY_SIZE(lookups); i++)
125 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { 187 clkdev_add(&lookups[i]);
126 struct clk *clkp = shx3_onchip_clocks[i];
127
128 clkp->parent = clk;
129 ret |= clk_register(clkp);
130 }
131
132 clk_put(clk);
133 188
134 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 189 if (!ret)
190 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
191 &div4_table);
192 if (!ret)
193 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
135 194
136 return ret; 195 return ret;
137} 196}
diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
new file mode 100644
index 000000000000..78c971486b4e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
@@ -0,0 +1,34 @@
1/*
2 * Shared support for SH-X3 interrupt controllers.
3 *
4 * Copyright (C) 2009 - 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/irq.h>
11#include <linux/io.h>
12#include <linux/init.h>
13
14#define INTACK 0xfe4100b8
15#define INTACKCLR 0xfe4100bc
16#define INTC_USERIMASK 0xfe411000
17
18#ifdef CONFIG_INTC_BALANCING
19unsigned int irq_lookup(unsigned int irq)
20{
21 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
22}
23
24void irq_finish(unsigned int irq)
25{
26 __raw_writel(irq2evt(irq), INTACKCLR);
27}
28#endif
29
30static int __init shx3_irq_setup(void)
31{
32 return register_intc_userimask(INTC_USERIMASK);
33}
34arch_initcall(shx3_irq_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index eddc21973fa1..b8b873d8d6b5 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Performance events support for SH-4A performance counters 2 * Performance events support for SH-4A performance counters
3 * 3 *
4 * Copyright (C) 2009 Paul Mundt 4 * Copyright (C) 2009, 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -22,7 +22,25 @@
22#define CCBR_CMDS (1 << 1) 22#define CCBR_CMDS (1 << 1)
23#define CCBR_PPCE (1 << 0) 23#define CCBR_PPCE (1 << 0)
24 24
25#ifdef CONFIG_CPU_SHX3
26/*
27 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
28 * and PMCTR locations remains tentatively constant. This change remains
29 * wholly undocumented, and was simply found through trial and error.
30 *
31 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
32 * it's unclear when this ceased to be the case. For now we always use
33 * the new location (if future parts keep up with this trend then
34 * scanning for them at runtime also remains a viable option.)
35 *
36 * The gap in the register space also suggests that there are other
37 * undocumented counters, so this will need to be revisited at a later
38 * point in time.
39 */
40#define PPC_PMCAT 0xfc100240
41#else
25#define PPC_PMCAT 0xfc100080 42#define PPC_PMCAT 0xfc100080
43#endif
26 44
27#define PMCAT_OVF3 (1 << 27) 45#define PMCAT_OVF3 (1 << 27)
28#define PMCAT_CNN3 (1 << 26) 46#define PMCAT_CNN3 (1 << 26)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index ed23b155c097..4c74bd04bba4 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -1,11 +1,11 @@
1/* 1/*
2 * SH7757 (A0 step) Pinmux 2 * SH7757 (B0 step) Pinmux
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009-2010 Renesas Solutions Corp.
5 * 5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 * 7 *
8 * Based on SH7757 Pinmux 8 * Based on SH7723 Pinmux
9 * Copyright (C) 2008 Magnus Damm 9 * Copyright (C) 2008 Magnus Damm
10 * 10 *
11 * This file is subject to the terms and conditions of the GNU General Public 11 * This file is subject to the terms and conditions of the GNU General Public
@@ -40,27 +40,27 @@ enum {
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, 40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, 41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA, 42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
43 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, 43 PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, 44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, 45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, 46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
47 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 47 PTL6_DATA, PTL5_DATA, PTL4_DATA,
48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, 48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
49 PTM6_DATA, PTM5_DATA, PTM4_DATA, 49 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, 50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
51 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 51 PTN6_DATA, PTN5_DATA, PTN4_DATA,
52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, 52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, 53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA, 54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
55 PTP6_DATA, PTP5_DATA, PTP4_DATA, 55 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA, 56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, 57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, 58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, 59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, 60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, 61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, 62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
63 PTT5_DATA, PTT4_DATA, 63 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, 64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, 65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, 66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
@@ -95,27 +95,27 @@ enum {
95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, 95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN, 96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN, 97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
98 PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN, 98 PTJ6_IN, PTJ5_IN, PTJ4_IN,
99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, 99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, 100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, 101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
102 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, 102 PTL6_IN, PTL5_IN, PTL4_IN,
103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, 103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
104 PTM6_IN, PTM5_IN, PTM4_IN, 104 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, 105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
106 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, 106 PTN6_IN, PTN5_IN, PTN4_IN,
107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, 107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN, 108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN, 109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
110 PTP6_IN, PTP5_IN, PTP4_IN, 110 PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN,
111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN, 111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
112 PTQ6_IN, PTQ5_IN, PTQ4_IN, 112 PTQ6_IN, PTQ5_IN, PTQ4_IN,
113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, 113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, 114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, 115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, 116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, 117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
118 PTT5_IN, PTT4_IN, 118 PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, 119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN, 120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, 121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
@@ -132,16 +132,43 @@ enum {
132 PINMUX_INPUT_END, 132 PINMUX_INPUT_END,
133 133
134 PINMUX_INPUT_PULLUP_BEGIN, 134 PINMUX_INPUT_PULLUP_BEGIN,
135 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
136 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
137 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
138 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
139 PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
140 PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
141 PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
142 PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
143 PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU,
144 PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
145 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
146 PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU,
147 PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU,
148 PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
149 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
150 PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
151 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
152 PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
153 PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
154 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
155 PTN4_IN_PU,
156 PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
157 PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU,
158 PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU,
159 PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
160 PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
135 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, 161 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
136 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, 162 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
137 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, 163 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
138 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, 164 PTV3_IN_PU, PTV2_IN_PU,
139 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, 165 PTW1_IN_PU, PTW0_IN_PU,
140 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
141 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, 166 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
142 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, 167 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
143 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, 168 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
144 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, 169 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
170 PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
171 PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
145 PINMUX_INPUT_PULLUP_END, 172 PINMUX_INPUT_PULLUP_END,
146 173
147 PINMUX_OUTPUT_BEGIN, 174 PINMUX_OUTPUT_BEGIN,
@@ -163,27 +190,27 @@ enum {
163 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, 190 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
164 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT, 191 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
165 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT, 192 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
166 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, 193 PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
167 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, 194 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
168 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, 195 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
169 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, 196 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
170 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, 197 PTL6_OUT, PTL5_OUT, PTL4_OUT,
171 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, 198 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
172 PTM6_OUT, PTM5_OUT, PTM4_OUT, 199 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
173 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, 200 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
174 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, 201 PTN6_OUT, PTN5_OUT, PTN4_OUT,
175 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, 202 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
176 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT, 203 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
177 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT, 204 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
178 PTP6_OUT, PTP5_OUT, PTP4_OUT, 205 PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT,
179 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT, 206 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
180 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, 207 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
181 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, 208 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
182 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, 209 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
183 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT, 210 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
184 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, 211 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
185 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, 212 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
186 PTT5_OUT, PTT4_OUT, 213 PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
187 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, 214 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
188 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT, 215 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
189 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, 216 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
@@ -218,27 +245,27 @@ enum {
218 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, 245 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
219 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN, 246 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
220 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN, 247 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
221 PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN, 248 PTJ6_FN, PTJ5_FN, PTJ4_FN,
222 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, 249 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
223 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, 250 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
224 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, 251 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
225 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, 252 PTL6_FN, PTL5_FN, PTL4_FN,
226 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, 253 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
227 PTM6_FN, PTM5_FN, PTM4_FN, 254 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
228 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, 255 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
229 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, 256 PTN6_FN, PTN5_FN, PTN4_FN,
230 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, 257 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
231 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN, 258 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
232 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN, 259 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
233 PTP6_FN, PTP5_FN, PTP4_FN, 260 PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN,
234 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN, 261 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
235 PTQ6_FN, PTQ5_FN, PTQ4_FN, 262 PTQ6_FN, PTQ5_FN, PTQ4_FN,
236 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, 263 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
237 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, 264 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
238 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, 265 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
239 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, 266 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
240 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, 267 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
241 PTT5_FN, PTT4_FN, 268 PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
242 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, 269 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
243 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN, 270 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
244 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, 271 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
@@ -253,181 +280,248 @@ enum {
253 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, 280 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
254 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, 281 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
255 282
256 PS0_15_FN1, PS0_15_FN3, 283 PS0_15_FN1, PS0_15_FN2,
257 PS0_14_FN1, PS0_14_FN3, 284 PS0_14_FN1, PS0_14_FN2,
258 PS0_13_FN1, PS0_13_FN3, 285 PS0_13_FN1, PS0_13_FN2,
259 PS0_12_FN1, PS0_12_FN3, 286 PS0_12_FN1, PS0_12_FN2,
287 PS0_11_FN1, PS0_11_FN2,
288 PS0_10_FN1, PS0_10_FN2,
289 PS0_9_FN1, PS0_9_FN2,
290 PS0_8_FN1, PS0_8_FN2,
260 PS0_7_FN1, PS0_7_FN2, 291 PS0_7_FN1, PS0_7_FN2,
261 PS0_6_FN1, PS0_6_FN2, 292 PS0_6_FN1, PS0_6_FN2,
262 PS0_5_FN1, PS0_5_FN2, 293 PS0_5_FN1, PS0_5_FN2,
263 PS0_4_FN1, PS0_4_FN2, 294 PS0_4_FN1, PS0_4_FN2,
264 PS0_3_FN1, PS0_3_FN2, 295 PS0_3_FN1, PS0_3_FN2,
265 PS0_2_FN1, PS0_2_FN2, 296 PS0_2_FN1, PS0_2_FN2,
266 PS0_1_FN1, PS0_1_FN2,
267 297
268 PS1_7_FN1, PS1_7_FN3, 298 PS1_10_FN1, PS1_10_FN2,
269 PS1_6_FN1, PS1_6_FN3, 299 PS1_9_FN1, PS1_9_FN2,
300 PS1_8_FN1, PS1_8_FN2,
301 PS1_2_FN1, PS1_2_FN2,
302
303 PS2_13_FN1, PS2_13_FN2,
304 PS2_12_FN1, PS2_12_FN2,
305 PS2_7_FN1, PS2_7_FN2,
306 PS2_6_FN1, PS2_6_FN2,
307 PS2_5_FN1, PS2_5_FN2,
308 PS2_4_FN1, PS2_4_FN2,
309 PS2_2_FN1, PS2_2_FN2,
310
311 PS3_15_FN1, PS3_15_FN2,
312 PS3_14_FN1, PS3_14_FN2,
313 PS3_13_FN1, PS3_13_FN2,
314 PS3_12_FN1, PS3_12_FN2,
315 PS3_11_FN1, PS3_11_FN2,
316 PS3_10_FN1, PS3_10_FN2,
317 PS3_9_FN1, PS3_9_FN2,
318 PS3_8_FN1, PS3_8_FN2,
319 PS3_7_FN1, PS3_7_FN2,
320 PS3_2_FN1, PS3_2_FN2,
321 PS3_1_FN1, PS3_1_FN2,
270 322
271 PS2_13_FN1, PS2_13_FN3,
272 PS2_12_FN1, PS2_12_FN3,
273 PS2_1_FN1, PS2_1_FN2,
274 PS2_0_FN1, PS2_0_FN2,
275
276 PS4_15_FN1, PS4_15_FN2,
277 PS4_14_FN1, PS4_14_FN2, 323 PS4_14_FN1, PS4_14_FN2,
278 PS4_13_FN1, PS4_13_FN2, 324 PS4_13_FN1, PS4_13_FN2,
279 PS4_12_FN1, PS4_12_FN2, 325 PS4_12_FN1, PS4_12_FN2,
280 PS4_11_FN1, PS4_11_FN2,
281 PS4_10_FN1, PS4_10_FN2, 326 PS4_10_FN1, PS4_10_FN2,
282 PS4_9_FN1, PS4_9_FN2, 327 PS4_9_FN1, PS4_9_FN2,
328 PS4_8_FN1, PS4_8_FN2,
329 PS4_4_FN1, PS4_4_FN2,
283 PS4_3_FN1, PS4_3_FN2, 330 PS4_3_FN1, PS4_3_FN2,
284 PS4_2_FN1, PS4_2_FN2, 331 PS4_2_FN1, PS4_2_FN2,
285 PS4_1_FN1, PS4_1_FN2, 332 PS4_1_FN1, PS4_1_FN2,
286 PS4_0_FN1, PS4_0_FN2, 333 PS4_0_FN1, PS4_0_FN2,
287 334
335 PS5_11_FN1, PS5_11_FN2,
336 PS5_10_FN1, PS5_10_FN2,
288 PS5_9_FN1, PS5_9_FN2, 337 PS5_9_FN1, PS5_9_FN2,
289 PS5_8_FN1, PS5_8_FN2, 338 PS5_8_FN1, PS5_8_FN2,
290 PS5_7_FN1, PS5_7_FN2, 339 PS5_7_FN1, PS5_7_FN2,
291 PS5_6_FN1, PS5_6_FN2, 340 PS5_6_FN1, PS5_6_FN2,
292 PS5_5_FN1, PS5_5_FN2, 341 PS5_5_FN1, PS5_5_FN2,
293 PS5_4_FN1, PS5_4_FN2, 342 PS5_4_FN1, PS5_4_FN2,
294 343 PS5_3_FN1, PS5_3_FN2,
295 /* AN15 to 8 : EVENT15 to 8 */ 344 PS5_2_FN1, PS5_2_FN2,
296 PS6_7_FN_AN, PS6_7_FN_EV, 345
297 PS6_6_FN_AN, PS6_6_FN_EV, 346 PS6_15_FN1, PS6_15_FN2,
298 PS6_5_FN_AN, PS6_5_FN_EV, 347 PS6_14_FN1, PS6_14_FN2,
299 PS6_4_FN_AN, PS6_4_FN_EV, 348 PS6_13_FN1, PS6_13_FN2,
300 PS6_3_FN_AN, PS6_3_FN_EV, 349 PS6_12_FN1, PS6_12_FN2,
301 PS6_2_FN_AN, PS6_2_FN_EV, 350 PS6_11_FN1, PS6_11_FN2,
302 PS6_1_FN_AN, PS6_1_FN_EV, 351 PS6_10_FN1, PS6_10_FN2,
303 PS6_0_FN_AN, PS6_0_FN_EV, 352 PS6_9_FN1, PS6_9_FN2,
304 353 PS6_8_FN1, PS6_8_FN2,
354 PS6_7_FN1, PS6_7_FN2,
355 PS6_6_FN1, PS6_6_FN2,
356 PS6_5_FN1, PS6_5_FN2,
357 PS6_4_FN1, PS6_4_FN2,
358 PS6_3_FN1, PS6_3_FN2,
359 PS6_2_FN1, PS6_2_FN2,
360 PS6_1_FN1, PS6_1_FN2,
361 PS6_0_FN1, PS6_0_FN2,
362
363 PS7_15_FN1, PS7_15_FN2,
364 PS7_14_FN1, PS7_14_FN2,
365 PS7_13_FN1, PS7_13_FN2,
366 PS7_12_FN1, PS7_12_FN2,
367 PS7_11_FN1, PS7_11_FN2,
368 PS7_10_FN1, PS7_10_FN2,
369 PS7_9_FN1, PS7_9_FN2,
370 PS7_8_FN1, PS7_8_FN2,
371 PS7_7_FN1, PS7_7_FN2,
372 PS7_6_FN1, PS7_6_FN2,
373 PS7_5_FN1, PS7_5_FN2,
374 PS7_4_FN1, PS7_4_FN2,
375
376 PS8_15_FN1, PS8_15_FN2,
377 PS8_14_FN1, PS8_14_FN2,
378 PS8_13_FN1, PS8_13_FN2,
379 PS8_12_FN1, PS8_12_FN2,
380 PS8_11_FN1, PS8_11_FN2,
381 PS8_10_FN1, PS8_10_FN2,
382 PS8_9_FN1, PS8_9_FN2,
383 PS8_8_FN1, PS8_8_FN2,
305 PINMUX_FUNCTION_END, 384 PINMUX_FUNCTION_END,
306 385
307 PINMUX_MARK_BEGIN, 386 PINMUX_MARK_BEGIN,
308 /* PTA (mobule: LBSC, CPG, LPC) */ 387 /* PTA (mobule: LBSC, RGMII) */
309 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK, 388 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK,
310 MD10_MARK, MD9_MARK, MD8_MARK,
311 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
312 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
313
314 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
315 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
316 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
317 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK, 389 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK,
318 SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
319 WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK,
320 LPC_SPIEN_MARK, BASEL_MARK,
321 390
322 /* PTC (mobule: SD) */ 391 /* PTB (mobule: INTC, ONFI, TMU) */
323 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, 392 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK,
324 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, 393 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK,
394 ON_NRE_MARK, ON_NWE_MARK, ON_NWP_MARK, ON_NCE0_MARK,
395 ON_R_B0_MARK, ON_ALE_MARK, ON_CLE_MARK, TCLK_MARK,
325 396
326 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ 397 /* PTC (mobule: IRQ, PWMU) */
327 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK, 398 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK,
328 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, 399 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
329 MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK, 400 PWMU0_MARK, PWMU1_MARK, PWMU2_MARK, PWMU3_MARK,
330 MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK, 401 PWMU4_MARK, PWMU5_MARK,
331 402
332 /* PTE (mobule: EtherC) */ 403 /* PTD (mobule: SPI0, DMAC) */
333 ET0_CRS_DV_MARK, ET0_TXD1_MARK, 404 SP0_MOSI_MARK, SP0_MISO_MARK, SP0_SCK_MARK, SP0_SCK_FB_MARK,
334 ET0_TXD0_MARK, ET0_TX_EN_MARK, 405 SP0_SS0_MARK, SP0_SS1_MARK, SP0_SS2_MARK, SP0_SS3_MARK,
335 ET0_REF_CLK_MARK, ET0_RXD1_MARK, 406 DREQ0_MARK, DACK0_MARK, TEND0_MARK,
336 ET0_RXD0_MARK, ET0_RX_ER_MARK, 407
337 408 /* PTE (mobule: RMII) */
338 /* PTF (mobule: EtherC) */ 409 RMII0_CRS_DV_MARK, RMII0_TXD1_MARK,
339 ET1_CRS_DV_MARK, ET1_TXD1_MARK, 410 RMII0_TXD0_MARK, RMII0_TXEN_MARK,
340 ET1_TXD0_MARK, ET1_TX_EN_MARK, 411 RMII0_REFCLK_MARK, RMII0_RXD1_MARK,
341 ET1_REF_CLK_MARK, ET1_RXD1_MARK, 412 RMII0_RXD0_MARK, RMII0_RX_ER_MARK,
342 ET1_RXD0_MARK, ET1_RX_ER_MARK, 413
343 414 /* PTF (mobule: RMII, SerMux) */
344 /* PTG (mobule: SYSTEM, PWMX, LPC) */ 415 RMII1_CRS_DV_MARK, RMII1_TXD1_MARK,
345 STATUS0_MARK, STATUS1_MARK, 416 RMII1_TXD0_MARK, RMII1_TXEN_MARK,
346 PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK, 417 RMII1_REFCLK_MARK, RMII1_RXD1_MARK,
347 SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK, 418 RMII1_RXD0_MARK, RMII1_RX_ER_MARK,
348 419 RAC_RI_MARK,
349 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ 420
350 TCLK_MARK, RXD4_MARK, TXD4_MARK, 421 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
422 BOOTFMS_MARK, BOOTWP_MARK, A25_MARK, A24_MARK,
423 SERIRQ_MARK, WDTOVF_MARK, LPCPD_MARK, LDRQ_MARK,
424 MMCCLK_MARK, MMCCMD_MARK,
425
426 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
351 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK, 427 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK,
352 SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK, 428 SP1_SS0_MARK, SP1_SS1_MARK, WP_MARK, FMS0_MARK,
429 TEND1_MARK, DREQ1_MARK, DACK1_MARK, ADTRG1_MARK,
430 ADTRG0_MARK,
353 431
354 /* PTI (mobule: INTC) */ 432 /* PTI (mobule: LBSC, SDHI) */
355 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, 433 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
356 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, 434 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
435 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK,
436 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK,
357 437
358 /* PTJ (mobule: SCIF234, SERMUX) */ 438 /* PTJ (mobule: SCIF234) */
359 RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK, 439 RTS3_MARK, CTS3_MARK, TXD3_MARK, RXD3_MARK,
360 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, 440 RTS4_MARK, RXD4_MARK, TXD4_MARK,
361 441
362 /* PTK (mobule: SERMUX) */ 442 /* PTK (mobule: SERMUX, LBSC, SCIF) */
363 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK, 443 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK,
364 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK, 444 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, CLKOUT_MARK,
445 SCK2_MARK, SCK4_MARK, SCK3_MARK,
365 446
366 /* PTL (mobule: SERMUX) */ 447 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
367 RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, 448 RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, RAC_DTR_MARK,
368 RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK, 449 RAC_DSR_MARK, RAC_DCD_MARK, RAC_TXD_MARK, RXD2_MARK,
450 CS5_MARK, CS6_MARK, AUDSYNC_MARK, AUDCK_MARK,
451 TXD2_MARK,
369 452
370 /* PTM (mobule: IIC, LPC) */ 453 /* PTM (mobule: LBSC, IIC) */
454 CS4_MARK, RD_MARK, WE0_MARK, CS0_MARK,
371 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK, 455 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK,
372 WP_MARK, FMS0_MARK, FMS1_MARK,
373 456
374 /* PTN (mobule: SCIF234, EVC) */ 457 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
375 SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK, 458 VBUS_EN_MARK, VBUS_OC_MARK, JMCTCK_MARK, JMCTMS_MARK,
376 CTS4_MARK, CTS3_MARK, CTS2_MARK, 459 JMCTDO_MARK, JMCTDI_MARK, JMCTRST_MARK,
377 EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK, 460 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, SGPIO1_DI_MARK,
378 EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK, 461 SGPIO1_DO_MARK, SUB_CLKIN_MARK,
379 462
380 /* PTO (mobule: SGPIO) */ 463 /* PTO (mobule: SGPIO, SerMux) */
381 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, 464 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, SGPIO0_DI_MARK,
382 SGPIO0_DI_MARK, SGPIO0_DO_MARK, 465 SGPIO0_DO_MARK, SGPIO2_CLK_MARK, SGPIO2_LOAD_MARK,
383 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, 466 SGPIO2_DI_MARK, SGPIO2_DO_MARK,
384 SGPIO1_DI_MARK, SGPIO1_DO_MARK, 467 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK,
385
386 /* PTP (mobule: JMC, SCIF234) */
387 JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK,
388 JMCRST_MARK, SCK4_MARK, SCK3_MARK,
389 468
390 /* PTQ (mobule: LPC) */ 469 /* PTQ (mobule: LPC) */
391 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK, 470 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK,
392 LFRAME_MARK, LRESET_MARK, LCLK_MARK, 471 LFRAME_MARK, LRESET_MARK, LCLK_MARK,
393 472
394 /* PTR (mobule: GRA, IIC) */ 473 /* PTR (mobule: GRA, IIC) */
395 DDC3_MARK, DDC2_MARK, 474 DDC3_MARK, DDC2_MARK, SDA2_MARK, SCL2_MARK,
396 SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK,
397 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK, 475 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK,
476 SDA8_MARK, SCL8_MARK,
398 477
399 /* PTS (mobule: GRA, IIC) */ 478 /* PTS (mobule: GRA, IIC) */
400 DDC1_MARK, DDC0_MARK, 479 DDC1_MARK, DDC0_MARK, SDA5_MARK, SCL5_MARK,
401 SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK,
402 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK, 480 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK,
481 SDA9_MARK, SCL9_MARK,
403 482
404 /* PTT (mobule: SYSTEM, PWMX) */ 483 /* PTT (mobule: PWMX, AUD) */
405 AUDSYNC_MARK, AUDCK_MARK, 484 PWMX7_MARK, PWMX6_MARK, PWMX5_MARK, PWMX4_MARK,
406 AUDATA3_MARK, AUDATA2_MARK, 485 PWMX3_MARK, PWMX2_MARK, PWMX1_MARK, PWMX0_MARK,
407 AUDATA1_MARK, AUDATA0_MARK, 486 AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
408 PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK, 487 STATUS1_MARK, STATUS0_MARK,
409 488
410 /* PTU (mobule: LBSC, DMAC) */ 489 /* PTU (mobule: LPC, APM) */
411 CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK, 490 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
412 RD_MARK, WE0_MARK, A25_MARK, A24_MARK, 491 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
413 DREQ0_MARK, DACK0_MARK, 492 APMONCTL_O_MARK, APMPWBTOUT_O_MARK, APMSCI_O_MARK,
493 APMVDDON_MARK, APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK,
494 APMS3N_MARK,
414 495
415 /* PTV (mobule: LBSC, DMAC) */ 496 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
416 A23_MARK, A22_MARK, A21_MARK, A20_MARK, 497 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
417 A19_MARK, A18_MARK, A17_MARK, A16_MARK, 498 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
418 TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK, 499 COM2_RI_MARK, R_SPI_MOSI_MARK, R_SPI_MISO_MARK,
500 R_SPI_RSPCK_MARK, R_SPI_SSL0_MARK, R_SPI_SSL1_MARK,
501 EVENT7_MARK, EVENT6_MARK, VBIOS_DI_MARK, VBIOS_DO_MARK,
502 VBIOS_CLK_MARK, VBIOS_CS_MARK,
419 503
420 /* PTW (mobule: LBSC) */ 504 /* PTW (mobule: LBSC, EVC, SCIF) */
421 A15_MARK, A14_MARK, A13_MARK, A12_MARK, 505 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
422 A11_MARK, A10_MARK, A9_MARK, A8_MARK, 506 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
507 EVENT5_MARK, EVENT4_MARK, EVENT3_MARK, EVENT2_MARK,
508 EVENT1_MARK, EVENT0_MARK, CTS4_MARK, CTS2_MARK,
423 509
424 /* PTX (mobule: LBSC) */ 510 /* PTX (mobule: LBSC, SCIF, SIM) */
425 A7_MARK, A6_MARK, A5_MARK, A4_MARK, 511 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
426 A3_MARK, A2_MARK, A1_MARK, A0_MARK, 512 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
513 RTS2_MARK, SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
427 514
428 /* PTY (mobule: LBSC) */ 515 /* PTY (mobule: LBSC) */
429 D7_MARK, D6_MARK, D5_MARK, D4_MARK, 516 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
430 D3_MARK, D2_MARK, D1_MARK, D0_MARK, 517 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
518
519 /* PTZ (mobule: eMMC, ONFI) */
520 MMCDAT7_MARK, MMCDAT6_MARK, MMCDAT5_MARK, MMCDAT4_MARK,
521 MMCDAT3_MARK, MMCDAT2_MARK, MMCDAT1_MARK, MMCDAT0_MARK,
522 ON_DQ7_MARK, ON_DQ6_MARK, ON_DQ5_MARK, ON_DQ4_MARK,
523 ON_DQ3_MARK, ON_DQ2_MARK, ON_DQ1_MARK, ON_DQ0_MARK,
524
431 PINMUX_MARK_END, 525 PINMUX_MARK_END,
432}; 526};
433 527
@@ -473,6 +567,8 @@ static pinmux_enum_t pinmux_data[] = {
473 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), 567 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
474 568
475 /* PTE GPIO */ 569 /* PTE GPIO */
570 PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
571 PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
476 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), 572 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
477 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), 573 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
478 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), 574 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
@@ -521,7 +617,6 @@ static pinmux_enum_t pinmux_data[] = {
521 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT), 617 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
522 618
523 /* PTJ GPIO */ 619 /* PTJ GPIO */
524 PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT),
525 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), 620 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
526 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), 621 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
527 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), 622 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
@@ -541,7 +636,6 @@ static pinmux_enum_t pinmux_data[] = {
541 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), 636 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
542 637
543 /* PTL GPIO */ 638 /* PTL GPIO */
544 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
545 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), 639 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
546 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), 640 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
547 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), 641 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
@@ -560,7 +654,6 @@ static pinmux_enum_t pinmux_data[] = {
560 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), 654 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
561 655
562 /* PTN GPIO */ 656 /* PTN GPIO */
563 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
564 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), 657 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
565 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), 658 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
566 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), 659 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
@@ -609,6 +702,8 @@ static pinmux_enum_t pinmux_data[] = {
609 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), 702 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
610 703
611 /* PTT GPIO */ 704 /* PTT GPIO */
705 PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
706 PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
612 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), 707 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
613 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), 708 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
614 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), 709 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
@@ -677,186 +772,204 @@ static pinmux_enum_t pinmux_data[] = {
677 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), 772 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
678 773
679 /* PTA FN */ 774 /* PTA FN */
680 PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN), 775 PINMUX_DATA(BS_MARK, PTA7_FN),
681 PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN), 776 PINMUX_DATA(RDWR_MARK, PTA6_FN),
682 PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN), 777 PINMUX_DATA(WE1_MARK, PTA5_FN),
683 PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN), 778 PINMUX_DATA(RDY_MARK, PTA4_FN),
684 PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN), 779 PINMUX_DATA(ET0_MDC_MARK, PTA3_FN),
685 PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN), 780 PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN),
686 PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN), 781 PINMUX_DATA(ET1_MDC_MARK, PTA1_FN),
687 PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN), 782 PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN),
688 PINMUX_DATA(LGPIO3_MARK, PTA3_FN),
689 PINMUX_DATA(LGPIO2_MARK, PTA2_FN),
690 PINMUX_DATA(LGPIO1_MARK, PTA1_FN),
691 PINMUX_DATA(LGPIO0_MARK, PTA0_FN),
692 783
693 /* PTB FN */ 784 /* PTB FN */
694 PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN), 785 PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN),
695 PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN), 786 PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN),
696 PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN), 787 PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN),
697 PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN), 788 PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN),
698 PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN), 789 PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN),
699 PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN), 790 PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN),
700 PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN), 791 PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN),
701 PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN), 792 PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN),
702 PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN), 793 PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN),
703 PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN), 794 PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN),
704 PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN), 795 PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN),
705 PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN), 796 PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN),
706 PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN), 797 PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN),
707 PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN), 798 PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN),
708 PINMUX_DATA(D8_MARK, PTB0_FN), 799 PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN),
800 PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN),
709 801
710 /* PTC FN */ 802 /* PTC FN */
711 PINMUX_DATA(SD_WP_MARK, PTC7_FN), 803 PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN),
712 PINMUX_DATA(SD_CD_MARK, PTC6_FN), 804 PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN),
713 PINMUX_DATA(SD_CLK_MARK, PTC5_FN), 805 PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN),
714 PINMUX_DATA(SD_CMD_MARK, PTC4_FN), 806 PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN),
715 PINMUX_DATA(SD_D3_MARK, PTC3_FN), 807 PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN),
716 PINMUX_DATA(SD_D2_MARK, PTC2_FN), 808 PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN),
717 PINMUX_DATA(SD_D1_MARK, PTC1_FN), 809 PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN),
718 PINMUX_DATA(SD_D0_MARK, PTC0_FN), 810 PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN),
811 PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN),
812 PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN),
813 PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN),
814 PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN),
815 PINMUX_DATA(IRQ1_MARK, PTC1_FN),
816 PINMUX_DATA(IRQ0_MARK, PTC0_FN),
719 817
720 /* PTD FN */ 818 /* PTD FN */
721 PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN), 819 PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN),
722 PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN), 820 PINMUX_DATA(SP0_MISO_MARK, PTD6_FN),
723 PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN), 821 PINMUX_DATA(SP0_SCK_MARK, PTD5_FN),
724 PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN), 822 PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN),
725 PINMUX_DATA(IRQ5_MARK, PTD5_FN), 823 PINMUX_DATA(SP0_SS0_MARK, PTD3_FN),
726 PINMUX_DATA(IRQ4_MARK, PTD4_FN), 824 PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN),
727 PINMUX_DATA(IRQ3_MARK, PTD3_FN), 825 PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN),
728 PINMUX_DATA(IRQ2_MARK, PTD2_FN), 826 PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN),
729 PINMUX_DATA(IRQ1_MARK, PTD1_FN), 827 PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN),
730 PINMUX_DATA(IRQ0_MARK, PTD0_FN), 828 PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN),
829 PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN),
731 830
732 /* PTE FN */ 831 /* PTE FN */
733 PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN), 832 PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN),
734 PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN), 833 PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN),
735 PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN), 834 PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN),
736 PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN), 835 PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN),
737 PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN), 836 PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN),
738 PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN), 837 PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN),
739 PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN), 838 PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN),
740 PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN), 839 PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN),
741 840
742 /* PTF FN */ 841 /* PTF FN */
743 PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN), 842 PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN),
744 PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN), 843 PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN),
745 PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN), 844 PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN),
746 PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN), 845 PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN),
747 PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN), 846 PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN),
748 PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN), 847 PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN),
749 PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN), 848 PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN),
750 PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN), 849 PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN),
850 PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN),
751 851
752 /* PTG FN */ 852 /* PTG FN */
753 PINMUX_DATA(PWX0_MARK, PTG7_FN), 853 PINMUX_DATA(BOOTFMS_MARK, PTG7_FN),
754 PINMUX_DATA(PWX1_MARK, PTG6_FN), 854 PINMUX_DATA(BOOTWP_MARK, PTG6_FN),
755 PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN), 855 PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN),
756 PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN), 856 PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN),
757 PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN), 857 PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN),
758 PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN), 858 PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN),
759 PINMUX_DATA(SERIRQ_MARK, PTG3_FN), 859 PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
760 PINMUX_DATA(CLKRUN_MARK, PTG2_FN), 860 PINMUX_DATA(WDTOVF_MARK, PTG2_FN),
761 PINMUX_DATA(LPCPD_MARK, PTG1_FN), 861 PINMUX_DATA(LPCPD_MARK, PTG1_FN),
762 PINMUX_DATA(LDRQ_MARK, PTG0_FN), 862 PINMUX_DATA(LDRQ_MARK, PTG0_FN),
763 863
764 /* PTH FN */ 864 /* PTH FN */
765 PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN), 865 PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN),
766 PINMUX_DATA(SP1_MISO_MARK, PTH6_FN), 866 PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN),
767 PINMUX_DATA(SP1_SCK_MARK, PTH5_FN), 867 PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN),
768 PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN), 868 PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN),
869 PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN),
870 PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN),
871 PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN),
872 PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN),
769 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN), 873 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
770 PINMUX_DATA(TCLK_MARK, PTH2_FN), 874 PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN),
771 PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN), 875 PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN),
772 PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN), 876 PINMUX_DATA(WP_MARK, PTH1_FN),
773 PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN), 877 PINMUX_DATA(FMS0_MARK, PTH0_FN),
774 PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN),
775 878
776 /* PTI FN */ 879 /* PTI FN */
777 PINMUX_DATA(IRQ15_MARK, PTI7_FN), 880 PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN),
778 PINMUX_DATA(IRQ14_MARK, PTI6_FN), 881 PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN),
779 PINMUX_DATA(IRQ13_MARK, PTI5_FN), 882 PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN),
780 PINMUX_DATA(IRQ12_MARK, PTI4_FN), 883 PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN),
781 PINMUX_DATA(IRQ11_MARK, PTI3_FN), 884 PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN),
782 PINMUX_DATA(IRQ10_MARK, PTI2_FN), 885 PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN),
783 PINMUX_DATA(IRQ9_MARK, PTI1_FN), 886 PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN),
784 PINMUX_DATA(IRQ8_MARK, PTI0_FN), 887 PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN),
888 PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN),
889 PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN),
890 PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN),
891 PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN),
892 PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN),
893 PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN),
894 PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN),
895 PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN),
785 896
786 /* PTJ FN */ 897 /* PTJ FN */
787 PINMUX_DATA(RXD3_MARK, PTJ7_FN), 898 PINMUX_DATA(RTS3_MARK, PTJ6_FN),
788 PINMUX_DATA(TXD3_MARK, PTJ6_FN), 899 PINMUX_DATA(CTS3_MARK, PTJ5_FN),
789 PINMUX_DATA(RXD2_MARK, PTJ5_FN), 900 PINMUX_DATA(TXD3_MARK, PTJ4_FN),
790 PINMUX_DATA(TXD2_MARK, PTJ4_FN), 901 PINMUX_DATA(RXD3_MARK, PTJ3_FN),
791 PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN), 902 PINMUX_DATA(RTS4_MARK, PTJ2_FN),
792 PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN), 903 PINMUX_DATA(RXD4_MARK, PTJ1_FN),
793 PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN), 904 PINMUX_DATA(TXD4_MARK, PTJ0_FN),
794 PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN),
795 905
796 /* PTK FN */ 906 /* PTK FN */
797 PINMUX_DATA(COM2_TXD_MARK, PTK7_FN), 907 PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN),
908 PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN),
798 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN), 909 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
799 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN), 910 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
800 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN), 911 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
801 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN), 912 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
802 PINMUX_DATA(COM2_DSR_MARK, PTK2_FN), 913 PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN),
803 PINMUX_DATA(COM2_DCD_MARK, PTK1_FN), 914 PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN),
804 PINMUX_DATA(COM2_RI_MARK, PTK0_FN), 915 PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN),
916 PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN),
917 PINMUX_DATA(CLKOUT_MARK, PTK0_FN),
805 918
806 /* PTL FN */ 919 /* PTL FN */
807 PINMUX_DATA(RAC_TXD_MARK, PTL7_FN), 920 PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN),
808 PINMUX_DATA(RAC_RXD_MARK, PTL6_FN), 921 PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN),
809 PINMUX_DATA(RAC_RTS_MARK, PTL5_FN), 922 PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN),
810 PINMUX_DATA(RAC_CTS_MARK, PTL4_FN), 923 PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN),
924 PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN),
925 PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN),
811 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN), 926 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
812 PINMUX_DATA(RAC_DSR_MARK, PTL2_FN), 927 PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN),
813 PINMUX_DATA(RAC_DCD_MARK, PTL1_FN), 928 PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN),
814 PINMUX_DATA(RAC_RI_MARK, PTL0_FN), 929 PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN),
930 PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN),
931 PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN),
932 PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN),
815 933
816 /* PTM FN */ 934 /* PTM FN */
817 PINMUX_DATA(WP_MARK, PTM6_FN), 935 PINMUX_DATA(CS4_MARK, PTM7_FN),
818 PINMUX_DATA(FMS0_MARK, PTM5_FN), 936 PINMUX_DATA(RD_MARK, PTM6_FN),
819 PINMUX_DATA(FMS1_MARK, PTM4_FN), 937 PINMUX_DATA(WE0_MARK, PTM7_FN),
938 PINMUX_DATA(CS0_MARK, PTM4_FN),
820 PINMUX_DATA(SDA6_MARK, PTM3_FN), 939 PINMUX_DATA(SDA6_MARK, PTM3_FN),
821 PINMUX_DATA(SCL6_MARK, PTM2_FN), 940 PINMUX_DATA(SCL6_MARK, PTM2_FN),
822 PINMUX_DATA(SDA7_MARK, PTM1_FN), 941 PINMUX_DATA(SDA7_MARK, PTM1_FN),
823 PINMUX_DATA(SCL7_MARK, PTM0_FN), 942 PINMUX_DATA(SCL7_MARK, PTM0_FN),
824 943
825 /* PTN FN */ 944 /* PTN FN */
826 PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN), 945 PINMUX_DATA(VBUS_EN_MARK, PTN6_FN),
827 PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN), 946 PINMUX_DATA(VBUS_OC_MARK, PTN5_FN),
828 PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN), 947 PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN),
829 PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN), 948 PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN),
830 PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN), 949 PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN),
831 PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN), 950 PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN),
832 PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN), 951 PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN),
833 PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN), 952 PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN),
834 PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN), 953 PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN),
835 PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN), 954 PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN),
836 PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN), 955 PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN),
837 PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN), 956 PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN),
838 PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN),
839 PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN),
840 PINMUX_DATA(EVENT0_MARK, PTN0_FN),
841 957
842 /* PTO FN */ 958 /* PTO FN */
843 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN), 959 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
844 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN), 960 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
845 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN), 961 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
846 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN), 962 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
847 PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN), 963 PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN),
848 PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN), 964 PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN),
849 PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN), 965 PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN),
850 PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN), 966 PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN),
967 PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN),
968 PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN),
969 PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN),
970 PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN),
851 971
852 /* PTP FN */ 972 /* PTP FN */
853 PINMUX_DATA(JMCTCK_MARK, PTP6_FN),
854 PINMUX_DATA(JMCTMS_MARK, PTP5_FN),
855 PINMUX_DATA(JMCTDO_MARK, PTP4_FN),
856 PINMUX_DATA(JMCTDI_MARK, PTP3_FN),
857 PINMUX_DATA(JMCRST_MARK, PTP2_FN),
858 PINMUX_DATA(SCK4_MARK, PTP1_FN),
859 PINMUX_DATA(SCK3_MARK, PTP0_FN),
860 973
861 /* PTQ FN */ 974 /* PTQ FN */
862 PINMUX_DATA(LAD3_MARK, PTQ6_FN), 975 PINMUX_DATA(LAD3_MARK, PTQ6_FN),
@@ -864,8 +977,8 @@ static pinmux_enum_t pinmux_data[] = {
864 PINMUX_DATA(LAD1_MARK, PTQ4_FN), 977 PINMUX_DATA(LAD1_MARK, PTQ4_FN),
865 PINMUX_DATA(LAD0_MARK, PTQ3_FN), 978 PINMUX_DATA(LAD0_MARK, PTQ3_FN),
866 PINMUX_DATA(LFRAME_MARK, PTQ2_FN), 979 PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
867 PINMUX_DATA(SCK4_MARK, PTQ1_FN), 980 PINMUX_DATA(LRESET_MARK, PTQ1_FN),
868 PINMUX_DATA(SCK3_MARK, PTQ0_FN), 981 PINMUX_DATA(LCLK_MARK, PTQ0_FN),
869 982
870 /* PTR FN */ 983 /* PTR FN */
871 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */ 984 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */
@@ -888,58 +1001,84 @@ static pinmux_enum_t pinmux_data[] = {
888 PINMUX_DATA(SCL3_MARK, PTS0_FN), 1001 PINMUX_DATA(SCL3_MARK, PTS0_FN),
889 1002
890 /* PTT FN */ 1003 /* PTT FN */
891 PINMUX_DATA(AUDSYNC_MARK, PTS5_FN), 1004 PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN),
892 PINMUX_DATA(AUDCK_MARK, PTS4_FN), 1005 PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN),
893 PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN), 1006 PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN),
894 PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN), 1007 PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN),
895 PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN), 1008 PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN),
896 PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN), 1009 PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN),
897 PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN), 1010 PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN),
898 PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN), 1011 PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN),
899 PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN), 1012 PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN),
900 PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN), 1013 PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN),
1014 PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN),
1015 PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN),
1016 PINMUX_DATA(PWMX1_MARK, PTT1_FN),
1017 PINMUX_DATA(PWMX0_MARK, PTT0_FN),
901 1018
902 /* PTU FN */ 1019 /* PTU FN */
903 PINMUX_DATA(CS6_MARK, PTU7_FN), 1020 PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN),
904 PINMUX_DATA(CS5_MARK, PTU6_FN), 1021 PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN),
905 PINMUX_DATA(CS4_MARK, PTU5_FN), 1022 PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN),
906 PINMUX_DATA(CS0_MARK, PTU4_FN), 1023 PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN),
907 PINMUX_DATA(RD_MARK, PTU3_FN), 1024 PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN),
908 PINMUX_DATA(WE0_MARK, PTU2_FN), 1025 PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN),
909 PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN), 1026 PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN),
910 PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN), 1027 PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN),
911 PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN), 1028 PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN),
912 PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN), 1029 PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN),
1030 PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN),
1031 PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN),
1032 PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN),
1033 PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN),
1034 PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN),
1035 PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN),
913 1036
914 /* PTV FN */ 1037 /* PTV FN */
915 PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN), 1038 PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN),
916 PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN), 1039 PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN),
917 PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN), 1040 PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN),
918 PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN), 1041 PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN),
919 PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN), 1042 PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN),
920 PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN), 1043 PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN),
921 PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN), 1044 PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN),
922 PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN), 1045 PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN),
923 PINMUX_DATA(A19_MARK, PTV3_FN), 1046 PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN),
924 PINMUX_DATA(A18_MARK, PTV2_FN), 1047 PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN),
925 PINMUX_DATA(A17_MARK, PTV1_FN), 1048 PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN),
926 PINMUX_DATA(A16_MARK, PTV0_FN), 1049 PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN),
1050 PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN),
1051 PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN),
1052 PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN),
1053 PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN),
927 1054
928 /* PTW FN */ 1055 /* PTW FN */
929 PINMUX_DATA(A15_MARK, PTW7_FN), 1056 PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN),
930 PINMUX_DATA(A14_MARK, PTW6_FN), 1057 PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN),
931 PINMUX_DATA(A13_MARK, PTW5_FN), 1058 PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN),
932 PINMUX_DATA(A12_MARK, PTW4_FN), 1059 PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN),
933 PINMUX_DATA(A11_MARK, PTW3_FN), 1060 PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN),
934 PINMUX_DATA(A10_MARK, PTW2_FN), 1061 PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN),
935 PINMUX_DATA(A9_MARK, PTW1_FN), 1062 PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN),
936 PINMUX_DATA(A8_MARK, PTW0_FN), 1063 PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN),
1064 PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN),
1065 PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN),
1066 PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN),
1067 PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN),
1068 PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN),
1069 PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN),
1070 PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN),
1071 PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN),
937 1072
938 /* PTX FN */ 1073 /* PTX FN */
939 PINMUX_DATA(A7_MARK, PTX7_FN), 1074 PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN),
940 PINMUX_DATA(A6_MARK, PTX6_FN), 1075 PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN),
941 PINMUX_DATA(A5_MARK, PTX5_FN), 1076 PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN),
942 PINMUX_DATA(A4_MARK, PTX4_FN), 1077 PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN),
1078 PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN),
1079 PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN),
1080 PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN),
1081 PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN),
943 PINMUX_DATA(A3_MARK, PTX3_FN), 1082 PINMUX_DATA(A3_MARK, PTX3_FN),
944 PINMUX_DATA(A2_MARK, PTX2_FN), 1083 PINMUX_DATA(A2_MARK, PTX2_FN),
945 PINMUX_DATA(A1_MARK, PTX1_FN), 1084 PINMUX_DATA(A1_MARK, PTX1_FN),
@@ -954,6 +1093,24 @@ static pinmux_enum_t pinmux_data[] = {
954 PINMUX_DATA(D2_MARK, PTY2_FN), 1093 PINMUX_DATA(D2_MARK, PTY2_FN),
955 PINMUX_DATA(D1_MARK, PTY1_FN), 1094 PINMUX_DATA(D1_MARK, PTY1_FN),
956 PINMUX_DATA(D0_MARK, PTY0_FN), 1095 PINMUX_DATA(D0_MARK, PTY0_FN),
1096
1097 /* PTZ FN */
1098 PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN),
1099 PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN),
1100 PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN),
1101 PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN),
1102 PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN),
1103 PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN),
1104 PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN),
1105 PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN),
1106 PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN),
1107 PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN),
1108 PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN),
1109 PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN),
1110 PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN),
1111 PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN),
1112 PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN),
1113 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
957}; 1114};
958 1115
959static struct pinmux_gpio pinmux_gpios[] = { 1116static struct pinmux_gpio pinmux_gpios[] = {
@@ -1048,7 +1205,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1048 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), 1205 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
1049 1206
1050 /* PTJ */ 1207 /* PTJ */
1051 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1052 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), 1208 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1053 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), 1209 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1054 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), 1210 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
@@ -1068,7 +1224,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1068 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), 1224 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1069 1225
1070 /* PTL */ 1226 /* PTL */
1071 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1072 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), 1227 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1073 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), 1228 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1074 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), 1229 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
@@ -1078,6 +1233,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1078 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), 1233 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1079 1234
1080 /* PTM */ 1235 /* PTM */
1236 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1081 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), 1237 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1082 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), 1238 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1083 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), 1239 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
@@ -1087,7 +1243,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1087 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), 1243 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1088 1244
1089 /* PTN */ 1245 /* PTN */
1090 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1091 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), 1246 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1092 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), 1247 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1093 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), 1248 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
@@ -1107,6 +1262,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1107 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), 1262 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
1108 1263
1109 /* PTP */ 1264 /* PTP */
1265 PINMUX_GPIO(GPIO_PTP7, PTP7_DATA),
1110 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), 1266 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
1111 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), 1267 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
1112 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), 1268 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
@@ -1145,6 +1301,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
1145 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), 1301 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1146 1302
1147 /* PTT */ 1303 /* PTT */
1304 PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
1305 PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
1148 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), 1306 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1149 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), 1307 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1150 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), 1308 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
@@ -1212,54 +1370,35 @@ static struct pinmux_gpio pinmux_gpios[] = {
1212 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1370 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1213 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1371 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1214 1372
1215 /* PTA (mobule: LBSC, CPG, LPC) */ 1373 /* PTA (mobule: LBSC, RGMII) */
1216 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1374 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1217 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1375 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1218 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), 1376 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
1219 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), 1377 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
1220 PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK),
1221 PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK),
1222 PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK),
1223 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1224 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1225 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1226 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1227 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1228 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1229 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1230 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1231
1232 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
1233 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1234 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1235 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1236 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1237 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1238 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1239 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1240 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1241 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), 1378 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
1242 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), 1379 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK),
1243 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), 1380 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
1244 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), 1381 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK),
1245 PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK),
1246 PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK),
1247 PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK),
1248 PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK),
1249 PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK),
1250 PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK),
1251
1252 /* PTC (mobule: SD) */
1253 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1254 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1255 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1256 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1257 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1258 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1259 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1260 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1261 1382
1262 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ 1383 /* PTB (mobule: INTC, ONFI, TMU) */
1384 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
1385 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
1386 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
1387 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
1388 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
1389 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
1390 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
1391 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
1392 PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
1393 PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
1394 PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
1395 PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
1396 PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
1397 PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
1398 PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
1399 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1400
1401 /* PTC (mobule: IRQ, PWMU) */
1263 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1402 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1264 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1403 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1265 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1404 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
@@ -1268,80 +1407,102 @@ static struct pinmux_gpio pinmux_gpios[] = {
1268 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1407 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1269 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1408 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1270 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1409 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1271 PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK), 1410 PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
1272 PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK), 1411 PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
1273 PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK), 1412 PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
1274 PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK), 1413 PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
1275 PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK), 1414 PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
1276 PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK), 1415 PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
1277 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), 1416
1278 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), 1417 /* PTD (mobule: SPI0, DMAC) */
1418 PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
1419 PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
1420 PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
1421 PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
1422 PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
1423 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
1424 PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
1425 PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
1426 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1427 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1428 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1279 1429
1280 /* PTE (mobule: EtherC) */ 1430 /* PTE (mobule: RMII) */
1281 PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK), 1431 PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
1282 PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK), 1432 PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
1283 PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK), 1433 PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
1284 PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK), 1434 PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
1285 PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK), 1435 PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
1286 PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK), 1436 PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
1287 PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK), 1437 PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
1288 PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK), 1438 PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
1289 1439
1290 /* PTF (mobule: EtherC) */ 1440 /* PTF (mobule: RMII, SerMux) */
1291 PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK), 1441 PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
1292 PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK), 1442 PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
1293 PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK), 1443 PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
1294 PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK), 1444 PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
1295 PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK), 1445 PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
1296 PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK), 1446 PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
1297 PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK), 1447 PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
1298 PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK), 1448 PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
1299 1449 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
1300 /* PTG (mobule: SYSTEM, PWMX, LPC) */ 1450
1301 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1451 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
1302 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 1452 PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
1303 PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK), 1453 PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
1304 PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK), 1454 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1305 PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK), 1455 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1306 PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK),
1307 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), 1456 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
1308 PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK), 1457 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
1309 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), 1458 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
1310 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), 1459 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
1460 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
1461 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
1311 1462
1312 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ 1463 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
1313 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1314 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1315 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1316 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), 1464 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
1317 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), 1465 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
1318 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), 1466 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
1319 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), 1467 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
1320 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), 1468 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
1321 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), 1469 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
1322 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), 1470 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1471 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1472 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1473 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1474 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1475 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
1476 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
1323 1477
1324 /* PTI (mobule: INTC) */ 1478 /* PTI (mobule: LBSC, SDHI) */
1325 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), 1479 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1326 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), 1480 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1327 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), 1481 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1328 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), 1482 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1329 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), 1483 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1330 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), 1484 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1331 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), 1485 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1332 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), 1486 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1487 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1488 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1489 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1490 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1491 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1492 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1493 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1494 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1333 1495
1334 /* PTJ (mobule: SCIF234, SERMUX) */ 1496 /* PTJ (mobule: SCIF234, SERMUX) */
1335 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1497 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1498 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1336 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1499 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1337 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1500 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1338 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1501 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
1339 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), 1502 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1340 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), 1503 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1341 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1342 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1343 1504
1344 /* PTK (mobule: SERMUX) */ 1505 /* PTK (mobule: SERMUX, LBSC, SCIF) */
1345 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), 1506 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
1346 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), 1507 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
1347 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), 1508 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
@@ -1349,62 +1510,65 @@ static struct pinmux_gpio pinmux_gpios[] = {
1349 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), 1510 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
1350 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), 1511 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
1351 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), 1512 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
1352 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), 1513 PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
1514 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1515 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1516 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1353 1517
1354 /* PTL (mobule: SERMUX) */ 1518 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
1355 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1356 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), 1519 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
1357 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), 1520 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
1358 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), 1521 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
1359 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), 1522 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
1360 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), 1523 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
1361 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), 1524 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
1362 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), 1525 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1526 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1527 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1528 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1529 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1530 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1531 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1363 1532
1364 /* PTM (mobule: IIC, LPC) */ 1533 /* PTM (mobule: LBSC, IIC) */
1534 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1535 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1536 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1537 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1365 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), 1538 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
1366 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), 1539 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
1367 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), 1540 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
1368 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), 1541 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
1369 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1370 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1371 PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK),
1372 1542
1373 /* PTN (mobule: SCIF234, EVC) */ 1543 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
1374 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1544 PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
1375 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), 1545 PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
1376 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1546 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1377 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), 1547 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1378 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), 1548 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1379 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1549 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1380 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), 1550 PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
1381 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), 1551 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
1382 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), 1552 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
1383 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), 1553 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
1384 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), 1554 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
1385 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), 1555 PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
1386 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1387 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1388 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1389 1556
1390 /* PTO (mobule: SGPIO) */ 1557 /* PTO (mobule: SGPIO, SerMux) */
1391 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), 1558 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
1392 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), 1559 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
1393 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), 1560 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
1394 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), 1561 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
1395 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), 1562 PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
1396 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), 1563 PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
1397 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), 1564 PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
1398 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), 1565 PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
1566 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
1567 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
1568 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1569 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1399 1570
1400 /* PTP (mobule: JMC, SCIF234) */ 1571 /* PTP (mobule: EVC, ADC) */
1401 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1402 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1403 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1404 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1405 PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK),
1406 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1407 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1408 1572
1409 /* PTQ (mobule: LPC) */ 1573 /* PTQ (mobule: LPC) */
1410 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), 1574 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
@@ -1439,31 +1603,41 @@ static struct pinmux_gpio pinmux_gpios[] = {
1439 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), 1603 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
1440 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), 1604 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
1441 1605
1442 /* PTT (mobule: SYSTEM, PWMX) */ 1606 /* PTT (mobule: PWMX, AUD) */
1443 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1607 PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
1444 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1608 PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
1609 PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
1610 PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
1611 PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
1612 PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
1613 PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
1614 PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
1445 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1615 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1446 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1616 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1447 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1617 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1448 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1618 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1449 PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK), 1619 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
1450 PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK), 1620 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1451 PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK),
1452 PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK),
1453
1454 /* PTU (mobule: LBSC, DMAC) */
1455 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1456 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1457 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1459 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1460 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1461 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1462 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1463 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1464 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1465 1621
1466 /* PTV (mobule: LBSC, DMAC) */ 1622 /* PTU (mobule: LPC, APM) */
1623 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1624 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1625 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1626 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1627 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1628 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1629 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1630 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1631 PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
1632 PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
1633 PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
1634 PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
1635 PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
1636 PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
1637 PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
1638 PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
1639
1640 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
1467 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1641 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1468 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1642 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1469 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1643 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
@@ -1472,12 +1646,20 @@ static struct pinmux_gpio pinmux_gpios[] = {
1472 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1646 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1473 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1647 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1474 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1648 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1475 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1649 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
1476 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1650 PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
1477 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1651 PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
1478 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1652 PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
1653 PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
1654 PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
1655 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
1656 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
1657 PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
1658 PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
1659 PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
1660 PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
1479 1661
1480 /* PTW (mobule: LBSC) */ 1662 /* PTW (mobule: LBSC, EVC, SCIF) */
1481 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1663 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1482 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1664 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1483 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1665 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
@@ -1487,6 +1669,14 @@ static struct pinmux_gpio pinmux_gpios[] = {
1487 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1669 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1488 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1670 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1489 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1671 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1672 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
1673 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
1674 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
1675 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1676 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1677 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1678 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
1679 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
1490 1680
1491 /* PTX (mobule: LBSC) */ 1681 /* PTX (mobule: LBSC) */
1492 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1682 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
@@ -1497,6 +1687,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
1497 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1687 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1498 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1688 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1499 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1689 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1690 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
1691 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
1692 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
1693 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
1500 1694
1501 /* PTY (mobule: LBSC) */ 1695 /* PTY (mobule: LBSC) */
1502 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1696 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
@@ -1507,18 +1701,36 @@ static struct pinmux_gpio pinmux_gpios[] = {
1507 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1701 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1508 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1702 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1509 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1703 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1704
1705 /* PTZ (mobule: eMMC, ONFI) */
1706 PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
1707 PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
1708 PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
1709 PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
1710 PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
1711 PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
1712 PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
1713 PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
1714 PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
1715 PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
1716 PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
1717 PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
1718 PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
1719 PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
1720 PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
1721 PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
1510 }; 1722 };
1511 1723
1512static struct pinmux_cfg_reg pinmux_config_regs[] = { 1724static struct pinmux_cfg_reg pinmux_config_regs[] = {
1513 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { 1725 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1514 PTA7_FN, PTA7_OUT, PTA7_IN, 0, 1726 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
1515 PTA6_FN, PTA6_OUT, PTA6_IN, 0, 1727 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
1516 PTA5_FN, PTA5_OUT, PTA5_IN, 0, 1728 PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
1517 PTA4_FN, PTA4_OUT, PTA4_IN, 0, 1729 PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
1518 PTA3_FN, PTA3_OUT, PTA3_IN, 0, 1730 PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
1519 PTA2_FN, PTA2_OUT, PTA2_IN, 0, 1731 PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
1520 PTA1_FN, PTA1_OUT, PTA1_IN, 0, 1732 PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
1521 PTA0_FN, PTA0_OUT, PTA0_IN, 0 } 1733 PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU }
1522 }, 1734 },
1523 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { 1735 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
1524 PTB7_FN, PTB7_OUT, PTB7_IN, 0, 1736 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
@@ -1541,125 +1753,126 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1541 PTC0_FN, PTC0_OUT, PTC0_IN, 0 } 1753 PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
1542 }, 1754 },
1543 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { 1755 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
1544 PTD7_FN, PTD7_OUT, PTD7_IN, 0, 1756 PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU,
1545 PTD6_FN, PTD6_OUT, PTD6_IN, 0, 1757 PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU,
1546 PTD5_FN, PTD5_OUT, PTD5_IN, 0, 1758 PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU,
1547 PTD4_FN, PTD4_OUT, PTD4_IN, 0, 1759 PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU,
1548 PTD3_FN, PTD3_OUT, PTD3_IN, 0, 1760 PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU,
1549 PTD2_FN, PTD2_OUT, PTD2_IN, 0, 1761 PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU,
1550 PTD1_FN, PTD1_OUT, PTD1_IN, 0, 1762 PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU,
1551 PTD0_FN, PTD0_OUT, PTD0_IN, 0 } 1763 PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU }
1552 }, 1764 },
1553 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { 1765 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
1554 PTE7_FN, PTE7_OUT, PTE7_IN, 0, 1766 PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU,
1555 PTE6_FN, PTE6_OUT, PTE6_IN, 0, 1767 PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU,
1556 PTE5_FN, PTE5_OUT, PTE5_IN, 0, 1768 PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU,
1557 PTE4_FN, PTE4_OUT, PTE4_IN, 0, 1769 PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU,
1558 PTE3_FN, PTE3_OUT, PTE3_IN, 0, 1770 PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU,
1559 PTE2_FN, PTE2_OUT, PTE2_IN, 0, 1771 PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU,
1560 PTE1_FN, PTE1_OUT, PTE1_IN, 0, 1772 PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU,
1561 PTE0_FN, PTE0_OUT, PTE0_IN, 0 } 1773 PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU }
1562 }, 1774 },
1563 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { 1775 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
1564 PTF7_FN, PTF7_OUT, PTF7_IN, 0, 1776 PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU,
1565 PTF6_FN, PTF6_OUT, PTF6_IN, 0, 1777 PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU,
1566 PTF5_FN, PTF5_OUT, PTF5_IN, 0, 1778 PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU,
1567 PTF4_FN, PTF4_OUT, PTF4_IN, 0, 1779 PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU,
1568 PTF3_FN, PTF3_OUT, PTF3_IN, 0, 1780 PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU,
1569 PTF2_FN, PTF2_OUT, PTF2_IN, 0, 1781 PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU,
1570 PTF1_FN, PTF1_OUT, PTF1_IN, 0, 1782 PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU,
1571 PTF0_FN, PTF0_OUT, PTF0_IN, 0 } 1783 PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU }
1572 }, 1784 },
1573 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { 1785 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
1574 PTG7_FN, PTG7_OUT, PTG7_IN, 0, 1786 PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU ,
1575 PTG6_FN, PTG6_OUT, PTG6_IN, 0, 1787 PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU ,
1576 PTG5_FN, PTG5_OUT, PTG5_IN, 0, 1788 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
1577 PTG4_FN, PTG4_OUT, PTG4_IN, 0, 1789 PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU ,
1578 PTG3_FN, PTG3_OUT, PTG3_IN, 0, 1790 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
1579 PTG2_FN, PTG2_OUT, PTG2_IN, 0, 1791 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
1580 PTG1_FN, PTG1_OUT, PTG1_IN, 0, 1792 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
1581 PTG0_FN, PTG0_OUT, PTG0_IN, 0 } 1793 PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
1582 }, 1794 },
1583 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { 1795 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
1584 PTH7_FN, PTH7_OUT, PTH7_IN, 0, 1796 PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU,
1585 PTH6_FN, PTH6_OUT, PTH6_IN, 0, 1797 PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU,
1586 PTH5_FN, PTH5_OUT, PTH5_IN, 0, 1798 PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU,
1587 PTH4_FN, PTH4_OUT, PTH4_IN, 0, 1799 PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU,
1588 PTH3_FN, PTH3_OUT, PTH3_IN, 0, 1800 PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU,
1589 PTH2_FN, PTH2_OUT, PTH2_IN, 0, 1801 PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU,
1590 PTH1_FN, PTH1_OUT, PTH1_IN, 0, 1802 PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU,
1591 PTH0_FN, PTH0_OUT, PTH0_IN, 0 } 1803 PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU }
1592 }, 1804 },
1593 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { 1805 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
1594 PTI7_FN, PTI7_OUT, PTI7_IN, 0, 1806 PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU,
1595 PTI6_FN, PTI6_OUT, PTI6_IN, 0, 1807 PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU,
1596 PTI5_FN, PTI5_OUT, PTI5_IN, 0, 1808 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
1597 PTI4_FN, PTI4_OUT, PTI4_IN, 0, 1809 PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU,
1598 PTI3_FN, PTI3_OUT, PTI3_IN, 0, 1810 PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU,
1599 PTI2_FN, PTI2_OUT, PTI2_IN, 0, 1811 PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU,
1600 PTI1_FN, PTI1_OUT, PTI1_IN, 0, 1812 PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU,
1601 PTI0_FN, PTI0_OUT, PTI0_IN, 0 } 1813 PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU }
1602 }, 1814 },
1603 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { 1815 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
1604 PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0, 1816 0, 0, 0, 0, /* reserved: always set 1 */
1605 PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, 1817 PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU,
1606 PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, 1818 PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU,
1607 PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, 1819 PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU,
1608 PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, 1820 PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU,
1609 PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, 1821 PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU,
1610 PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, 1822 PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU,
1611 PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } 1823 PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU }
1612 }, 1824 },
1613 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { 1825 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
1614 PTK7_FN, PTK7_OUT, PTK7_IN, 0, 1826 PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU,
1615 PTK6_FN, PTK6_OUT, PTK6_IN, 0, 1827 PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU,
1616 PTK5_FN, PTK5_OUT, PTK5_IN, 0, 1828 PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU,
1617 PTK4_FN, PTK4_OUT, PTK4_IN, 0, 1829 PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU,
1618 PTK3_FN, PTK3_OUT, PTK3_IN, 0, 1830 PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU,
1619 PTK2_FN, PTK2_OUT, PTK2_IN, 0, 1831 PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU,
1620 PTK1_FN, PTK1_OUT, PTK1_IN, 0, 1832 PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU,
1621 PTK0_FN, PTK0_OUT, PTK0_IN, 0 } 1833 PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU }
1622 }, 1834 },
1623 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { 1835 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
1624 PTL7_FN, PTL7_OUT, PTL7_IN, 0, 1836 0, 0, 0, 0, /* reserved: always set 1 */
1625 PTL6_FN, PTL6_OUT, PTL6_IN, 0, 1837 PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU,
1626 PTL5_FN, PTL5_OUT, PTL5_IN, 0, 1838 PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU,
1627 PTL4_FN, PTL4_OUT, PTL4_IN, 0, 1839 PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU,
1628 PTL3_FN, PTL3_OUT, PTL3_IN, 0, 1840 PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU,
1629 PTL2_FN, PTL2_OUT, PTL2_IN, 0, 1841 PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU,
1630 PTL1_FN, PTL1_OUT, PTL1_IN, 0, 1842 PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU,
1631 PTL0_FN, PTL0_OUT, PTL0_IN, 0 } 1843 PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU }
1632 }, 1844 },
1633 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { 1845 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
1634 0, 0, 0, 0, /* reserved: always set 1 */ 1846 PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU,
1635 PTM6_FN, PTM6_OUT, PTM6_IN, 0, 1847 PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU,
1636 PTM5_FN, PTM5_OUT, PTM5_IN, 0, 1848 PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU,
1637 PTM4_FN, PTM4_OUT, PTM4_IN, 0, 1849 PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU,
1638 PTM3_FN, PTM3_OUT, PTM3_IN, 0, 1850 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
1639 PTM2_FN, PTM2_OUT, PTM2_IN, 0, 1851 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
1640 PTM1_FN, PTM1_OUT, PTM1_IN, 0, 1852 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
1641 PTM0_FN, PTM0_OUT, PTM0_IN, 0 } 1853 PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
1642 }, 1854 },
1643 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) { 1855 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
1644 PTN7_FN, PTN7_OUT, PTN7_IN, 0, 1856 0, 0, 0, 0, /* reserved: always set 1 */
1645 PTN6_FN, PTN6_OUT, PTN6_IN, 0, 1857 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
1646 PTN5_FN, PTN5_OUT, PTN5_IN, 0, 1858 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
1647 PTN4_FN, PTN4_OUT, PTN4_IN, 0, 1859 PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU,
1648 PTN3_FN, PTN3_OUT, PTN3_IN, 0, 1860 PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU,
1649 PTN2_FN, PTN2_OUT, PTN2_IN, 0, 1861 PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU,
1650 PTN1_FN, PTN1_OUT, PTN1_IN, 0, 1862 PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU,
1651 PTN0_FN, PTN0_OUT, PTN0_IN, 0 } 1863 PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU }
1652 }, 1864 },
1653 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { 1865 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
1654 PTO7_FN, PTO7_OUT, PTO7_IN, 0, 1866 PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU,
1655 PTO6_FN, PTO6_OUT, PTO6_IN, 0, 1867 PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU,
1656 PTO5_FN, PTO5_OUT, PTO5_IN, 0, 1868 PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU,
1657 PTO4_FN, PTO4_OUT, PTO4_IN, 0, 1869 PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU,
1658 PTO3_FN, PTO3_OUT, PTO3_IN, 0, 1870 PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU,
1659 PTO2_FN, PTO2_OUT, PTO2_IN, 0, 1871 PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU,
1660 PTO1_FN, PTO1_OUT, PTO1_IN, 0, 1872 PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU,
1661 PTO0_FN, PTO0_OUT, PTO0_IN, 0 } 1873 PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU }
1662 }, 1874 },
1875#if 0 /* FIXME: Remove it? */
1663 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { 1876 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
1664 0, 0, 0, 0, /* reserved: always set 1 */ 1877 0, 0, 0, 0, /* reserved: always set 1 */
1665 PTP6_FN, PTP6_OUT, PTP6_IN, 0, 1878 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
@@ -1670,6 +1883,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1670 PTP1_FN, PTP1_OUT, PTP1_IN, 0, 1883 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
1671 PTP0_FN, PTP0_OUT, PTP0_IN, 0 } 1884 PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
1672 }, 1885 },
1886#endif
1673 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) { 1887 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
1674 0, 0, 0, 0, /* reserved: always set 1 */ 1888 0, 0, 0, 0, /* reserved: always set 1 */
1675 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0, 1889 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
@@ -1701,14 +1915,14 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1701 PTS0_FN, PTS0_OUT, PTS0_IN, 0 } 1915 PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
1702 }, 1916 },
1703 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { 1917 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
1704 0, 0, 0, 0, /* reserved: always set 1 */ 1918 PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU,
1705 0, 0, 0, 0, /* reserved: always set 1 */ 1919 PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU,
1706 PTT5_FN, PTT5_OUT, PTT5_IN, 0, 1920 PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU,
1707 PTT4_FN, PTT4_OUT, PTT4_IN, 0, 1921 PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU,
1708 PTT3_FN, PTT3_OUT, PTT3_IN, 0, 1922 PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU,
1709 PTT2_FN, PTT2_OUT, PTT2_IN, 0, 1923 PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU,
1710 PTT1_FN, PTT1_OUT, PTT1_IN, 0, 1924 PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU,
1711 PTT0_FN, PTT0_OUT, PTT0_IN, 0 } 1925 PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU }
1712 }, 1926 },
1713 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { 1927 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
1714 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, 1928 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
@@ -1727,16 +1941,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1727 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, 1941 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
1728 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, 1942 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
1729 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, 1943 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
1730 PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU, 1944 PTV1_FN, PTV1_OUT, PTV1_IN, 0,
1731 PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU } 1945 PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
1732 }, 1946 },
1733 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) { 1947 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
1734 PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU, 1948 PTW7_FN, PTW7_OUT, PTW7_IN, 0,
1735 PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU, 1949 PTW6_FN, PTW6_OUT, PTW6_IN, 0,
1736 PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU, 1950 PTW5_FN, PTW5_OUT, PTW5_IN, 0,
1737 PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU, 1951 PTW4_FN, PTW4_OUT, PTW4_IN, 0,
1738 PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU, 1952 PTW3_FN, PTW3_OUT, PTW3_IN, 0,
1739 PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU, 1953 PTW2_FN, PTW2_OUT, PTW2_IN, 0,
1740 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, 1954 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
1741 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } 1955 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
1742 }, 1956 },
@@ -1761,32 +1975,32 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1761 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } 1975 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
1762 }, 1976 },
1763 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { 1977 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
1764 0, PTZ7_OUT, PTZ7_IN, 0, 1978 PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
1765 0, PTZ6_OUT, PTZ6_IN, 0, 1979 PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
1766 0, PTZ5_OUT, PTZ5_IN, 0, 1980 PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
1767 0, PTZ4_OUT, PTZ4_IN, 0, 1981 PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0,
1768 0, PTZ3_OUT, PTZ3_IN, 0, 1982 PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
1769 0, PTZ2_OUT, PTZ2_IN, 0, 1983 PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
1770 0, PTZ1_OUT, PTZ1_IN, 0, 1984 PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
1771 0, PTZ0_OUT, PTZ0_IN, 0 } 1985 PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 }
1772 }, 1986 },
1773 1987
1774 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) { 1988 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
1775 PS0_15_FN3, PS0_15_FN1, 1989 PS0_15_FN1, PS0_15_FN2,
1776 PS0_14_FN3, PS0_14_FN1, 1990 PS0_14_FN1, PS0_14_FN2,
1777 PS0_13_FN3, PS0_13_FN1, 1991 PS0_13_FN1, PS0_13_FN2,
1778 PS0_12_FN3, PS0_12_FN1, 1992 PS0_12_FN1, PS0_12_FN2,
1779 0, 0, 1993 PS0_11_FN1, PS0_11_FN2,
1780 0, 0, 1994 PS0_10_FN1, PS0_10_FN2,
1995 PS0_9_FN1, PS0_9_FN2,
1996 PS0_8_FN1, PS0_8_FN2,
1997 PS0_7_FN1, PS0_7_FN2,
1998 PS0_6_FN1, PS0_6_FN2,
1999 PS0_5_FN1, PS0_5_FN2,
2000 PS0_4_FN1, PS0_4_FN2,
2001 PS0_3_FN1, PS0_3_FN2,
2002 PS0_2_FN1, PS0_2_FN2,
1781 0, 0, 2003 0, 0,
1782 0, 0,
1783 PS0_7_FN2, PS0_7_FN1,
1784 PS0_6_FN2, PS0_6_FN1,
1785 PS0_5_FN2, PS0_5_FN1,
1786 PS0_4_FN2, PS0_4_FN1,
1787 PS0_3_FN2, PS0_3_FN1,
1788 PS0_2_FN2, PS0_2_FN1,
1789 PS0_1_FN2, PS0_1_FN1,
1790 0, 0, } 2004 0, 0, }
1791 }, 2005 },
1792 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) { 2006 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
@@ -1795,73 +2009,136 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1795 0, 0, 2009 0, 0,
1796 0, 0, 2010 0, 0,
1797 0, 0, 2011 0, 0,
2012 PS1_10_FN1, PS1_10_FN2,
2013 PS1_9_FN1, PS1_9_FN2,
2014 PS1_8_FN1, PS1_8_FN2,
1798 0, 0, 2015 0, 0,
1799 0, 0, 2016 0, 0,
1800 0, 0, 2017 0, 0,
1801 PS1_7_FN1, PS1_7_FN3,
1802 PS1_6_FN1, PS1_6_FN3,
1803 0, 0,
1804 0, 0,
1805 0, 0, 2018 0, 0,
1806 0, 0, 2019 0, 0,
2020 PS1_2_FN1, PS1_2_FN2,
1807 0, 0, 2021 0, 0,
1808 0, 0, } 2022 0, 0, }
1809 }, 2023 },
1810 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) { 2024 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
1811 0, 0, 2025 0, 0,
1812 0, 0, 2026 0, 0,
1813 PS2_13_FN3, PS2_13_FN1, 2027 PS2_13_FN1, PS2_13_FN2,
1814 PS2_12_FN3, PS2_12_FN1, 2028 PS2_12_FN1, PS2_12_FN2,
1815 0, 0, 2029 0, 0,
1816 0, 0, 2030 0, 0,
1817 0, 0, 2031 0, 0,
1818 0, 0, 2032 0, 0,
2033 PS2_7_FN1, PS2_7_FN2,
2034 PS2_6_FN1, PS2_6_FN2,
2035 PS2_5_FN1, PS2_5_FN2,
2036 PS2_4_FN1, PS2_4_FN2,
1819 0, 0, 2037 0, 0,
2038 PS2_2_FN1, PS2_2_FN2,
1820 0, 0, 2039 0, 0,
2040 0, 0, }
2041 },
2042 { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) {
2043 PS3_15_FN1, PS3_15_FN2,
2044 PS3_14_FN1, PS3_14_FN2,
2045 PS3_13_FN1, PS3_13_FN2,
2046 PS3_12_FN1, PS3_12_FN2,
2047 PS3_11_FN1, PS3_11_FN2,
2048 PS3_10_FN1, PS3_10_FN2,
2049 PS3_9_FN1, PS3_9_FN2,
2050 PS3_8_FN1, PS3_8_FN2,
2051 PS3_7_FN1, PS3_7_FN2,
1821 0, 0, 2052 0, 0,
1822 0, 0, 2053 0, 0,
1823 0, 0, 2054 0, 0,
1824 0, 0, 2055 0, 0,
1825 PS2_1_FN1, PS2_1_FN2, 2056 PS3_2_FN1, PS3_2_FN2,
1826 PS2_0_FN1, PS2_0_FN2, } 2057 PS3_1_FN1, PS3_1_FN2,
2058 0, 0, }
1827 }, 2059 },
2060
1828 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) { 2061 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
1829 PS4_15_FN2, PS4_15_FN1,
1830 PS4_14_FN2, PS4_14_FN1,
1831 PS4_13_FN2, PS4_13_FN1,
1832 PS4_12_FN2, PS4_12_FN1,
1833 PS4_11_FN2, PS4_11_FN1,
1834 PS4_10_FN2, PS4_10_FN1,
1835 PS4_9_FN2, PS4_9_FN1,
1836 0, 0, 2062 0, 0,
2063 PS4_14_FN1, PS4_14_FN2,
2064 PS4_13_FN1, PS4_13_FN2,
2065 PS4_12_FN1, PS4_12_FN2,
1837 0, 0, 2066 0, 0,
2067 PS4_10_FN1, PS4_10_FN2,
2068 PS4_9_FN1, PS4_9_FN2,
2069 PS4_8_FN1, PS4_8_FN2,
1838 0, 0, 2070 0, 0,
1839 0, 0, 2071 0, 0,
1840 0, 0, 2072 0, 0,
1841 PS4_3_FN2, PS4_3_FN1, 2073 PS4_4_FN1, PS4_4_FN2,
1842 PS4_2_FN2, PS4_2_FN1, 2074 PS4_3_FN1, PS4_3_FN2,
1843 PS4_1_FN2, PS4_1_FN1, 2075 PS4_2_FN1, PS4_2_FN2,
1844 PS4_0_FN2, PS4_0_FN1, } 2076 PS4_1_FN1, PS4_1_FN2,
2077 PS4_0_FN1, PS4_0_FN2, }
1845 }, 2078 },
1846 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) { 2079 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
1847 0, 0, 2080 0, 0,
1848 0, 0, 2081 0, 0,
1849 0, 0, 2082 0, 0,
1850 0, 0, 2083 0, 0,
1851 0, 0, 2084 PS5_11_FN1, PS5_11_FN2,
1852 0, 0, 2085 PS5_10_FN1, PS5_10_FN2,
1853 PS5_9_FN1, PS5_9_FN2, 2086 PS5_9_FN1, PS5_9_FN2,
1854 PS5_8_FN1, PS5_8_FN2, 2087 PS5_8_FN1, PS5_8_FN2,
1855 PS5_7_FN1, PS5_7_FN2, 2088 PS5_7_FN1, PS5_7_FN2,
1856 PS5_6_FN1, PS5_6_FN2, 2089 PS5_6_FN1, PS5_6_FN2,
1857 PS5_5_FN1, PS5_5_FN2, 2090 PS5_5_FN1, PS5_5_FN2,
2091 PS5_4_FN1, PS5_4_FN2,
2092 PS5_3_FN1, PS5_3_FN2,
2093 PS5_2_FN1, PS5_2_FN2,
2094 0, 0,
2095 0, 0, }
2096 },
2097 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
2098 PS6_15_FN1, PS6_15_FN2,
2099 PS6_14_FN1, PS6_14_FN2,
2100 PS6_13_FN1, PS6_13_FN2,
2101 PS6_12_FN1, PS6_12_FN2,
2102 PS6_11_FN1, PS6_11_FN2,
2103 PS6_10_FN1, PS6_10_FN2,
2104 PS6_9_FN1, PS6_9_FN2,
2105 PS6_8_FN1, PS6_8_FN2,
2106 PS6_7_FN1, PS6_7_FN2,
2107 PS6_6_FN1, PS6_6_FN2,
2108 PS6_5_FN1, PS6_5_FN2,
2109 PS6_4_FN1, PS6_4_FN2,
2110 PS6_3_FN1, PS6_3_FN2,
2111 PS6_2_FN1, PS6_2_FN2,
2112 PS6_1_FN1, PS6_1_FN2,
2113 PS6_0_FN1, PS6_0_FN2, }
2114 },
2115 { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) {
2116 PS7_15_FN1, PS7_15_FN2,
2117 PS7_14_FN1, PS7_14_FN2,
2118 PS7_13_FN1, PS7_13_FN2,
2119 PS7_12_FN1, PS7_12_FN2,
2120 PS7_11_FN1, PS7_11_FN2,
2121 PS7_10_FN1, PS7_10_FN2,
2122 PS7_9_FN1, PS7_9_FN2,
2123 PS7_8_FN1, PS7_8_FN2,
2124 PS7_7_FN1, PS7_7_FN2,
2125 PS7_6_FN1, PS7_6_FN2,
2126 PS7_5_FN1, PS7_5_FN2,
1858 0, 0, 2127 0, 0,
1859 0, 0, 2128 0, 0,
1860 0, 0, 2129 0, 0,
1861 0, 0, 2130 0, 0,
1862 0, 0, } 2131 0, 0, }
1863 }, 2132 },
1864 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { 2133 { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) {
2134 PS8_15_FN1, PS8_15_FN2,
2135 PS8_14_FN1, PS8_14_FN2,
2136 PS8_13_FN1, PS8_13_FN2,
2137 PS8_12_FN1, PS8_12_FN2,
2138 PS8_11_FN1, PS8_11_FN2,
2139 PS8_10_FN1, PS8_10_FN2,
2140 PS8_9_FN1, PS8_9_FN2,
2141 PS8_8_FN1, PS8_8_FN2,
1865 0, 0, 2142 0, 0,
1866 0, 0, 2143 0, 0,
1867 0, 0, 2144 0, 0,
@@ -1869,15 +2146,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1869 0, 0, 2146 0, 0,
1870 0, 0, 2147 0, 0,
1871 0, 0, 2148 0, 0,
1872 0, 0, 2149 0, 0, }
1873 PS6_7_FN_AN, PS6_7_FN_EV,
1874 PS6_6_FN_AN, PS6_6_FN_EV,
1875 PS6_5_FN_AN, PS6_5_FN_EV,
1876 PS6_4_FN_AN, PS6_4_FN_EV,
1877 PS6_3_FN_AN, PS6_3_FN_EV,
1878 PS6_2_FN_AN, PS6_2_FN_EV,
1879 PS6_1_FN_AN, PS6_1_FN_EV,
1880 PS6_0_FN_AN, PS6_0_FN_EV, }
1881 }, 2150 },
1882 {} 2151 {}
1883}; 2152};
@@ -1920,7 +2189,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1920 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA } 2189 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
1921 }, 2190 },
1922 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) { 2191 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
1923 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, 2192 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
1924 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } 2193 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
1925 }, 2194 },
1926 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) { 2195 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
@@ -1928,15 +2197,15 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1928 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 2197 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1929 }, 2198 },
1930 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) { 2199 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
1931 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 2200 0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1932 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } 2201 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
1933 }, 2202 },
1934 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) { 2203 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
1935 0, PTM6_DATA, PTM5_DATA, PTM4_DATA, 2204 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1936 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 2205 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1937 }, 2206 },
1938 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) { 2207 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
1939 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 2208 0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1940 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } 2209 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
1941 }, 2210 },
1942 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) { 2211 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
@@ -1944,7 +2213,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1944 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA } 2213 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
1945 }, 2214 },
1946 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) { 2215 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
1947 0, PTP6_DATA, PTP5_DATA, PTP4_DATA, 2216 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
1948 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } 2217 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
1949 }, 2218 },
1950 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) { 2219 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
@@ -1960,7 +2229,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1960 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 2229 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1961 }, 2230 },
1962 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) { 2231 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
1963 0, 0, PTT5_DATA, PTT4_DATA, 2232 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
1964 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 2233 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1965 }, 2234 },
1966 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) { 2235 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
@@ -2000,8 +2269,8 @@ static struct pinmux_info sh7757_pinmux_info = {
2000 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, 2269 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2001 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2270 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2002 2271
2003 .first_gpio = GPIO_PTA7, 2272 .first_gpio = GPIO_PTA0,
2004 .last_gpio = GPIO_FN_D0, 2273 .last_gpio = GPIO_FN_ON_DQ0,
2005 2274
2006 .gpios = pinmux_gpios, 2275 .gpios = pinmux_gpios,
2007 .cfg_regs = pinmux_config_regs, 2276 .cfg_regs = pinmux_config_regs,
@@ -2015,5 +2284,4 @@ static int __init plat_pinmux_setup(void)
2015{ 2284{
2016 return register_pinmux(&sh7757_pinmux_info); 2285 return register_pinmux(&sh7757_pinmux_info);
2017} 2286}
2018
2019arch_initcall(plat_pinmux_setup); 2287arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
new file mode 100644
index 000000000000..aaa5338abbff
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -0,0 +1,587 @@
1/*
2 * SH-X3 prototype CPU pinmux
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <cpu/shx3.h>
14
15enum {
16 PINMUX_RESERVED = 0,
17
18 PINMUX_DATA_BEGIN,
19 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
20 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
21 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
22 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
23 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
24 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
25 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
26 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
27 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
28 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
29 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
30 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
31 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
32 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
33
34 PH5_DATA, PH4_DATA,
35 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
36 PINMUX_DATA_END,
37
38 PINMUX_INPUT_BEGIN,
39 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
40 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
41 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
42 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
43 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
44 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
45 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
46 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
47 PE7_IN, PE6_IN, PE5_IN, PE4_IN,
48 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
49 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
50 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
51 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
52 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
53
54 PH5_IN, PH4_IN,
55 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
56 PINMUX_INPUT_END,
57
58 PINMUX_INPUT_PULLUP_BEGIN,
59 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
60 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
61 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
62 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
63 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
64 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
65 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
66 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
67 PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
68 PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
69 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
70 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
71 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
72 PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
73
74 PH5_IN_PU, PH4_IN_PU,
75 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
76 PINMUX_INPUT_PULLUP_END,
77
78 PINMUX_OUTPUT_BEGIN,
79 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
80 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
81 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
82 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
83 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
84 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
85 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
86 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
87 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
88 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
89 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
90 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
91 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
92 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
93
94 PH5_OUT, PH4_OUT,
95 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96 PINMUX_OUTPUT_END,
97
98 PINMUX_FUNCTION_BEGIN,
99 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
100 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
101 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
102 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
103 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
104 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
105 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
106 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
107 PE7_FN, PE6_FN, PE5_FN, PE4_FN,
108 PE3_FN, PE2_FN, PE1_FN, PE0_FN,
109 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
110 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
111 PG7_FN, PG6_FN, PG5_FN, PG4_FN,
112 PG3_FN, PG2_FN, PG1_FN, PG0_FN,
113
114 PH5_FN, PH4_FN,
115 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
116 PINMUX_FUNCTION_END,
117
118 PINMUX_MARK_BEGIN,
119
120 D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
121 D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
122 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
123
124 BACK_MARK, BREQ_MARK,
125 WE3_MARK, WE2_MARK,
126 CS6_MARK, CS5_MARK, CS4_MARK,
127 CLKOUTENB_MARK,
128
129 DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
130 DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
131
132 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
133
134 DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
135
136 SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
137 IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
138 TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
139 RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
140
141 CE2B_MARK, CE2A_MARK, IOIS16_MARK,
142 STATUS1_MARK, STATUS0_MARK,
143
144 IRQOUT_MARK,
145
146 PINMUX_MARK_END,
147};
148
149static pinmux_enum_t shx3_pinmux_data[] = {
150
151 /* PA GPIO */
152 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
153 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
154 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
155 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
156 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
157 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
158 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
159 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
160
161 /* PB GPIO */
162 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
163 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
164 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
165 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
166 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
167 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
168 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
169 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
170
171 /* PC GPIO */
172 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
173 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
174 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
175 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
176 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
177 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
178 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
179 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
180
181 /* PD GPIO */
182 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
183 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
184 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
185 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
186 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
187 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
188 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
189 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
190
191 /* PE GPIO */
192 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
193 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
194 PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
195 PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
196 PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
197 PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
198 PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
199 PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
200
201 /* PF GPIO */
202 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
203 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
204 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
205 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
206 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
207 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
208 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
209 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
210
211 /* PG GPIO */
212 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
213 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
214 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
215 PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
216 PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
217 PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
218 PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
219 PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
220
221 /* PH GPIO */
222 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
223 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
224 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
225 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
226 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
227 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
228
229 /* PA FN */
230 PINMUX_DATA(D31_MARK, PA7_FN),
231 PINMUX_DATA(D30_MARK, PA6_FN),
232 PINMUX_DATA(D29_MARK, PA5_FN),
233 PINMUX_DATA(D28_MARK, PA4_FN),
234 PINMUX_DATA(D27_MARK, PA3_FN),
235 PINMUX_DATA(D26_MARK, PA2_FN),
236 PINMUX_DATA(D25_MARK, PA1_FN),
237 PINMUX_DATA(D24_MARK, PA0_FN),
238
239 /* PB FN */
240 PINMUX_DATA(D23_MARK, PB7_FN),
241 PINMUX_DATA(D22_MARK, PB6_FN),
242 PINMUX_DATA(D21_MARK, PB5_FN),
243 PINMUX_DATA(D20_MARK, PB4_FN),
244 PINMUX_DATA(D19_MARK, PB3_FN),
245 PINMUX_DATA(D18_MARK, PB2_FN),
246 PINMUX_DATA(D17_MARK, PB1_FN),
247 PINMUX_DATA(D16_MARK, PB0_FN),
248
249 /* PC FN */
250 PINMUX_DATA(BACK_MARK, PC7_FN),
251 PINMUX_DATA(BREQ_MARK, PC6_FN),
252 PINMUX_DATA(WE3_MARK, PC5_FN),
253 PINMUX_DATA(WE2_MARK, PC4_FN),
254 PINMUX_DATA(CS6_MARK, PC3_FN),
255 PINMUX_DATA(CS5_MARK, PC2_FN),
256 PINMUX_DATA(CS4_MARK, PC1_FN),
257 PINMUX_DATA(CLKOUTENB_MARK, PC0_FN),
258
259 /* PD FN */
260 PINMUX_DATA(DACK3_MARK, PD7_FN),
261 PINMUX_DATA(DACK2_MARK, PD6_FN),
262 PINMUX_DATA(DACK1_MARK, PD5_FN),
263 PINMUX_DATA(DACK0_MARK, PD4_FN),
264 PINMUX_DATA(DREQ3_MARK, PD3_FN),
265 PINMUX_DATA(DREQ2_MARK, PD2_FN),
266 PINMUX_DATA(DREQ1_MARK, PD1_FN),
267 PINMUX_DATA(DREQ0_MARK, PD0_FN),
268
269 /* PE FN */
270 PINMUX_DATA(IRQ3_MARK, PE7_FN),
271 PINMUX_DATA(IRQ2_MARK, PE6_FN),
272 PINMUX_DATA(IRQ1_MARK, PE5_FN),
273 PINMUX_DATA(IRQ0_MARK, PE4_FN),
274 PINMUX_DATA(DRAK3_MARK, PE3_FN),
275 PINMUX_DATA(DRAK2_MARK, PE2_FN),
276 PINMUX_DATA(DRAK1_MARK, PE1_FN),
277 PINMUX_DATA(DRAK0_MARK, PE0_FN),
278
279 /* PF FN */
280 PINMUX_DATA(SCK3_MARK, PF7_FN),
281 PINMUX_DATA(SCK2_MARK, PF6_FN),
282 PINMUX_DATA(SCK1_MARK, PF5_FN),
283 PINMUX_DATA(SCK0_MARK, PF4_FN),
284 PINMUX_DATA(IRL3_MARK, PF3_FN),
285 PINMUX_DATA(IRL2_MARK, PF2_FN),
286 PINMUX_DATA(IRL1_MARK, PF1_FN),
287 PINMUX_DATA(IRL0_MARK, PF0_FN),
288
289 /* PG FN */
290 PINMUX_DATA(TXD3_MARK, PG7_FN),
291 PINMUX_DATA(TXD2_MARK, PG6_FN),
292 PINMUX_DATA(TXD1_MARK, PG5_FN),
293 PINMUX_DATA(TXD0_MARK, PG4_FN),
294 PINMUX_DATA(RXD3_MARK, PG3_FN),
295 PINMUX_DATA(RXD2_MARK, PG2_FN),
296 PINMUX_DATA(RXD1_MARK, PG1_FN),
297 PINMUX_DATA(RXD0_MARK, PG0_FN),
298
299 /* PH FN */
300 PINMUX_DATA(CE2B_MARK, PH5_FN),
301 PINMUX_DATA(CE2A_MARK, PH4_FN),
302 PINMUX_DATA(IOIS16_MARK, PH3_FN),
303 PINMUX_DATA(STATUS1_MARK, PH2_FN),
304 PINMUX_DATA(STATUS0_MARK, PH1_FN),
305 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
306};
307
308static struct pinmux_gpio shx3_pinmux_gpios[] = {
309 /* PA */
310 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
311 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
312 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
313 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
314 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
315 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
316 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
317 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
318
319 /* PB */
320 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
321 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
322 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
323 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
324 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
325 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
326 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
327 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
328
329 /* PC */
330 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
331 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
332 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
333 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
334 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
335 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
336 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
337 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
338
339 /* PD */
340 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
341 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
342 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
343 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
344 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
345 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
346 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
347 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
348
349 /* PE */
350 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
351 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
352 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
353 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
354 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
355 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
356 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
357 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
358
359 /* PF */
360 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
361 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
362 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
363 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
364 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
365 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
366 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
367 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
368
369 /* PG */
370 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
371 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
372 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
373 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
374 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
375 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
376 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
377 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
378
379 /* PH */
380 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
381 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
382 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
383 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
384 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
385 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
386
387 /* FN */
388 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
389 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
390 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
391 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
392 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
393 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
394 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
395 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
396 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
397 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
398 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
399 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
400 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
401 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
402 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
403 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
404 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
405 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
406 PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK),
407 PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK),
408 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
409 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
410 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
411 PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK),
412 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
413 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
414 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
415 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
416 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
417 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
418 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
419 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
420 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
421 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
422 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
423 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
424 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
425 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
426 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
427 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
428 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
429 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
430 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
431 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
432 PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK),
433 PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK),
434 PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK),
435 PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK),
436 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
437 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
438 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
439 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
440 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
441 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
442 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
443 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
444 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
445 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
446 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
447 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
448 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
449 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
450};
451
452static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
453 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
454 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
455 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
456 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
457 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
458 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
459 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
460 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
461 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
462 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
463 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
464 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
465 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
466 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
467 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
468 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
469 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
470 },
471 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
472 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
473 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
474 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
475 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
476 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
477 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
478 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
479 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
480 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
481 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
482 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
483 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
484 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
485 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
486 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
487 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
488 },
489 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
490 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
491 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
492 PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
493 PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
494 PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
495 PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
496 PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
497 PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
498 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
499 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
500 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
501 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
502 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
503 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
504 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
505 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
506 },
507 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
508 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
509 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
510 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
511 PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
512 PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
513 PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
514 PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
515 PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
516 0, 0, 0, 0,
517 0, 0, 0, 0,
518 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
519 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
520 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
521 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
522 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
523 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
524 },
525 { },
526};
527
528static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
529 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
530 0, 0, 0, 0, 0, 0, 0, 0,
531 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
532 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
533 0, 0, 0, 0, 0, 0, 0, 0,
534 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
535 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
536 },
537 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
538 0, 0, 0, 0, 0, 0, 0, 0,
539 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
540 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
541 0, 0, 0, 0, 0, 0, 0, 0,
542 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
543 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
544 },
545 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
546 0, 0, 0, 0, 0, 0, 0, 0,
547 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
548 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
549 0, 0, 0, 0, 0, 0, 0, 0,
550 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
551 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
552 },
553 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
554 0, 0, 0, 0, 0, 0, 0, 0,
555 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
556 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
557 0, 0, 0, 0, 0, 0, 0, 0,
558 0, 0, PH5_DATA, PH4_DATA,
559 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
560 },
561 { },
562};
563
564static struct pinmux_info shx3_pinmux_info = {
565 .name = "shx3_pfc",
566 .reserved_id = PINMUX_RESERVED,
567 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
568 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
569 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
570 PINMUX_INPUT_PULLUP_END },
571 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
572 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
573 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
574 .first_gpio = GPIO_PA7,
575 .last_gpio = GPIO_FN_IRQOUT,
576 .gpios = shx3_pinmux_gpios,
577 .gpio_data = shx3_pinmux_data,
578 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
579 .cfg_regs = shx3_pinmux_config_regs,
580 .data_regs = shx3_pinmux_data_regs,
581};
582
583static int __init shx3_pinmux_setup(void)
584{
585 return register_pinmux(&shx3_pinmux_info);
586}
587arch_initcall(shx3_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 156ccc960015..d551ed8dea95 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -551,7 +551,7 @@ static struct resource siu_resources[] = {
551}; 551};
552 552
553static struct platform_device siu_device = { 553static struct platform_device siu_device = {
554 .name = "sh_siu", 554 .name = "siu-pcm-audio",
555 .id = -1, 555 .id = -1,
556 .dev = { 556 .dev = {
557 .platform_data = &siu_platform_data, 557 .platform_data = &siu_platform_data,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 79c556e56262..828c9657eb52 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -524,6 +524,70 @@ static struct platform_device veu1_device = {
524 }, 524 },
525}; 525};
526 526
527/* BEU0 */
528static struct uio_info beu0_platform_data = {
529 .name = "BEU0",
530 .version = "0",
531 .irq = evt2irq(0x8A0),
532};
533
534static struct resource beu0_resources[] = {
535 [0] = {
536 .name = "BEU0",
537 .start = 0xfe930000,
538 .end = 0xfe933400,
539 .flags = IORESOURCE_MEM,
540 },
541 [1] = {
542 /* place holder for contiguous memory */
543 },
544};
545
546static struct platform_device beu0_device = {
547 .name = "uio_pdrv_genirq",
548 .id = 6,
549 .dev = {
550 .platform_data = &beu0_platform_data,
551 },
552 .resource = beu0_resources,
553 .num_resources = ARRAY_SIZE(beu0_resources),
554 .archdata = {
555 .hwblk_id = HWBLK_BEU0,
556 },
557};
558
559/* BEU1 */
560static struct uio_info beu1_platform_data = {
561 .name = "BEU1",
562 .version = "0",
563 .irq = evt2irq(0xA00),
564};
565
566static struct resource beu1_resources[] = {
567 [0] = {
568 .name = "BEU1",
569 .start = 0xfe940000,
570 .end = 0xfe943400,
571 .flags = IORESOURCE_MEM,
572 },
573 [1] = {
574 /* place holder for contiguous memory */
575 },
576};
577
578static struct platform_device beu1_device = {
579 .name = "uio_pdrv_genirq",
580 .id = 7,
581 .dev = {
582 .platform_data = &beu1_platform_data,
583 },
584 .resource = beu1_resources,
585 .num_resources = ARRAY_SIZE(beu1_resources),
586 .archdata = {
587 .hwblk_id = HWBLK_BEU1,
588 },
589};
590
527static struct sh_timer_config cmt_platform_data = { 591static struct sh_timer_config cmt_platform_data = {
528 .channel_offset = 0x60, 592 .channel_offset = 0x60,
529 .timer_bit = 5, 593 .timer_bit = 5,
@@ -857,6 +921,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
857 &vpu_device, 921 &vpu_device,
858 &veu0_device, 922 &veu0_device,
859 &veu1_device, 923 &veu1_device,
924 &beu0_device,
925 &beu1_device,
860 &jpu_device, 926 &jpu_device,
861 &spu0_device, 927 &spu0_device,
862 &spu1_device, 928 &spu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 444aca95b20d..749c6388d5a5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -26,7 +26,7 @@ static struct plat_sci_port scif2_platform_data = {
26 26
27static struct platform_device scif2_device = { 27static struct platform_device scif2_device = {
28 .name = "sh-sci", 28 .name = "sh-sci",
29 .id = 2, 29 .id = 0,
30 .dev = { 30 .dev = {
31 .platform_data = &scif2_platform_data, 31 .platform_data = &scif2_platform_data,
32 }, 32 },
@@ -41,7 +41,7 @@ static struct plat_sci_port scif3_platform_data = {
41 41
42static struct platform_device scif3_device = { 42static struct platform_device scif3_device = {
43 .name = "sh-sci", 43 .name = "sh-sci",
44 .id = 3, 44 .id = 1,
45 .dev = { 45 .dev = {
46 .platform_data = &scif3_platform_data, 46 .platform_data = &scif3_platform_data,
47 }, 47 },
@@ -56,7 +56,7 @@ static struct plat_sci_port scif4_platform_data = {
56 56
57static struct platform_device scif4_device = { 57static struct platform_device scif4_device = {
58 .name = "sh-sci", 58 .name = "sh-sci",
59 .id = 4, 59 .id = 2,
60 .dev = { 60 .dev = {
61 .platform_data = &scif4_platform_data, 61 .platform_data = &scif4_platform_data,
62 }, 62 },
@@ -163,39 +163,23 @@ enum {
163 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 163 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
164 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 164 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
165 165
166 SDHI, 166 SDHI, DVC,
167 DVC, 167 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
168 IRQ8, IRQ9, IRQ10, 168 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
169 WDT0,
170 TMU0, TMU1, TMU2, TMU2_TICPI,
171 HUDI, 169 HUDI,
172
173 ARC4, 170 ARC4,
174 DMAC0, 171 DMAC0_5, DMAC6_7, DMAC8_11,
175 IRQ11, 172 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
176 SCIF2, 173 USB0, USB1,
177 DMAC1_6,
178 USB0,
179 IRQ12,
180 JMC, 174 JMC,
181 SPI1, 175 SPI0, SPI1,
182 IRQ13, IRQ14,
183 USB1,
184 TMR01, TMR23, TMR45, 176 TMR01, TMR23, TMR45,
185 WDT1,
186 FRT, 177 FRT,
187 LPC, 178 LPC, LPC5, LPC6, LPC7, LPC8,
188 SCIF0, SCIF1, SCIF3, 179 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
189 PECI0I, PECI1I, PECI2I,
190 IRQ15,
191 ETHERC, 180 ETHERC,
192 SPI0, 181 ADC0, ADC1,
193 ADC1,
194 DMAC1_8,
195 SIM, 182 SIM,
196 TMU3, TMU4, TMU5,
197 ADC0,
198 SCIF4,
199 IIC0_0, IIC0_1, IIC0_2, IIC0_3, 183 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
200 IIC1_0, IIC1_1, IIC1_2, IIC1_3, 184 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
201 IIC2_0, IIC2_1, IIC2_2, IIC2_3, 185 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
@@ -206,9 +190,23 @@ enum {
206 IIC7_0, IIC7_1, IIC7_2, IIC7_3, 190 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
207 IIC8_0, IIC8_1, IIC8_2, IIC8_3, 191 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
208 IIC9_0, IIC9_1, IIC9_2, IIC9_3, 192 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
209 PCIINTA, 193 ONFICTL,
210 PCIE, 194 MMC1, MMC2,
195 ECCU,
196 PCIC,
197 G200,
198 RSPI,
211 SGPIO, 199 SGPIO,
200 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
201 DMINT20, DMINT21, DMINT22, DMINT23,
202 DDRECC,
203 TSIP,
204 PCIE_BRIDGE,
205 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
206 GETHER0, GETHER1, GETHER2,
207 PBIA, PBIB, PBIC,
208 DMAE2, DMAE3,
209 SERMUX2, SERMUX3,
212 210
213 /* interrupt groups */ 211 /* interrupt groups */
214 212
@@ -221,19 +219,18 @@ static struct intc_vect vectors[] __initdata = {
221 INTC_VECT(DVC, 0x4e0), 219 INTC_VECT(DVC, 0x4e0),
222 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), 220 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
223 INTC_VECT(IRQ10, 0x540), 221 INTC_VECT(IRQ10, 0x540),
224 INTC_VECT(WDT0, 0x560),
225 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 222 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
226 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 223 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
227 INTC_VECT(HUDI, 0x600), 224 INTC_VECT(HUDI, 0x600),
228 INTC_VECT(ARC4, 0x620), 225 INTC_VECT(ARC4, 0x620),
229 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), 226 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
230 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), 227 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
231 INTC_VECT(DMAC0, 0x6c0), 228 INTC_VECT(DMAC0_5, 0x6c0),
232 INTC_VECT(IRQ11, 0x6e0), 229 INTC_VECT(IRQ11, 0x6e0),
233 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), 230 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
234 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), 231 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
235 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), 232 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
236 INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0), 233 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
237 INTC_VECT(USB0, 0x840), 234 INTC_VECT(USB0, 0x840),
238 INTC_VECT(IRQ12, 0x880), 235 INTC_VECT(IRQ12, 0x880),
239 INTC_VECT(JMC, 0x8a0), 236 INTC_VECT(JMC, 0x8a0),
@@ -242,7 +239,6 @@ static struct intc_vect vectors[] __initdata = {
242 INTC_VECT(USB1, 0x920), 239 INTC_VECT(USB1, 0x920),
243 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), 240 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
244 INTC_VECT(TMR45, 0xa40), 241 INTC_VECT(TMR45, 0xa40),
245 INTC_VECT(WDT1, 0xa60),
246 INTC_VECT(FRT, 0xa80), 242 INTC_VECT(FRT, 0xa80),
247 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), 243 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
248 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), 244 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
@@ -250,14 +246,14 @@ static struct intc_vect vectors[] __initdata = {
250 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), 246 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
251 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), 247 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
252 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), 248 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
253 INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20), 249 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
254 INTC_VECT(PECI2I, 0xc40), 250 INTC_VECT(PECI2, 0xc40),
255 INTC_VECT(IRQ15, 0xc60), 251 INTC_VECT(IRQ15, 0xc60),
256 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), 252 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
257 INTC_VECT(SPI0, 0xcc0), 253 INTC_VECT(SPI0, 0xcc0),
258 INTC_VECT(ADC1, 0xce0), 254 INTC_VECT(ADC1, 0xce0),
259 INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20), 255 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
260 INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60), 256 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
261 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), 257 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
262 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), 258 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
263 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 259 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
@@ -278,17 +274,47 @@ static struct intc_vect vectors[] __initdata = {
278 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), 274 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
279 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), 275 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
280 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), 276 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
281 INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980), 277 INTC_VECT(IIC6_2, 0x1920),
278 INTC_VECT(ONFICTL, 0x1960),
279 INTC_VECT(IIC6_3, 0x1980),
282 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), 280 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
283 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), 281 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
284 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), 282 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
285 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), 283 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
286 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), 284 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
287 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), 285 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
288 INTC_VECT(PCIINTA, 0x1ce0), 286 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
289 INTC_VECT(PCIE, 0x1e00), 287 INTC_VECT(ECCU, 0x1cc0),
290 INTC_VECT(SGPIO, 0x1f80), 288 INTC_VECT(PCIC, 0x1ce0),
291 INTC_VECT(SGPIO, 0x1fa0), 289 INTC_VECT(G200, 0x1d00),
290 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
291 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
292 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
293 INTC_VECT(PECI5, 0x1f00),
294 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
295 INTC_VECT(SGPIO, 0x1fc0),
296 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
297 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
298 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
299 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
300 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
301 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
302 INTC_VECT(DDRECC, 0x2620),
303 INTC_VECT(TSIP, 0x2640),
304 INTC_VECT(PCIE_BRIDGE, 0x27c0),
305 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
306 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
307 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
308 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
309 INTC_VECT(WDT8B, 0x2900),
310 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
311 INTC_VECT(GETHER2, 0x29a0),
312 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
313 INTC_VECT(PBIC, 0x2a40),
314 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
315 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
316 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
317 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
292}; 318};
293 319
294static struct intc_group groups[] __initdata = { 320static struct intc_group groups[] __initdata = {
@@ -312,31 +338,45 @@ static struct intc_mask_reg mask_registers[] __initdata = {
312 338
313 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ 339 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
314 { 0, 0, 0, 0, 0, 0, 0, 0, 340 { 0, 0, 0, 0, 0, 0, 0, 0,
315 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45, 341 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
316 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0, 342 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
317 HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012 343 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
318 } }, 344 } },
319 345
320 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ 346 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
321 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, 347 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
322 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, 348 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
323 ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I, 349 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
324 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC 350 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
325 } }, 351 } },
326 352
327 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ 353 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
328 { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0, 354 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
329 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, 355 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
330 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, 356 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
331 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2 357 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
332 } }, 358 } },
333 359
334 { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */ 360 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
335 { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0, 361 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
336 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, 362 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
337 PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3, 363 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
338 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 364 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
339 } }, 365 } },
366
367 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
368 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
369 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
370 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
371 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
372 } },
373
374 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
375 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
376 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
377 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
378 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
379 } },
340}; 380};
341 381
342#define INTPRI 0xffd00010 382#define INTPRI 0xffd00010
@@ -372,6 +412,22 @@ static struct intc_mask_reg mask_registers[] __initdata = {
372#define INT2PRI29 0xffd100b4 412#define INT2PRI29 0xffd100b4
373#define INT2PRI30 0xffd100b8 413#define INT2PRI30 0xffd100b8
374#define INT2PRI31 0xffd100bc 414#define INT2PRI31 0xffd100bc
415#define INT2PRI32 0xffd20000
416#define INT2PRI33 0xffd20004
417#define INT2PRI34 0xffd20008
418#define INT2PRI35 0xffd2000c
419#define INT2PRI36 0xffd20010
420#define INT2PRI37 0xffd20014
421#define INT2PRI38 0xffd20018
422#define INT2PRI39 0xffd2001c
423#define INT2PRI40 0xffd200a0
424#define INT2PRI41 0xffd200a4
425#define INT2PRI42 0xffd200a8
426#define INT2PRI43 0xffd200ac
427#define INT2PRI44 0xffd200b0
428#define INT2PRI45 0xffd200b4
429#define INT2PRI46 0xffd200b8
430#define INT2PRI47 0xffd200bc
375 431
376static struct intc_prio_reg prio_registers[] __initdata = { 432static struct intc_prio_reg prio_registers[] __initdata = {
377 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, 433 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
@@ -379,39 +435,61 @@ static struct intc_prio_reg prio_registers[] __initdata = {
379 435
380 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, 436 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
381 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, 437 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
382 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } }, 438 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
383 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } }, 439 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
384 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, 440 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
385 { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } }, 441 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
386 { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } }, 442 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
387 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, 443 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
388 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, 444 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
389 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, 445 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
390 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } }, 446 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
391 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } }, 447 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
392 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, 448 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
393 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, 449 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
394 450
395 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, 451 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
396 { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } }, 452 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
397 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, 453 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
398 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, 454 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
399 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, 455 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
400 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, 456 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
401 { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } }, 457 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
402 { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } }, 458 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
403 { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } }, 459 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
404 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, 460 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
405 { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } }, 461 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
406 { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } }, 462 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
407 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } }, 463 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
408 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, 464 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
409 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } }, 465 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
410 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, 466 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
467 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
468 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
469 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
470 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
471 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
472 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
473 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
474 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
475 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
476 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
477 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
478 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
479 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
480 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
481 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
482 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
483};
484
485static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
486 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
487 IRQ11, IRQ10, IRQ9, IRQ8 } },
411}; 488};
412 489
413static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, 490static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
414 mask_registers, prio_registers, NULL); 491 mask_registers, prio_registers,
492 sense_registers_irq8to15);
415 493
416/* Support for external interrupt pins in IRQ mode */ 494/* Support for external interrupt pins in IRQ mode */
417static struct intc_vect vectors_irq0123[] __initdata = { 495static struct intc_vect vectors_irq0123[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 8797723231ea..c016c0004714 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -629,33 +629,10 @@ static void __init sh7786_usb_setup(void)
629 } 629 }
630} 630}
631 631
632static int __init sh7786_devices_setup(void)
633{
634 int ret;
635
636 sh7786_usb_setup();
637
638 ret = platform_add_devices(sh7786_early_devices,
639 ARRAY_SIZE(sh7786_early_devices));
640 if (unlikely(ret != 0))
641 return ret;
642
643 return platform_add_devices(sh7786_devices,
644 ARRAY_SIZE(sh7786_devices));
645}
646arch_initcall(sh7786_devices_setup);
647
648void __init plat_early_device_setup(void)
649{
650 early_platform_add_devices(sh7786_early_devices,
651 ARRAY_SIZE(sh7786_early_devices));
652}
653
654enum { 632enum {
655 UNUSED = 0, 633 UNUSED = 0,
656 634
657 /* interrupt sources */ 635 /* interrupt sources */
658
659 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 636 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
660 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 637 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
661 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 638 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
@@ -693,9 +670,12 @@ enum {
693 Thermal, 670 Thermal,
694 INTICI0, INTICI1, INTICI2, INTICI3, 671 INTICI0, INTICI1, INTICI2, INTICI3,
695 INTICI4, INTICI5, INTICI6, INTICI7, 672 INTICI4, INTICI5, INTICI6, INTICI7,
673
674 /* Muxed sub-events */
675 TXI1, BRI1, RXI1, ERI1,
696}; 676};
697 677
698static struct intc_vect vectors[] __initdata = { 678static struct intc_vect sh7786_vectors[] __initdata = {
699 INTC_VECT(WDT, 0x3e0), 679 INTC_VECT(WDT, 0x3e0),
700 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420), 680 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
701 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460), 681 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
@@ -756,14 +736,12 @@ static struct intc_vect vectors[] __initdata = {
756 736
757#define INTDISTCR0 0xfe4100b0 737#define INTDISTCR0 0xfe4100b0
758#define INTDISTCR1 0xfe4100b4 738#define INTDISTCR1 0xfe4100b4
759#define INTACK 0xfe4100b8
760#define INTACKCLR 0xfe4100bc
761#define INT2DISTCR0 0xfe410900 739#define INT2DISTCR0 0xfe410900
762#define INT2DISTCR1 0xfe410904 740#define INT2DISTCR1 0xfe410904
763#define INT2DISTCR2 0xfe410908 741#define INT2DISTCR2 0xfe410908
764#define INT2DISTCR3 0xfe41090c 742#define INT2DISTCR3 0xfe41090c
765 743
766static struct intc_mask_reg mask_registers[] __initdata = { 744static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
767 { CnINTMSK0, CnINTMSKCLR0, 32, 745 { CnINTMSK0, CnINTMSKCLR0, 32,
768 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 }, 746 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
769 INTC_SMP_BALANCING(INTDISTCR0) }, 747 INTC_SMP_BALANCING(INTDISTCR0) },
@@ -807,7 +785,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
807 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) }, 785 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
808}; 786};
809 787
810static struct intc_prio_reg prio_registers[] __initdata = { 788static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
811 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 789 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
812 IRQ4, IRQ5, IRQ6, IRQ7 } }, 790 IRQ4, IRQ5, IRQ6, IRQ7 } },
813 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } }, 791 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
@@ -851,11 +829,27 @@ static struct intc_prio_reg prio_registers[] __initdata = {
851 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, 829 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
852}; 830};
853 831
854static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, 832static struct intc_subgroup sh7786_subgroups[] __initdata = {
855 mask_registers, prio_registers, NULL); 833 { 0xfe410c20, 32, SCIF1,
834 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
835 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
836};
856 837
857/* Support for external interrupt pins in IRQ mode */ 838static struct intc_desc sh7786_intc_desc __initdata = {
839 .name = "sh7786",
840 .hw = {
841 .vectors = sh7786_vectors,
842 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
843 .mask_regs = sh7786_mask_registers,
844 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
845 .subgroups = sh7786_subgroups,
846 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
847 .prio_regs = sh7786_prio_registers,
848 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
849 },
850};
858 851
852/* Support for external interrupt pins in IRQ mode */
859static struct intc_vect vectors_irq0123[] __initdata = { 853static struct intc_vect vectors_irq0123[] __initdata = {
860 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 854 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
861 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 855 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
@@ -866,23 +860,25 @@ static struct intc_vect vectors_irq4567[] __initdata = {
866 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 860 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
867}; 861};
868 862
869static struct intc_sense_reg sense_registers[] __initdata = { 863static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
870 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 864 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
871 IRQ4, IRQ5, IRQ6, IRQ7 } }, 865 IRQ4, IRQ5, IRQ6, IRQ7 } },
872}; 866};
873 867
874static struct intc_mask_reg ack_registers[] __initdata = { 868static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
875 { 0xfe410024, 0, 32, /* INTREQ */ 869 { 0xfe410024, 0, 32, /* INTREQ */
876 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 870 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
877}; 871};
878 872
879static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123", 873static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
880 vectors_irq0123, NULL, mask_registers, 874 vectors_irq0123, NULL, sh7786_mask_registers,
881 prio_registers, sense_registers, ack_registers); 875 sh7786_prio_registers, sh7786_sense_registers,
876 sh7786_ack_registers);
882 877
883static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567", 878static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
884 vectors_irq4567, NULL, mask_registers, 879 vectors_irq4567, NULL, sh7786_mask_registers,
885 prio_registers, sense_registers, ack_registers); 880 sh7786_prio_registers, sh7786_sense_registers,
881 sh7786_ack_registers);
886 882
887/* External interrupt pins in IRL mode */ 883/* External interrupt pins in IRL mode */
888 884
@@ -909,10 +905,10 @@ static struct intc_vect vectors_irl4567[] __initdata = {
909}; 905};
910 906
911static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123, 907static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
912 NULL, mask_registers, NULL, NULL); 908 NULL, sh7786_mask_registers, NULL, NULL);
913 909
914static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, 910static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
915 NULL, mask_registers, NULL, NULL); 911 NULL, sh7786_mask_registers, NULL, NULL);
916 912
917#define INTC_ICR0 0xfe410000 913#define INTC_ICR0 0xfe410000
918#define INTC_INTMSK0 CnINTMSK0 914#define INTC_INTMSK0 CnINTMSK0
@@ -920,19 +916,6 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
920#define INTC_INTMSK2 INTMSK2 916#define INTC_INTMSK2 INTMSK2
921#define INTC_INTMSKCLR1 CnINTMSKCLR1 917#define INTC_INTMSKCLR1 CnINTMSKCLR1
922#define INTC_INTMSKCLR2 INTMSKCLR2 918#define INTC_INTMSKCLR2 INTMSKCLR2
923#define INTC_USERIMASK 0xfe411000
924
925#ifdef CONFIG_INTC_BALANCING
926unsigned int irq_lookup(unsigned int irq)
927{
928 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
929}
930
931void irq_finish(unsigned int irq)
932{
933 __raw_writel(irq2evt(irq), INTACKCLR);
934}
935#endif
936 919
937void __init plat_irq_setup(void) 920void __init plat_irq_setup(void)
938{ 921{
@@ -946,8 +929,7 @@ void __init plat_irq_setup(void)
946 /* select IRL mode for IRL3-0 + IRL7-4 */ 929 /* select IRL mode for IRL3-0 + IRL7-4 */
947 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 930 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
948 931
949 register_intc_controller(&intc_desc); 932 register_intc_controller(&sh7786_intc_desc);
950 register_intc_userimask(INTC_USERIMASK);
951} 933}
952 934
953void __init plat_irq_setup_pins(int mode) 935void __init plat_irq_setup_pins(int mode)
@@ -991,3 +973,39 @@ void __init plat_irq_setup_pins(int mode)
991void __init plat_mem_setup(void) 973void __init plat_mem_setup(void)
992{ 974{
993} 975}
976
977static int __init sh7786_devices_setup(void)
978{
979 int ret, irq;
980
981 sh7786_usb_setup();
982
983 /*
984 * De-mux SCIF1 IRQs if possible
985 */
986 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
987 if (irq > 0) {
988 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
989 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
990 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
991 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
992 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
993 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
994 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
995 }
996
997 ret = platform_add_devices(sh7786_early_devices,
998 ARRAY_SIZE(sh7786_early_devices));
999 if (unlikely(ret != 0))
1000 return ret;
1001
1002 return platform_add_devices(sh7786_devices,
1003 ARRAY_SIZE(sh7786_devices));
1004}
1005arch_initcall(sh7786_devices_setup);
1006
1007void __init plat_early_device_setup(void)
1008{
1009 early_platform_add_devices(sh7786_early_devices,
1010 ARRAY_SIZE(sh7786_early_devices));
1011}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 9158bc5ea38b..013f0b144489 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 Prototype Setup 2 * SH-X3 Prototype Setup
3 * 3 *
4 * Copyright (C) 2007 - 2009 Paul Mundt 4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,9 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/gpio.h>
15#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <cpu/shx3.h>
16#include <asm/mmzone.h> 18#include <asm/mmzone.h>
17 19
18/* 20/*
@@ -354,6 +356,10 @@ static struct intc_group groups[] __initdata = {
354 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), 356 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
355}; 357};
356 358
359#define INT2DISTCR0 0xfe4108a0
360#define INT2DISTCR1 0xfe4108a4
361#define INT2DISTCR2 0xfe4108a8
362
357static struct intc_mask_reg mask_registers[] __initdata = { 363static struct intc_mask_reg mask_registers[] __initdata = {
358 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ 364 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
359 { IRQ0, IRQ1, IRQ2, IRQ3 } }, 365 { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -363,20 +369,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
363 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, 369 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
364 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, 370 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
365 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ 371 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
366 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } }, 372 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
373 INTC_SMP_BALANCING(INT2DISTCR0) },
367 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ 374 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
368 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ 375 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
369 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, 376 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
370 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, 377 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
371 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, 378 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
372 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, 379 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
373 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } }, 380 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
381 INTC_SMP_BALANCING(INT2DISTCR1) },
374 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ 382 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
375 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 383 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
376 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, 384 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
377 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, 385 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
378 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, 386 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
379 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, 387 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
388 INTC_SMP_BALANCING(INT2DISTCR2) },
380}; 389};
381 390
382static struct intc_prio_reg prio_registers[] __initdata = { 391static struct intc_prio_reg prio_registers[] __initdata = {
@@ -433,11 +442,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
433 442
434void __init plat_irq_setup_pins(int mode) 443void __init plat_irq_setup_pins(int mode)
435{ 444{
445 int ret = 0;
446
436 switch (mode) { 447 switch (mode) {
437 case IRQ_MODE_IRQ: 448 case IRQ_MODE_IRQ:
449 ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
450 ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
451 ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
452 ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
453
454 if (unlikely(ret)) {
455 pr_err("Failed to set IRQ mode\n");
456 return;
457 }
458
438 register_intc_controller(&intc_desc_irq); 459 register_intc_controller(&intc_desc_irq);
439 break; 460 break;
440 case IRQ_MODE_IRL3210: 461 case IRQ_MODE_IRL3210:
462 ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
463 ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
464 ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
465 ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
466
467 if (unlikely(ret)) {
468 pr_err("Failed to set IRL mode\n");
469 return;
470 }
471
441 register_intc_controller(&intc_desc_irl); 472 register_intc_controller(&intc_desc_irl);
442 break; 473 break;
443 default: 474 default:
@@ -447,6 +478,9 @@ void __init plat_irq_setup_pins(int mode)
447 478
448void __init plat_irq_setup(void) 479void __init plat_irq_setup(void)
449{ 480{
481 reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
482 reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
483
450 register_intc_controller(&intc_desc); 484 register_intc_controller(&intc_desc);
451} 485}
452 486
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 23:04:09 -0500