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-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c490
1 files changed, 490 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
new file mode 100644
index 000000000000..5a47e1cf442e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -0,0 +1,490 @@
1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 Setup
8 *
9 * Copyright (C) 2007 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/serial_sci.h>
19#include <linux/io.h>
20#include <linux/mm.h>
21#include <linux/dma-mapping.h>
22#include <asm/mmzone.h>
23
24static struct plat_sci_port sci_platform_data[] = {
25 {
26 .mapbase = 0xffea0000,
27 .flags = UPF_BOOT_AUTOCONF,
28 .type = PORT_SCIF,
29 .irqs = { 40, 41, 43, 42 },
30 },
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffeb0000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 44, 44, 44, 44 },
39 }, {
40 .mapbase = 0xffec0000,
41 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF,
43 .irqs = { 50, 50, 50, 50 },
44 }, {
45 .mapbase = 0xffed0000,
46 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF,
48 .irqs = { 51, 51, 51, 51 },
49 }, {
50 .mapbase = 0xffee0000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF,
53 .irqs = { 52, 52, 52, 52 },
54 }, {
55 .mapbase = 0xffef0000,
56 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF,
58 .irqs = { 53, 53, 53, 53 },
59 }, {
60 .flags = 0,
61 }
62};
63
64static struct platform_device sci_device = {
65 .name = "sh-sci",
66 .id = -1,
67 .dev = {
68 .platform_data = sci_platform_data,
69 },
70};
71
72static struct resource usb_ohci_resources[] = {
73 [0] = {
74 .start = 0xffe70400,
75 .end = 0xffe704ff,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = 77,
80 .end = 77,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
86static struct platform_device usb_ohci_device = {
87 .name = "sh_ohci",
88 .id = -1,
89 .dev = {
90 .dma_mask = &usb_ohci_dma_mask,
91 .coherent_dma_mask = DMA_BIT_MASK(32),
92 },
93 .num_resources = ARRAY_SIZE(usb_ohci_resources),
94 .resource = usb_ohci_resources,
95};
96
97static struct platform_device *sh7786_devices[] __initdata = {
98 &sci_device,
99 &usb_ohci_device,
100};
101
102
103/*
104 * Please call this function if your platform board
105 * use external clock for USB
106 * */
107#define USBCTL0 0xffe70858
108#define CLOCK_MODE_MASK 0xffffff7f
109#define EXT_CLOCK_MODE 0x00000080
110void __init sh7786_usb_use_exclock(void)
111{
112 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
113 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
114}
115
116#define USBINITREG1 0xffe70094
117#define USBINITREG2 0xffe7009c
118#define USBINITVAL1 0x00ff0040
119#define USBINITVAL2 0x00000001
120
121#define USBPCTL1 0xffe70804
122#define USBST 0xffe70808
123#define PHY_ENB 0x00000001
124#define PLL_ENB 0x00000002
125#define PHY_RST 0x00000004
126#define ACT_PLL_STATUS 0xc0000000
127static void __init sh7786_usb_setup(void)
128{
129 int i = 1000000;
130
131 /*
132 * USB initial settings
133 *
134 * The following settings are necessary
135 * for using the USB modules.
136 *
137 * see "USB Inital Settings" for detail
138 */
139 __raw_writel(USBINITVAL1, USBINITREG1);
140 __raw_writel(USBINITVAL2, USBINITREG2);
141
142 /*
143 * Set the PHY and PLL enable bit
144 */
145 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
146 while (i-- &&
147 ((__raw_readl(USBST) & ACT_PLL_STATUS) != ACT_PLL_STATUS))
148 cpu_relax();
149
150 if (i) {
151 /* Set the PHY RST bit */
152 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
153 printk(KERN_INFO "sh7786 usb setup done\n");
154 }
155}
156
157static int __init sh7786_devices_setup(void)
158{
159 sh7786_usb_setup();
160 return platform_add_devices(sh7786_devices,
161 ARRAY_SIZE(sh7786_devices));
162}
163device_initcall(sh7786_devices_setup);
164
165enum {
166 UNUSED = 0,
167
168 /* interrupt sources */
169
170 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
171 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
172 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
173 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
174
175 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
176 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
177 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
178 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
179
180 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
181 WDT,
182 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
183 TMU1_0, TMU1_1, TMU1_2,
184 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
185 HUDI1, HUDI0,
186 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
187 HPB_0, HPB_1, HPB_2,
188 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
189 SCIF1,
190 TMU2, TMU3,
191 SCIF2, SCIF3, SCIF4, SCIF5,
192 Eth_0, Eth_1,
193 PCIeC0_0, PCIeC0_1, PCIeC0_2,
194 PCIeC1_0, PCIeC1_1, PCIeC1_2,
195 USB,
196 I2C0, I2C1,
197 DU,
198 SSI0, SSI1, SSI2, SSI3,
199 PCIeC2_0, PCIeC2_1, PCIeC2_2,
200 HAC0, HAC1,
201 FLCTL,
202 HSPI,
203 GPIO0, GPIO1,
204 Thermal,
205 INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
206
207 /* interrupt groups */
208};
209
210static struct intc_vect vectors[] __initdata = {
211 INTC_VECT(WDT, 0x3e0),
212 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
213 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
214 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
215 INTC_VECT(TMU1_2, 0x4c0),
216 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
217 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
218 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
219 INTC_VECT(DMAC0_6, 0x5c0),
220 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
221 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
222 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
223 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
224 INTC_VECT(HPB_2, 0x6e0),
225 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
226 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
227 INTC_VECT(SCIF1, 0x780),
228 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
229 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
230 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
231 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
232 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
233 INTC_VECT(PCIeC0_2, 0xb20),
234 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
235 INTC_VECT(PCIeC1_2, 0xb80),
236 INTC_VECT(USB, 0xba0),
237 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
238 INTC_VECT(DU, 0xd00),
239 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
240 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
241 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
242 INTC_VECT(PCIeC2_2, 0xde0),
243 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
244 INTC_VECT(FLCTL, 0xe40),
245 INTC_VECT(HSPI, 0xe80),
246 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
247 INTC_VECT(Thermal, 0xee0),
248};
249
250/* FIXME: Main CPU support only now */
251#if 1 /* Main CPU */
252#define CnINTMSK0 0xfe410030
253#define CnINTMSK1 0xfe410040
254#define CnINTMSKCLR0 0xfe410050
255#define CnINTMSKCLR1 0xfe410060
256#define CnINT2MSKR0 0xfe410a20
257#define CnINT2MSKR1 0xfe410a24
258#define CnINT2MSKR2 0xfe410a28
259#define CnINT2MSKR3 0xfe410a2c
260#define CnINT2MSKCR0 0xfe410a30
261#define CnINT2MSKCR1 0xfe410a34
262#define CnINT2MSKCR2 0xfe410a38
263#define CnINT2MSKCR3 0xfe410a3c
264#else /* Sub CPU */
265#define CnINTMSK0 0xfe410034
266#define CnINTMSK1 0xfe410044
267#define CnINTMSKCLR0 0xfe410054
268#define CnINTMSKCLR1 0xfe410064
269#define CnINT2MSKR0 0xfe410b20
270#define CnINT2MSKR1 0xfe410b24
271#define CnINT2MSKR2 0xfe410b28
272#define CnINT2MSKR3 0xfe410b2c
273#define CnINT2MSKCR0 0xfe410b30
274#define CnINT2MSKCR1 0xfe410b34
275#define CnINT2MSKCR2 0xfe410b38
276#define CnINT2MSKCR3 0xfe410b3c
277#endif
278
279#define INTMSK2 0xfe410068
280#define INTMSKCLR2 0xfe41006c
281
282static struct intc_mask_reg mask_registers[] __initdata = {
283 { CnINTMSK0, CnINTMSKCLR0, 32,
284 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
285 { INTMSK2, INTMSKCLR2, 32,
286 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
287 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
288 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
289 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
290 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
291 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
292 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
293 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
294 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
295 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
297 { CnINT2MSKR1, CnINT2MSKCR1, 32,
298 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
299 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
300 HUDI1, HUDI0,
301 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
302 HPB_0, HPB_1, HPB_2,
303 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
304 SCIF1,
305 TMU2, TMU3, 0, } },
306 { CnINT2MSKR2, CnINT2MSKCR2, 32,
307 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
308 Eth_0, Eth_1,
309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
310 PCIeC0_0, PCIeC0_1, PCIeC0_2,
311 PCIeC1_0, PCIeC1_1, PCIeC1_2,
312 USB, 0, 0 } },
313 { CnINT2MSKR3, CnINT2MSKCR3, 32,
314 { 0, 0, 0, 0, 0, 0,
315 I2C0, I2C1,
316 DU, SSI0, SSI1, SSI2, SSI3,
317 PCIeC2_0, PCIeC2_1, PCIeC2_2,
318 HAC0, HAC1,
319 FLCTL, 0,
320 HSPI, GPIO0, GPIO1, Thermal,
321 0, 0, 0, 0, 0, 0, 0, 0 } },
322};
323
324static struct intc_prio_reg prio_registers[] __initdata = {
325 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
326 IRQ4, IRQ5, IRQ6, IRQ7 } },
327 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
328 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
329 TMU0_2, TMU0_3 } },
330 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
331 TMU1_2, 0 } },
332 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
333 DMAC0_2, DMAC0_3 } },
334 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
335 DMAC0_6, HUDI1 } },
336 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
337 DMAC1_1, DMAC1_2 } },
338 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
339 HPB_1, HPB_2 } },
340 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
341 SCIF0_2, SCIF0_3 } },
342 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
343 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
344 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
345 Eth_0, Eth_1 } },
346 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
347 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
348 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
349 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
350 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
351 PCIeC1_0, PCIeC1_1 } },
352 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
353 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
354 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
355 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
356 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
357 PCIeC2_1, PCIeC2_2 } },
358 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
359 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
360 GPIO1, Thermal } },
361 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
362 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
363};
364
365static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
366 mask_registers, prio_registers, NULL);
367
368/* Support for external interrupt pins in IRQ mode */
369
370static struct intc_vect vectors_irq0123[] __initdata = {
371 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
372 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
373};
374
375static struct intc_vect vectors_irq4567[] __initdata = {
376 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
377 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
378};
379
380static struct intc_sense_reg sense_registers[] __initdata = {
381 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
382 IRQ4, IRQ5, IRQ6, IRQ7 } },
383};
384
385static struct intc_mask_reg ack_registers[] __initdata = {
386 { 0xfe410024, 0, 32, /* INTREQ */
387 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
388};
389
390static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
391 vectors_irq0123, NULL, mask_registers,
392 prio_registers, sense_registers, ack_registers);
393
394static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
395 vectors_irq4567, NULL, mask_registers,
396 prio_registers, sense_registers, ack_registers);
397
398/* External interrupt pins in IRL mode */
399
400static struct intc_vect vectors_irl0123[] __initdata = {
401 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
402 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
403 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
404 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
405 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
406 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
407 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
408 INTC_VECT(IRL0_HHHL, 0x3c0),
409};
410
411static struct intc_vect vectors_irl4567[] __initdata = {
412 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
413 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
414 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
415 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
416 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
417 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
418 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
419 INTC_VECT(IRL4_HHHL, 0xac0),
420};
421
422static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
423 NULL, mask_registers, NULL, NULL);
424
425static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
426 NULL, mask_registers, NULL, NULL);
427
428#define INTC_ICR0 0xfe410000
429#define INTC_INTMSK0 CnINTMSK0
430#define INTC_INTMSK1 CnINTMSK1
431#define INTC_INTMSK2 INTMSK2
432#define INTC_INTMSKCLR1 CnINTMSKCLR1
433#define INTC_INTMSKCLR2 INTMSKCLR2
434
435void __init plat_irq_setup(void)
436{
437 /* disable IRQ3-0 + IRQ7-4 */
438 ctrl_outl(0xff000000, INTC_INTMSK0);
439
440 /* disable IRL3-0 + IRL7-4 */
441 ctrl_outl(0xc0000000, INTC_INTMSK1);
442 ctrl_outl(0xfffefffe, INTC_INTMSK2);
443
444 /* select IRL mode for IRL3-0 + IRL7-4 */
445 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
446
447 register_intc_controller(&intc_desc);
448}
449
450void __init plat_irq_setup_pins(int mode)
451{
452 switch (mode) {
453 case IRQ_MODE_IRQ7654:
454 /* select IRQ mode for IRL7-4 */
455 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
456 register_intc_controller(&intc_desc_irq4567);
457 break;
458 case IRQ_MODE_IRQ3210:
459 /* select IRQ mode for IRL3-0 */
460 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
461 register_intc_controller(&intc_desc_irq0123);
462 break;
463 case IRQ_MODE_IRL7654:
464 /* enable IRL7-4 but don't provide any masking */
465 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
466 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
467 break;
468 case IRQ_MODE_IRL3210:
469 /* enable IRL0-3 but don't provide any masking */
470 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
471 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
472 break;
473 case IRQ_MODE_IRL7654_MASK:
474 /* enable IRL7-4 and mask using cpu intc controller */
475 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
476 register_intc_controller(&intc_desc_irl4567);
477 break;
478 case IRQ_MODE_IRL3210_MASK:
479 /* enable IRL0-3 and mask using cpu intc controller */
480 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
481 register_intc_controller(&intc_desc_irl0123);
482 break;
483 default:
484 BUG();
485 }
486}
487
488void __init plat_mem_setup(void)
489{
490}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 08:29:40 -0500