diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7785.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 30 |
1 files changed, 3 insertions, 27 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 1fcd88b1671e..f3e3ea0ce050 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
25 | .flags = UPF_BOOT_AUTOCONF, | 25 | .flags = UPF_BOOT_AUTOCONF, |
26 | .type = PORT_SCIF, | 26 | .type = PORT_SCIF, |
27 | .irqs = { 40, 40, 40, 40 }, | 27 | .irqs = { 40, 40, 40, 40 }, |
28 | .clk = "scif_fck", | ||
29 | }; | 28 | }; |
30 | 29 | ||
31 | static struct platform_device scif0_device = { | 30 | static struct platform_device scif0_device = { |
@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
41 | .flags = UPF_BOOT_AUTOCONF, | 40 | .flags = UPF_BOOT_AUTOCONF, |
42 | .type = PORT_SCIF, | 41 | .type = PORT_SCIF, |
43 | .irqs = { 44, 44, 44, 44 }, | 42 | .irqs = { 44, 44, 44, 44 }, |
44 | .clk = "scif_fck", | ||
45 | }; | 43 | }; |
46 | 44 | ||
47 | static struct platform_device scif1_device = { | 45 | static struct platform_device scif1_device = { |
@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
57 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
58 | .type = PORT_SCIF, | 56 | .type = PORT_SCIF, |
59 | .irqs = { 60, 60, 60, 60 }, | 57 | .irqs = { 60, 60, 60, 60 }, |
60 | .clk = "scif_fck", | ||
61 | }; | 58 | }; |
62 | 59 | ||
63 | static struct platform_device scif2_device = { | 60 | static struct platform_device scif2_device = { |
@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = { | |||
73 | .flags = UPF_BOOT_AUTOCONF, | 70 | .flags = UPF_BOOT_AUTOCONF, |
74 | .type = PORT_SCIF, | 71 | .type = PORT_SCIF, |
75 | .irqs = { 61, 61, 61, 61 }, | 72 | .irqs = { 61, 61, 61, 61 }, |
76 | .clk = "scif_fck", | ||
77 | }; | 73 | }; |
78 | 74 | ||
79 | static struct platform_device scif3_device = { | 75 | static struct platform_device scif3_device = { |
@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = { | |||
89 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
90 | .type = PORT_SCIF, | 86 | .type = PORT_SCIF, |
91 | .irqs = { 62, 62, 62, 62 }, | 87 | .irqs = { 62, 62, 62, 62 }, |
92 | .clk = "scif_fck", | ||
93 | }; | 88 | }; |
94 | 89 | ||
95 | static struct platform_device scif4_device = { | 90 | static struct platform_device scif4_device = { |
@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = { | |||
105 | .flags = UPF_BOOT_AUTOCONF, | 100 | .flags = UPF_BOOT_AUTOCONF, |
106 | .type = PORT_SCIF, | 101 | .type = PORT_SCIF, |
107 | .irqs = { 63, 63, 63, 63 }, | 102 | .irqs = { 63, 63, 63, 63 }, |
108 | .clk = "scif_fck", | ||
109 | }; | 103 | }; |
110 | 104 | ||
111 | static struct platform_device scif5_device = { | 105 | static struct platform_device scif5_device = { |
@@ -117,16 +111,13 @@ static struct platform_device scif5_device = { | |||
117 | }; | 111 | }; |
118 | 112 | ||
119 | static struct sh_timer_config tmu0_platform_data = { | 113 | static struct sh_timer_config tmu0_platform_data = { |
120 | .name = "TMU0", | ||
121 | .channel_offset = 0x04, | 114 | .channel_offset = 0x04, |
122 | .timer_bit = 0, | 115 | .timer_bit = 0, |
123 | .clk = "tmu012_fck", | ||
124 | .clockevent_rating = 200, | 116 | .clockevent_rating = 200, |
125 | }; | 117 | }; |
126 | 118 | ||
127 | static struct resource tmu0_resources[] = { | 119 | static struct resource tmu0_resources[] = { |
128 | [0] = { | 120 | [0] = { |
129 | .name = "TMU0", | ||
130 | .start = 0xffd80008, | 121 | .start = 0xffd80008, |
131 | .end = 0xffd80013, | 122 | .end = 0xffd80013, |
132 | .flags = IORESOURCE_MEM, | 123 | .flags = IORESOURCE_MEM, |
@@ -148,16 +139,13 @@ static struct platform_device tmu0_device = { | |||
148 | }; | 139 | }; |
149 | 140 | ||
150 | static struct sh_timer_config tmu1_platform_data = { | 141 | static struct sh_timer_config tmu1_platform_data = { |
151 | .name = "TMU1", | ||
152 | .channel_offset = 0x10, | 142 | .channel_offset = 0x10, |
153 | .timer_bit = 1, | 143 | .timer_bit = 1, |
154 | .clk = "tmu012_fck", | ||
155 | .clocksource_rating = 200, | 144 | .clocksource_rating = 200, |
156 | }; | 145 | }; |
157 | 146 | ||
158 | static struct resource tmu1_resources[] = { | 147 | static struct resource tmu1_resources[] = { |
159 | [0] = { | 148 | [0] = { |
160 | .name = "TMU1", | ||
161 | .start = 0xffd80014, | 149 | .start = 0xffd80014, |
162 | .end = 0xffd8001f, | 150 | .end = 0xffd8001f, |
163 | .flags = IORESOURCE_MEM, | 151 | .flags = IORESOURCE_MEM, |
@@ -179,15 +167,12 @@ static struct platform_device tmu1_device = { | |||
179 | }; | 167 | }; |
180 | 168 | ||
181 | static struct sh_timer_config tmu2_platform_data = { | 169 | static struct sh_timer_config tmu2_platform_data = { |
182 | .name = "TMU2", | ||
183 | .channel_offset = 0x1c, | 170 | .channel_offset = 0x1c, |
184 | .timer_bit = 2, | 171 | .timer_bit = 2, |
185 | .clk = "tmu012_fck", | ||
186 | }; | 172 | }; |
187 | 173 | ||
188 | static struct resource tmu2_resources[] = { | 174 | static struct resource tmu2_resources[] = { |
189 | [0] = { | 175 | [0] = { |
190 | .name = "TMU2", | ||
191 | .start = 0xffd80020, | 176 | .start = 0xffd80020, |
192 | .end = 0xffd8002f, | 177 | .end = 0xffd8002f, |
193 | .flags = IORESOURCE_MEM, | 178 | .flags = IORESOURCE_MEM, |
@@ -209,15 +194,12 @@ static struct platform_device tmu2_device = { | |||
209 | }; | 194 | }; |
210 | 195 | ||
211 | static struct sh_timer_config tmu3_platform_data = { | 196 | static struct sh_timer_config tmu3_platform_data = { |
212 | .name = "TMU3", | ||
213 | .channel_offset = 0x04, | 197 | .channel_offset = 0x04, |
214 | .timer_bit = 0, | 198 | .timer_bit = 0, |
215 | .clk = "tmu345_fck", | ||
216 | }; | 199 | }; |
217 | 200 | ||
218 | static struct resource tmu3_resources[] = { | 201 | static struct resource tmu3_resources[] = { |
219 | [0] = { | 202 | [0] = { |
220 | .name = "TMU3", | ||
221 | .start = 0xffdc0008, | 203 | .start = 0xffdc0008, |
222 | .end = 0xffdc0013, | 204 | .end = 0xffdc0013, |
223 | .flags = IORESOURCE_MEM, | 205 | .flags = IORESOURCE_MEM, |
@@ -239,15 +221,12 @@ static struct platform_device tmu3_device = { | |||
239 | }; | 221 | }; |
240 | 222 | ||
241 | static struct sh_timer_config tmu4_platform_data = { | 223 | static struct sh_timer_config tmu4_platform_data = { |
242 | .name = "TMU4", | ||
243 | .channel_offset = 0x10, | 224 | .channel_offset = 0x10, |
244 | .timer_bit = 1, | 225 | .timer_bit = 1, |
245 | .clk = "tmu345_fck", | ||
246 | }; | 226 | }; |
247 | 227 | ||
248 | static struct resource tmu4_resources[] = { | 228 | static struct resource tmu4_resources[] = { |
249 | [0] = { | 229 | [0] = { |
250 | .name = "TMU4", | ||
251 | .start = 0xffdc0014, | 230 | .start = 0xffdc0014, |
252 | .end = 0xffdc001f, | 231 | .end = 0xffdc001f, |
253 | .flags = IORESOURCE_MEM, | 232 | .flags = IORESOURCE_MEM, |
@@ -269,15 +248,12 @@ static struct platform_device tmu4_device = { | |||
269 | }; | 248 | }; |
270 | 249 | ||
271 | static struct sh_timer_config tmu5_platform_data = { | 250 | static struct sh_timer_config tmu5_platform_data = { |
272 | .name = "TMU5", | ||
273 | .channel_offset = 0x1c, | 251 | .channel_offset = 0x1c, |
274 | .timer_bit = 2, | 252 | .timer_bit = 2, |
275 | .clk = "tmu345_fck", | ||
276 | }; | 253 | }; |
277 | 254 | ||
278 | static struct resource tmu5_resources[] = { | 255 | static struct resource tmu5_resources[] = { |
279 | [0] = { | 256 | [0] = { |
280 | .name = "TMU5", | ||
281 | .start = 0xffdc0020, | 257 | .start = 0xffdc0020, |
282 | .end = 0xffdc002b, | 258 | .end = 0xffdc002b, |
283 | .flags = IORESOURCE_MEM, | 259 | .flags = IORESOURCE_MEM, |
@@ -299,7 +275,7 @@ static struct platform_device tmu5_device = { | |||
299 | }; | 275 | }; |
300 | 276 | ||
301 | /* DMA */ | 277 | /* DMA */ |
302 | static struct sh_dmae_channel sh7785_dmae0_channels[] = { | 278 | static const struct sh_dmae_channel sh7785_dmae0_channels[] = { |
303 | { | 279 | { |
304 | .offset = 0, | 280 | .offset = 0, |
305 | .dmars = 0, | 281 | .dmars = 0, |
@@ -327,7 +303,7 @@ static struct sh_dmae_channel sh7785_dmae0_channels[] = { | |||
327 | } | 303 | } |
328 | }; | 304 | }; |
329 | 305 | ||
330 | static struct sh_dmae_channel sh7785_dmae1_channels[] = { | 306 | static const struct sh_dmae_channel sh7785_dmae1_channels[] = { |
331 | { | 307 | { |
332 | .offset = 0, | 308 | .offset = 0, |
333 | }, { | 309 | }, { |
@@ -343,7 +319,7 @@ static struct sh_dmae_channel sh7785_dmae1_channels[] = { | |||
343 | } | 319 | } |
344 | }; | 320 | }; |
345 | 321 | ||
346 | static unsigned int ts_shift[] = TS_SHIFT; | 322 | static const unsigned int ts_shift[] = TS_SHIFT; |
347 | 323 | ||
348 | static struct sh_dmae_pdata dma0_platform_data = { | 324 | static struct sh_dmae_pdata dma0_platform_data = { |
349 | .channel = sh7785_dmae0_channels, | 325 | .channel = sh7785_dmae0_channels, |