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Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7785.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c95
1 files changed, 32 insertions, 63 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 30baa63b24c8..d80802a49dbd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,18 +20,13 @@ static struct plat_sci_port sci_platform_data[] = {
20 .mapbase = 0xffea0000, 20 .mapbase = 0xffea0000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 40, 41, 43, 42 }, 23 .irqs = { 40, 40, 40, 40 },
24 }, { 24 }, {
25 .mapbase = 0xffeb0000, 25 .mapbase = 0xffeb0000,
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 44, 45, 47, 46 }, 28 .irqs = { 44, 44, 44, 44 },
29 }, 29 }, {
30
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffec0000, 30 .mapbase = 0xffec0000,
36 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 32 .type = PORT_SCIF,
@@ -91,33 +86,19 @@ enum {
91 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 86 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
92 87
93 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 88 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
94 WDT, 89 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 90 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
96 HUDI,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
98 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
99 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
100 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
101 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
102 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
103 HSPI,
104 SCIF2, SCIF3, SCIF4, SCIF5, 91 SCIF2, SCIF3, SCIF4, SCIF5,
105 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, 92 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
106 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, 93 SIOF, MMCIF, DU, GDTA,
107 SIOF,
108 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
109 DU,
110 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
111 TMU3, TMU4, TMU5, 94 TMU3, TMU4, TMU5,
112 SSI0, SSI1, 95 SSI0, SSI1,
113 HAC0, HAC1, 96 HAC0, HAC1,
114 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1, 97 FLCTL, GPIO,
115 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
116 98
117 /* interrupt groups */ 99 /* interrupt groups */
118 100
119 TMU012, DMAC0, SCIF0, SCIF1, DMAC1, 101 TMU012, TMU345
120 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
121}; 102};
122 103
123static struct intc_vect vectors[] __initdata = { 104static struct intc_vect vectors[] __initdata = {
@@ -125,57 +106,45 @@ static struct intc_vect vectors[] __initdata = {
125 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 106 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
126 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 107 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
127 INTC_VECT(HUDI, 0x600), 108 INTC_VECT(HUDI, 0x600),
128 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640), 109 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
129 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680), 110 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
130 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0), 111 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
131 INTC_VECT(DMAC0_DMAE, 0x6e0), 112 INTC_VECT(DMAC0, 0x6e0),
132 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 113 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
133 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 114 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
134 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), 115 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
135 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), 116 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
136 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0), 117 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
137 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0), 118 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
138 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920), 119 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
139 INTC_VECT(DMAC1_DMAE, 0x940), 120 INTC_VECT(DMAC1, 0x940),
140 INTC_VECT(HSPI, 0x960), 121 INTC_VECT(HSPI, 0x960),
141 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0), 122 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
142 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0), 123 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
143 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 124 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
144 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 125 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
145 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 126 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
146 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 127 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
147 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 128 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
148 INTC_VECT(SIOF, 0xc00), 129 INTC_VECT(SIOF, 0xc00),
149 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 130 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
150 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 131 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
151 INTC_VECT(DU, 0xd80), 132 INTC_VECT(DU, 0xd80),
152 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0), 133 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
153 INTC_VECT(GDTA_GAERI, 0xde0), 134 INTC_VECT(GDTA, 0xde0),
154 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 135 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
155 INTC_VECT(TMU5, 0xe40), 136 INTC_VECT(TMU5, 0xe40),
156 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 137 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
157 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0), 138 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
158 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 139 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
159 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 140 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
160 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 141 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
161 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 142 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
162}; 143};
163 144
164static struct intc_group groups[] __initdata = { 145static struct intc_group groups[] __initdata = {
165 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 146 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
166 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
167 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
168 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
169 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
170 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
171 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
172 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
173 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
174 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
175 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 147 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
176 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
177 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
178 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
179}; 148};
180 149
181static struct intc_mask_reg mask_registers[] __initdata = { 150static struct intc_mask_reg mask_registers[] __initdata = {