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Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7780.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c231
1 files changed, 181 insertions, 50 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index bcd411eb9cb0..08add7fa6849 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -12,19 +12,53 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_dma.h>
15#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
16 17
18#include <cpu/dma-register.h>
19
20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF,
26 .irqs = { 40, 40, 40, 40 },
27};
28
29static struct platform_device scif0_device = {
30 .name = "sh-sci",
31 .id = 0,
32 .dev = {
33 .platform_data = &scif0_platform_data,
34 },
35};
36
37static struct plat_sci_port scif1_platform_data = {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_1,
42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 },
44};
45
46static struct platform_device scif1_device = {
47 .name = "sh-sci",
48 .id = 1,
49 .dev = {
50 .platform_data = &scif1_platform_data,
51 },
52};
53
17static struct sh_timer_config tmu0_platform_data = { 54static struct sh_timer_config tmu0_platform_data = {
18 .name = "TMU0",
19 .channel_offset = 0x04, 55 .channel_offset = 0x04,
20 .timer_bit = 0, 56 .timer_bit = 0,
21 .clk = "peripheral_clk",
22 .clockevent_rating = 200, 57 .clockevent_rating = 200,
23}; 58};
24 59
25static struct resource tmu0_resources[] = { 60static struct resource tmu0_resources[] = {
26 [0] = { 61 [0] = {
27 .name = "TMU0",
28 .start = 0xffd80008, 62 .start = 0xffd80008,
29 .end = 0xffd80013, 63 .end = 0xffd80013,
30 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
@@ -46,16 +80,13 @@ static struct platform_device tmu0_device = {
46}; 80};
47 81
48static struct sh_timer_config tmu1_platform_data = { 82static struct sh_timer_config tmu1_platform_data = {
49 .name = "TMU1",
50 .channel_offset = 0x10, 83 .channel_offset = 0x10,
51 .timer_bit = 1, 84 .timer_bit = 1,
52 .clk = "peripheral_clk",
53 .clocksource_rating = 200, 85 .clocksource_rating = 200,
54}; 86};
55 87
56static struct resource tmu1_resources[] = { 88static struct resource tmu1_resources[] = {
57 [0] = { 89 [0] = {
58 .name = "TMU1",
59 .start = 0xffd80014, 90 .start = 0xffd80014,
60 .end = 0xffd8001f, 91 .end = 0xffd8001f,
61 .flags = IORESOURCE_MEM, 92 .flags = IORESOURCE_MEM,
@@ -77,15 +108,12 @@ static struct platform_device tmu1_device = {
77}; 108};
78 109
79static struct sh_timer_config tmu2_platform_data = { 110static struct sh_timer_config tmu2_platform_data = {
80 .name = "TMU2",
81 .channel_offset = 0x1c, 111 .channel_offset = 0x1c,
82 .timer_bit = 2, 112 .timer_bit = 2,
83 .clk = "peripheral_clk",
84}; 113};
85 114
86static struct resource tmu2_resources[] = { 115static struct resource tmu2_resources[] = {
87 [0] = { 116 [0] = {
88 .name = "TMU2",
89 .start = 0xffd80020, 117 .start = 0xffd80020,
90 .end = 0xffd8002f, 118 .end = 0xffd8002f,
91 .flags = IORESOURCE_MEM, 119 .flags = IORESOURCE_MEM,
@@ -107,15 +135,12 @@ static struct platform_device tmu2_device = {
107}; 135};
108 136
109static struct sh_timer_config tmu3_platform_data = { 137static struct sh_timer_config tmu3_platform_data = {
110 .name = "TMU3",
111 .channel_offset = 0x04, 138 .channel_offset = 0x04,
112 .timer_bit = 0, 139 .timer_bit = 0,
113 .clk = "peripheral_clk",
114}; 140};
115 141
116static struct resource tmu3_resources[] = { 142static struct resource tmu3_resources[] = {
117 [0] = { 143 [0] = {
118 .name = "TMU3",
119 .start = 0xffdc0008, 144 .start = 0xffdc0008,
120 .end = 0xffdc0013, 145 .end = 0xffdc0013,
121 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
@@ -137,15 +162,12 @@ static struct platform_device tmu3_device = {
137}; 162};
138 163
139static struct sh_timer_config tmu4_platform_data = { 164static struct sh_timer_config tmu4_platform_data = {
140 .name = "TMU4",
141 .channel_offset = 0x10, 165 .channel_offset = 0x10,
142 .timer_bit = 1, 166 .timer_bit = 1,
143 .clk = "peripheral_clk",
144}; 167};
145 168
146static struct resource tmu4_resources[] = { 169static struct resource tmu4_resources[] = {
147 [0] = { 170 [0] = {
148 .name = "TMU4",
149 .start = 0xffdc0014, 171 .start = 0xffdc0014,
150 .end = 0xffdc001f, 172 .end = 0xffdc001f,
151 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
@@ -167,15 +189,12 @@ static struct platform_device tmu4_device = {
167}; 189};
168 190
169static struct sh_timer_config tmu5_platform_data = { 191static struct sh_timer_config tmu5_platform_data = {
170 .name = "TMU5",
171 .channel_offset = 0x1c, 192 .channel_offset = 0x1c,
172 .timer_bit = 2, 193 .timer_bit = 2,
173 .clk = "peripheral_clk",
174}; 194};
175 195
176static struct resource tmu5_resources[] = { 196static struct resource tmu5_resources[] = {
177 [0] = { 197 [0] = {
178 .name = "TMU5",
179 .start = 0xffdc0020, 198 .start = 0xffdc0020,
180 .end = 0xffdc002b, 199 .end = 0xffdc002b,
181 .flags = IORESOURCE_MEM, 200 .flags = IORESOURCE_MEM,
@@ -216,35 +235,137 @@ static struct platform_device rtc_device = {
216 .resource = rtc_resources, 235 .resource = rtc_resources,
217}; 236};
218 237
219static struct plat_sci_port sci_platform_data[] = { 238/* DMA */
239static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
220 { 240 {
221 .mapbase = 0xffe00000, 241 .offset = 0,
222 .flags = UPF_BOOT_AUTOCONF, 242 .dmars = 0,
223 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 243 .dmars_bit = 0,
224 .scbrr_algo_id = SCBRR_ALGO_1, 244 }, {
225 .type = PORT_SCIF, 245 .offset = 0x10,
226 .irqs = { 40, 40, 40, 40 }, 246 .dmars = 0,
247 .dmars_bit = 8,
248 }, {
249 .offset = 0x20,
250 .dmars = 4,
251 .dmars_bit = 0,
227 }, { 252 }, {
228 .mapbase = 0xffe10000, 253 .offset = 0x30,
229 .flags = UPF_BOOT_AUTOCONF, 254 .dmars = 4,
230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 255 .dmars_bit = 8,
231 .scbrr_algo_id = SCBRR_ALGO_1,
232 .type = PORT_SCIF,
233 .irqs = { 76, 76, 76, 76 },
234 }, { 256 }, {
235 .flags = 0, 257 .offset = 0x50,
258 .dmars = 8,
259 .dmars_bit = 0,
260 }, {
261 .offset = 0x60,
262 .dmars = 8,
263 .dmars_bit = 8,
236 } 264 }
237}; 265};
238 266
239static struct platform_device sci_device = { 267static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
240 .name = "sh-sci", 268 {
241 .id = -1, 269 .offset = 0,
270 }, {
271 .offset = 0x10,
272 }, {
273 .offset = 0x20,
274 }, {
275 .offset = 0x30,
276 }, {
277 .offset = 0x50,
278 }, {
279 .offset = 0x60,
280 }
281};
282
283static const unsigned int ts_shift[] = TS_SHIFT;
284
285static struct sh_dmae_pdata dma0_platform_data = {
286 .channel = sh7780_dmae0_channels,
287 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
288 .ts_low_shift = CHCR_TS_LOW_SHIFT,
289 .ts_low_mask = CHCR_TS_LOW_MASK,
290 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
291 .ts_high_mask = CHCR_TS_HIGH_MASK,
292 .ts_shift = ts_shift,
293 .ts_shift_num = ARRAY_SIZE(ts_shift),
294 .dmaor_init = DMAOR_INIT,
295};
296
297static struct sh_dmae_pdata dma1_platform_data = {
298 .channel = sh7780_dmae1_channels,
299 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
300 .ts_low_shift = CHCR_TS_LOW_SHIFT,
301 .ts_low_mask = CHCR_TS_LOW_MASK,
302 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
303 .ts_high_mask = CHCR_TS_HIGH_MASK,
304 .ts_shift = ts_shift,
305 .ts_shift_num = ARRAY_SIZE(ts_shift),
306 .dmaor_init = DMAOR_INIT,
307};
308
309static struct resource sh7780_dmae0_resources[] = {
310 [0] = {
311 /* Channel registers and DMAOR */
312 .start = 0xfc808020,
313 .end = 0xfc80808f,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 /* DMARSx */
318 .start = 0xfc809000,
319 .end = 0xfc80900b,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
324 .start = 34,
325 .end = 34,
326 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
327 },
328};
329
330static struct resource sh7780_dmae1_resources[] = {
331 [0] = {
332 /* Channel registers and DMAOR */
333 .start = 0xfc818020,
334 .end = 0xfc81808f,
335 .flags = IORESOURCE_MEM,
336 },
337 /* DMAC1 has no DMARS */
338 {
339 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
340 .start = 46,
341 .end = 46,
342 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
343 },
344};
345
346static struct platform_device dma0_device = {
347 .name = "sh-dma-engine",
348 .id = 0,
349 .resource = sh7780_dmae0_resources,
350 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
351 .dev = {
352 .platform_data = &dma0_platform_data,
353 },
354};
355
356static struct platform_device dma1_device = {
357 .name = "sh-dma-engine",
358 .id = 1,
359 .resource = sh7780_dmae1_resources,
360 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
242 .dev = { 361 .dev = {
243 .platform_data = sci_platform_data, 362 .platform_data = &dma1_platform_data,
244 }, 363 },
245}; 364};
246 365
247static struct platform_device *sh7780_devices[] __initdata = { 366static struct platform_device *sh7780_devices[] __initdata = {
367 &scif0_device,
368 &scif1_device,
248 &tmu0_device, 369 &tmu0_device,
249 &tmu1_device, 370 &tmu1_device,
250 &tmu2_device, 371 &tmu2_device,
@@ -252,7 +373,8 @@ static struct platform_device *sh7780_devices[] __initdata = {
252 &tmu4_device, 373 &tmu4_device,
253 &tmu5_device, 374 &tmu5_device,
254 &rtc_device, 375 &rtc_device,
255 &sci_device, 376 &dma0_device,
377 &dma1_device,
256}; 378};
257 379
258static int __init sh7780_devices_setup(void) 380static int __init sh7780_devices_setup(void)
@@ -260,9 +382,11 @@ static int __init sh7780_devices_setup(void)
260 return platform_add_devices(sh7780_devices, 382 return platform_add_devices(sh7780_devices,
261 ARRAY_SIZE(sh7780_devices)); 383 ARRAY_SIZE(sh7780_devices));
262} 384}
263__initcall(sh7780_devices_setup); 385arch_initcall(sh7780_devices_setup);
264 386
265static struct platform_device *sh7780_early_devices[] __initdata = { 387static struct platform_device *sh7780_early_devices[] __initdata = {
388 &scif0_device,
389 &scif1_device,
266 &tmu0_device, 390 &tmu0_device,
267 &tmu1_device, 391 &tmu1_device,
268 &tmu2_device, 392 &tmu2_device,
@@ -273,6 +397,13 @@ static struct platform_device *sh7780_early_devices[] __initdata = {
273 397
274void __init plat_early_device_setup(void) 398void __init plat_early_device_setup(void)
275{ 399{
400 if (mach_is_sh2007()) {
401 scif0_platform_data.scscr &= ~SCSCR_CKE1;
402 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
403 scif1_platform_data.scscr &= ~SCSCR_CKE1;
404 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
405 }
406
276 early_platform_add_devices(sh7780_early_devices, 407 early_platform_add_devices(sh7780_early_devices,
277 ARRAY_SIZE(sh7780_early_devices)); 408 ARRAY_SIZE(sh7780_early_devices));
278} 409}
@@ -443,17 +574,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
443void __init plat_irq_setup(void) 574void __init plat_irq_setup(void)
444{ 575{
445 /* disable IRQ7-0 */ 576 /* disable IRQ7-0 */
446 ctrl_outl(0xff000000, INTC_INTMSK0); 577 __raw_writel(0xff000000, INTC_INTMSK0);
447 578
448 /* disable IRL3-0 + IRL7-4 */ 579 /* disable IRL3-0 + IRL7-4 */
449 ctrl_outl(0xc0000000, INTC_INTMSK1); 580 __raw_writel(0xc0000000, INTC_INTMSK1);
450 ctrl_outl(0xfffefffe, INTC_INTMSK2); 581 __raw_writel(0xfffefffe, INTC_INTMSK2);
451 582
452 /* select IRL mode for IRL3-0 + IRL7-4 */ 583 /* select IRL mode for IRL3-0 + IRL7-4 */
453 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 584 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
454 585
455 /* disable holding function, ie enable "SH-4 Mode" */ 586 /* disable holding function, ie enable "SH-4 Mode" */
456 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 587 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
457 588
458 register_intc_controller(&intc_desc); 589 register_intc_controller(&intc_desc);
459} 590}
@@ -463,27 +594,27 @@ void __init plat_irq_setup_pins(int mode)
463 switch (mode) { 594 switch (mode) {
464 case IRQ_MODE_IRQ: 595 case IRQ_MODE_IRQ:
465 /* select IRQ mode for IRL3-0 + IRL7-4 */ 596 /* select IRQ mode for IRL3-0 + IRL7-4 */
466 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 597 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
467 register_intc_controller(&intc_irq_desc); 598 register_intc_controller(&intc_irq_desc);
468 break; 599 break;
469 case IRQ_MODE_IRL7654: 600 case IRQ_MODE_IRL7654:
470 /* enable IRL7-4 but don't provide any masking */ 601 /* enable IRL7-4 but don't provide any masking */
471 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 602 __raw_writel(0x40000000, INTC_INTMSKCLR1);
472 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 603 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
473 break; 604 break;
474 case IRQ_MODE_IRL3210: 605 case IRQ_MODE_IRL3210:
475 /* enable IRL0-3 but don't provide any masking */ 606 /* enable IRL0-3 but don't provide any masking */
476 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 607 __raw_writel(0x80000000, INTC_INTMSKCLR1);
477 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 608 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
478 break; 609 break;
479 case IRQ_MODE_IRL7654_MASK: 610 case IRQ_MODE_IRL7654_MASK:
480 /* enable IRL7-4 and mask using cpu intc controller */ 611 /* enable IRL7-4 and mask using cpu intc controller */
481 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 612 __raw_writel(0x40000000, INTC_INTMSKCLR1);
482 register_intc_controller(&intc_irl7654_desc); 613 register_intc_controller(&intc_irl7654_desc);
483 break; 614 break;
484 case IRQ_MODE_IRL3210_MASK: 615 case IRQ_MODE_IRL3210_MASK:
485 /* enable IRL0-3 and mask using cpu intc controller */ 616 /* enable IRL0-3 and mask using cpu intc controller */
486 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 617 __raw_writel(0x80000000, INTC_INTMSKCLR1);
487 register_intc_controller(&intc_irl3210_desc); 618 register_intc_controller(&intc_irl3210_desc);
488 break; 619 break;
489 default: 620 default:
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 08:42:42 -0500