diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7770.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7770.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 7270d7fd6761..2c6aa22cf5f6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
@@ -17,6 +17,8 @@ | |||
17 | static struct plat_sci_port scif0_platform_data = { | 17 | static struct plat_sci_port scif0_platform_data = { |
18 | .mapbase = 0xff923000, | 18 | .mapbase = 0xff923000, |
19 | .flags = UPF_BOOT_AUTOCONF, | 19 | .flags = UPF_BOOT_AUTOCONF, |
20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
21 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
20 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
21 | .irqs = { 61, 61, 61, 61 }, | 23 | .irqs = { 61, 61, 61, 61 }, |
22 | }; | 24 | }; |
@@ -32,6 +34,8 @@ static struct platform_device scif0_device = { | |||
32 | static struct plat_sci_port scif1_platform_data = { | 34 | static struct plat_sci_port scif1_platform_data = { |
33 | .mapbase = 0xff924000, | 35 | .mapbase = 0xff924000, |
34 | .flags = UPF_BOOT_AUTOCONF, | 36 | .flags = UPF_BOOT_AUTOCONF, |
37 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
38 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
35 | .type = PORT_SCIF, | 39 | .type = PORT_SCIF, |
36 | .irqs = { 62, 62, 62, 62 }, | 40 | .irqs = { 62, 62, 62, 62 }, |
37 | }; | 41 | }; |
@@ -47,6 +51,8 @@ static struct platform_device scif1_device = { | |||
47 | static struct plat_sci_port scif2_platform_data = { | 51 | static struct plat_sci_port scif2_platform_data = { |
48 | .mapbase = 0xff925000, | 52 | .mapbase = 0xff925000, |
49 | .flags = UPF_BOOT_AUTOCONF, | 53 | .flags = UPF_BOOT_AUTOCONF, |
54 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
55 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
50 | .type = PORT_SCIF, | 56 | .type = PORT_SCIF, |
51 | .irqs = { 63, 63, 63, 63 }, | 57 | .irqs = { 63, 63, 63, 63 }, |
52 | }; | 58 | }; |
@@ -62,6 +68,8 @@ static struct platform_device scif2_device = { | |||
62 | static struct plat_sci_port scif3_platform_data = { | 68 | static struct plat_sci_port scif3_platform_data = { |
63 | .mapbase = 0xff926000, | 69 | .mapbase = 0xff926000, |
64 | .flags = UPF_BOOT_AUTOCONF, | 70 | .flags = UPF_BOOT_AUTOCONF, |
71 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
72 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
65 | .type = PORT_SCIF, | 73 | .type = PORT_SCIF, |
66 | .irqs = { 64, 64, 64, 64 }, | 74 | .irqs = { 64, 64, 64, 64 }, |
67 | }; | 75 | }; |
@@ -77,6 +85,8 @@ static struct platform_device scif3_device = { | |||
77 | static struct plat_sci_port scif4_platform_data = { | 85 | static struct plat_sci_port scif4_platform_data = { |
78 | .mapbase = 0xff927000, | 86 | .mapbase = 0xff927000, |
79 | .flags = UPF_BOOT_AUTOCONF, | 87 | .flags = UPF_BOOT_AUTOCONF, |
88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
89 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
80 | .type = PORT_SCIF, | 90 | .type = PORT_SCIF, |
81 | .irqs = { 65, 65, 65, 65 }, | 91 | .irqs = { 65, 65, 65, 65 }, |
82 | }; | 92 | }; |
@@ -92,6 +102,8 @@ static struct platform_device scif4_device = { | |||
92 | static struct plat_sci_port scif5_platform_data = { | 102 | static struct plat_sci_port scif5_platform_data = { |
93 | .mapbase = 0xff928000, | 103 | .mapbase = 0xff928000, |
94 | .flags = UPF_BOOT_AUTOCONF, | 104 | .flags = UPF_BOOT_AUTOCONF, |
105 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
106 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
95 | .type = PORT_SCIF, | 107 | .type = PORT_SCIF, |
96 | .irqs = { 66, 66, 66, 66 }, | 108 | .irqs = { 66, 66, 66, 66 }, |
97 | }; | 109 | }; |
@@ -107,6 +119,8 @@ static struct platform_device scif5_device = { | |||
107 | static struct plat_sci_port scif6_platform_data = { | 119 | static struct plat_sci_port scif6_platform_data = { |
108 | .mapbase = 0xff929000, | 120 | .mapbase = 0xff929000, |
109 | .flags = UPF_BOOT_AUTOCONF, | 121 | .flags = UPF_BOOT_AUTOCONF, |
122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
123 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
110 | .type = PORT_SCIF, | 124 | .type = PORT_SCIF, |
111 | .irqs = { 67, 67, 67, 67 }, | 125 | .irqs = { 67, 67, 67, 67 }, |
112 | }; | 126 | }; |
@@ -122,6 +136,8 @@ static struct platform_device scif6_device = { | |||
122 | static struct plat_sci_port scif7_platform_data = { | 136 | static struct plat_sci_port scif7_platform_data = { |
123 | .mapbase = 0xff92a000, | 137 | .mapbase = 0xff92a000, |
124 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
140 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
125 | .type = PORT_SCIF, | 141 | .type = PORT_SCIF, |
126 | .irqs = { 68, 68, 68, 68 }, | 142 | .irqs = { 68, 68, 68, 68 }, |
127 | }; | 143 | }; |
@@ -137,6 +153,8 @@ static struct platform_device scif7_device = { | |||
137 | static struct plat_sci_port scif8_platform_data = { | 153 | static struct plat_sci_port scif8_platform_data = { |
138 | .mapbase = 0xff92b000, | 154 | .mapbase = 0xff92b000, |
139 | .flags = UPF_BOOT_AUTOCONF, | 155 | .flags = UPF_BOOT_AUTOCONF, |
156 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
157 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
140 | .type = PORT_SCIF, | 158 | .type = PORT_SCIF, |
141 | .irqs = { 69, 69, 69, 69 }, | 159 | .irqs = { 69, 69, 69, 69 }, |
142 | }; | 160 | }; |
@@ -152,6 +170,8 @@ static struct platform_device scif8_device = { | |||
152 | static struct plat_sci_port scif9_platform_data = { | 170 | static struct plat_sci_port scif9_platform_data = { |
153 | .mapbase = 0xff92c000, | 171 | .mapbase = 0xff92c000, |
154 | .flags = UPF_BOOT_AUTOCONF, | 172 | .flags = UPF_BOOT_AUTOCONF, |
173 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | ||
174 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
155 | .type = PORT_SCIF, | 175 | .type = PORT_SCIF, |
156 | .irqs = { 70, 70, 70, 70 }, | 176 | .irqs = { 70, 70, 70, 70 }, |
157 | }; | 177 | }; |