aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7724.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c81
1 files changed, 7 insertions, 74 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index e7fa2a92fc1f..89fe16d20fdb 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -31,7 +31,7 @@
31#include <cpu/sh7724.h> 31#include <cpu/sh7724.h>
32 32
33/* DMA */ 33/* DMA */
34static struct sh_dmae_channel sh7724_dmae0_channels[] = { 34static const struct sh_dmae_channel sh7724_dmae_channels[] = {
35 { 35 {
36 .offset = 0, 36 .offset = 0,
37 .dmars = 0, 37 .dmars = 0,
@@ -59,51 +59,11 @@ static struct sh_dmae_channel sh7724_dmae0_channels[] = {
59 } 59 }
60}; 60};
61 61
62static struct sh_dmae_channel sh7724_dmae1_channels[] = { 62static const unsigned int ts_shift[] = TS_SHIFT;
63 {
64 .offset = 0,
65 .dmars = 0,
66 .dmars_bit = 0,
67 }, {
68 .offset = 0x10,
69 .dmars = 0,
70 .dmars_bit = 8,
71 }, {
72 .offset = 0x20,
73 .dmars = 4,
74 .dmars_bit = 0,
75 }, {
76 .offset = 0x30,
77 .dmars = 4,
78 .dmars_bit = 8,
79 }, {
80 .offset = 0x50,
81 .dmars = 8,
82 .dmars_bit = 0,
83 }, {
84 .offset = 0x60,
85 .dmars = 8,
86 .dmars_bit = 8,
87 }
88};
89
90static unsigned int ts_shift[] = TS_SHIFT;
91
92static struct sh_dmae_pdata dma0_platform_data = {
93 .channel = sh7724_dmae0_channels,
94 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
95 .ts_low_shift = CHCR_TS_LOW_SHIFT,
96 .ts_low_mask = CHCR_TS_LOW_MASK,
97 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
98 .ts_high_mask = CHCR_TS_HIGH_MASK,
99 .ts_shift = ts_shift,
100 .ts_shift_num = ARRAY_SIZE(ts_shift),
101 .dmaor_init = DMAOR_INIT,
102};
103 63
104static struct sh_dmae_pdata dma1_platform_data = { 64static struct sh_dmae_pdata dma_platform_data = {
105 .channel = sh7724_dmae1_channels, 65 .channel = sh7724_dmae_channels,
106 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels), 66 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
107 .ts_low_shift = CHCR_TS_LOW_SHIFT, 67 .ts_low_shift = CHCR_TS_LOW_SHIFT,
108 .ts_low_mask = CHCR_TS_LOW_MASK, 68 .ts_low_mask = CHCR_TS_LOW_MASK,
109 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 69 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
@@ -187,7 +147,7 @@ static struct platform_device dma0_device = {
187 .resource = sh7724_dmae0_resources, 147 .resource = sh7724_dmae0_resources,
188 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 148 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
189 .dev = { 149 .dev = {
190 .platform_data = &dma0_platform_data, 150 .platform_data = &dma_platform_data,
191 }, 151 },
192 .archdata = { 152 .archdata = {
193 .hwblk_id = HWBLK_DMAC0, 153 .hwblk_id = HWBLK_DMAC0,
@@ -200,7 +160,7 @@ static struct platform_device dma1_device = {
200 .resource = sh7724_dmae1_resources, 160 .resource = sh7724_dmae1_resources,
201 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 161 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
202 .dev = { 162 .dev = {
203 .platform_data = &dma1_platform_data, 163 .platform_data = &dma_platform_data,
204 }, 164 },
205 .archdata = { 165 .archdata = {
206 .hwblk_id = HWBLK_DMAC1, 166 .hwblk_id = HWBLK_DMAC1,
@@ -213,7 +173,6 @@ static struct plat_sci_port scif0_platform_data = {
213 .flags = UPF_BOOT_AUTOCONF, 173 .flags = UPF_BOOT_AUTOCONF,
214 .type = PORT_SCIF, 174 .type = PORT_SCIF,
215 .irqs = { 80, 80, 80, 80 }, 175 .irqs = { 80, 80, 80, 80 },
216 .clk = "scif0",
217}; 176};
218 177
219static struct platform_device scif0_device = { 178static struct platform_device scif0_device = {
@@ -229,7 +188,6 @@ static struct plat_sci_port scif1_platform_data = {
229 .flags = UPF_BOOT_AUTOCONF, 188 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF, 189 .type = PORT_SCIF,
231 .irqs = { 81, 81, 81, 81 }, 190 .irqs = { 81, 81, 81, 81 },
232 .clk = "scif1",
233}; 191};
234 192
235static struct platform_device scif1_device = { 193static struct platform_device scif1_device = {
@@ -245,7 +203,6 @@ static struct plat_sci_port scif2_platform_data = {
245 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF, 204 .type = PORT_SCIF,
247 .irqs = { 82, 82, 82, 82 }, 205 .irqs = { 82, 82, 82, 82 },
248 .clk = "scif2",
249}; 206};
250 207
251static struct platform_device scif2_device = { 208static struct platform_device scif2_device = {
@@ -261,7 +218,6 @@ static struct plat_sci_port scif3_platform_data = {
261 .flags = UPF_BOOT_AUTOCONF, 218 .flags = UPF_BOOT_AUTOCONF,
262 .type = PORT_SCIFA, 219 .type = PORT_SCIFA,
263 .irqs = { 56, 56, 56, 56 }, 220 .irqs = { 56, 56, 56, 56 },
264 .clk = "scif3",
265}; 221};
266 222
267static struct platform_device scif3_device = { 223static struct platform_device scif3_device = {
@@ -277,7 +233,6 @@ static struct plat_sci_port scif4_platform_data = {
277 .flags = UPF_BOOT_AUTOCONF, 233 .flags = UPF_BOOT_AUTOCONF,
278 .type = PORT_SCIFA, 234 .type = PORT_SCIFA,
279 .irqs = { 88, 88, 88, 88 }, 235 .irqs = { 88, 88, 88, 88 },
280 .clk = "scif4",
281}; 236};
282 237
283static struct platform_device scif4_device = { 238static struct platform_device scif4_device = {
@@ -293,7 +248,6 @@ static struct plat_sci_port scif5_platform_data = {
293 .flags = UPF_BOOT_AUTOCONF, 248 .flags = UPF_BOOT_AUTOCONF,
294 .type = PORT_SCIFA, 249 .type = PORT_SCIFA,
295 .irqs = { 109, 109, 109, 109 }, 250 .irqs = { 109, 109, 109, 109 },
296 .clk = "scif5",
297}; 251};
298 252
299static struct platform_device scif5_device = { 253static struct platform_device scif5_device = {
@@ -485,17 +439,14 @@ static struct platform_device veu1_device = {
485}; 439};
486 440
487static struct sh_timer_config cmt_platform_data = { 441static struct sh_timer_config cmt_platform_data = {
488 .name = "CMT",
489 .channel_offset = 0x60, 442 .channel_offset = 0x60,
490 .timer_bit = 5, 443 .timer_bit = 5,
491 .clk = "cmt0",
492 .clockevent_rating = 125, 444 .clockevent_rating = 125,
493 .clocksource_rating = 200, 445 .clocksource_rating = 200,
494}; 446};
495 447
496static struct resource cmt_resources[] = { 448static struct resource cmt_resources[] = {
497 [0] = { 449 [0] = {
498 .name = "CMT",
499 .start = 0x044a0060, 450 .start = 0x044a0060,
500 .end = 0x044a006b, 451 .end = 0x044a006b,
501 .flags = IORESOURCE_MEM, 452 .flags = IORESOURCE_MEM,
@@ -520,16 +471,13 @@ static struct platform_device cmt_device = {
520}; 471};
521 472
522static struct sh_timer_config tmu0_platform_data = { 473static struct sh_timer_config tmu0_platform_data = {
523 .name = "TMU0",
524 .channel_offset = 0x04, 474 .channel_offset = 0x04,
525 .timer_bit = 0, 475 .timer_bit = 0,
526 .clk = "tmu0",
527 .clockevent_rating = 200, 476 .clockevent_rating = 200,
528}; 477};
529 478
530static struct resource tmu0_resources[] = { 479static struct resource tmu0_resources[] = {
531 [0] = { 480 [0] = {
532 .name = "TMU0",
533 .start = 0xffd80008, 481 .start = 0xffd80008,
534 .end = 0xffd80013, 482 .end = 0xffd80013,
535 .flags = IORESOURCE_MEM, 483 .flags = IORESOURCE_MEM,
@@ -554,16 +502,13 @@ static struct platform_device tmu0_device = {
554}; 502};
555 503
556static struct sh_timer_config tmu1_platform_data = { 504static struct sh_timer_config tmu1_platform_data = {
557 .name = "TMU1",
558 .channel_offset = 0x10, 505 .channel_offset = 0x10,
559 .timer_bit = 1, 506 .timer_bit = 1,
560 .clk = "tmu0",
561 .clocksource_rating = 200, 507 .clocksource_rating = 200,
562}; 508};
563 509
564static struct resource tmu1_resources[] = { 510static struct resource tmu1_resources[] = {
565 [0] = { 511 [0] = {
566 .name = "TMU1",
567 .start = 0xffd80014, 512 .start = 0xffd80014,
568 .end = 0xffd8001f, 513 .end = 0xffd8001f,
569 .flags = IORESOURCE_MEM, 514 .flags = IORESOURCE_MEM,
@@ -588,15 +533,12 @@ static struct platform_device tmu1_device = {
588}; 533};
589 534
590static struct sh_timer_config tmu2_platform_data = { 535static struct sh_timer_config tmu2_platform_data = {
591 .name = "TMU2",
592 .channel_offset = 0x1c, 536 .channel_offset = 0x1c,
593 .timer_bit = 2, 537 .timer_bit = 2,
594 .clk = "tmu0",
595}; 538};
596 539
597static struct resource tmu2_resources[] = { 540static struct resource tmu2_resources[] = {
598 [0] = { 541 [0] = {
599 .name = "TMU2",
600 .start = 0xffd80020, 542 .start = 0xffd80020,
601 .end = 0xffd8002b, 543 .end = 0xffd8002b,
602 .flags = IORESOURCE_MEM, 544 .flags = IORESOURCE_MEM,
@@ -622,15 +564,12 @@ static struct platform_device tmu2_device = {
622 564
623 565
624static struct sh_timer_config tmu3_platform_data = { 566static struct sh_timer_config tmu3_platform_data = {
625 .name = "TMU3",
626 .channel_offset = 0x04, 567 .channel_offset = 0x04,
627 .timer_bit = 0, 568 .timer_bit = 0,
628 .clk = "tmu1",
629}; 569};
630 570
631static struct resource tmu3_resources[] = { 571static struct resource tmu3_resources[] = {
632 [0] = { 572 [0] = {
633 .name = "TMU3",
634 .start = 0xffd90008, 573 .start = 0xffd90008,
635 .end = 0xffd90013, 574 .end = 0xffd90013,
636 .flags = IORESOURCE_MEM, 575 .flags = IORESOURCE_MEM,
@@ -655,15 +594,12 @@ static struct platform_device tmu3_device = {
655}; 594};
656 595
657static struct sh_timer_config tmu4_platform_data = { 596static struct sh_timer_config tmu4_platform_data = {
658 .name = "TMU4",
659 .channel_offset = 0x10, 597 .channel_offset = 0x10,
660 .timer_bit = 1, 598 .timer_bit = 1,
661 .clk = "tmu1",
662}; 599};
663 600
664static struct resource tmu4_resources[] = { 601static struct resource tmu4_resources[] = {
665 [0] = { 602 [0] = {
666 .name = "TMU4",
667 .start = 0xffd90014, 603 .start = 0xffd90014,
668 .end = 0xffd9001f, 604 .end = 0xffd9001f,
669 .flags = IORESOURCE_MEM, 605 .flags = IORESOURCE_MEM,
@@ -688,15 +624,12 @@ static struct platform_device tmu4_device = {
688}; 624};
689 625
690static struct sh_timer_config tmu5_platform_data = { 626static struct sh_timer_config tmu5_platform_data = {
691 .name = "TMU5",
692 .channel_offset = 0x1c, 627 .channel_offset = 0x1c,
693 .timer_bit = 2, 628 .timer_bit = 2,
694 .clk = "tmu1",
695}; 629};
696 630
697static struct resource tmu5_resources[] = { 631static struct resource tmu5_resources[] = {
698 [0] = { 632 [0] = {
699 .name = "TMU5",
700 .start = 0xffd90020, 633 .start = 0xffd90020,
701 .end = 0xffd9002b, 634 .end = 0xffd9002b,
702 .flags = IORESOURCE_MEM, 635 .flags = IORESOURCE_MEM,