aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7786.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c115
1 files changed, 21 insertions, 94 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index 42e403be9076..f6c0c3d5599f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -125,8 +125,6 @@ static struct clk mstp_clks[MSTP_NR] = {
125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0), 125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
126}; 126};
127 127
128#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
129
130static struct clk_lookup lookups[] = { 128static struct clk_lookup lookups[] = {
131 /* main clocks */ 129 /* main clocks */
132 CLKDEV_CON_ID("extal", &extal_clk), 130 CLKDEV_CON_ID("extal", &extal_clk),
@@ -141,37 +139,13 @@ static struct clk_lookup lookups[] = {
141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 139 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
142 140
143 /* MSTP32 clocks */ 141 /* MSTP32 clocks */
144 { 142 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
145 /* SCIF5 */ 143 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
146 .dev_id = "sh-sci.5", 144 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
147 .con_id = "sci_fck", 145 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
148 .clk = &mstp_clks[MSTP029], 146 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
149 }, { 147 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
150 /* SCIF4 */ 148
151 .dev_id = "sh-sci.4",
152 .con_id = "sci_fck",
153 .clk = &mstp_clks[MSTP028],
154 }, {
155 /* SCIF3 */
156 .dev_id = "sh-sci.3",
157 .con_id = "sci_fck",
158 .clk = &mstp_clks[MSTP027],
159 }, {
160 /* SCIF2 */
161 .dev_id = "sh-sci.2",
162 .con_id = "sci_fck",
163 .clk = &mstp_clks[MSTP026],
164 }, {
165 /* SCIF1 */
166 .dev_id = "sh-sci.1",
167 .con_id = "sci_fck",
168 .clk = &mstp_clks[MSTP025],
169 }, {
170 /* SCIF0 */
171 .dev_id = "sh-sci.0",
172 .con_id = "sci_fck",
173 .clk = &mstp_clks[MSTP024],
174 },
175 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]), 149 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
176 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]), 150 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
177 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), 151 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
@@ -180,67 +154,20 @@ static struct clk_lookup lookups[] = {
180 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), 154 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
181 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]), 155 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
182 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]), 156 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
183 { 157
184 /* TMU0 */ 158 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
185 .dev_id = "sh_tmu.0", 159 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]),
186 .con_id = "tmu_fck", 160 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]),
187 .clk = &mstp_clks[MSTP008], 161 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]),
188 }, { 162 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]),
189 /* TMU1 */ 163 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]),
190 .dev_id = "sh_tmu.1", 164 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP010]),
191 .con_id = "tmu_fck", 165 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP010]),
192 .clk = &mstp_clks[MSTP008], 166 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP010]),
193 }, { 167 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.9", &mstp_clks[MSTP011]),
194 /* TMU2 */ 168 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.10", &mstp_clks[MSTP011]),
195 .dev_id = "sh_tmu.2", 169 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.11", &mstp_clks[MSTP011]),
196 .con_id = "tmu_fck", 170
197 .clk = &mstp_clks[MSTP008],
198 }, {
199 /* TMU3 */
200 .dev_id = "sh_tmu.3",
201 .con_id = "tmu_fck",
202 .clk = &mstp_clks[MSTP009],
203 }, {
204 /* TMU4 */
205 .dev_id = "sh_tmu.4",
206 .con_id = "tmu_fck",
207 .clk = &mstp_clks[MSTP009],
208 }, {
209 /* TMU5 */
210 .dev_id = "sh_tmu.5",
211 .con_id = "tmu_fck",
212 .clk = &mstp_clks[MSTP009],
213 }, {
214 /* TMU6 */
215 .dev_id = "sh_tmu.6",
216 .con_id = "tmu_fck",
217 .clk = &mstp_clks[MSTP010],
218 }, {
219 /* TMU7 */
220 .dev_id = "sh_tmu.7",
221 .con_id = "tmu_fck",
222 .clk = &mstp_clks[MSTP010],
223 }, {
224 /* TMU8 */
225 .dev_id = "sh_tmu.8",
226 .con_id = "tmu_fck",
227 .clk = &mstp_clks[MSTP010],
228 }, {
229 /* TMU9 */
230 .dev_id = "sh_tmu.9",
231 .con_id = "tmu_fck",
232 .clk = &mstp_clks[MSTP011],
233 }, {
234 /* TMU10 */
235 .dev_id = "sh_tmu.10",
236 .con_id = "tmu_fck",
237 .clk = &mstp_clks[MSTP011],
238 }, {
239 /* TMU11 */
240 .dev_id = "sh_tmu.11",
241 .con_id = "tmu_fck",
242 .clk = &mstp_clks[MSTP011],
243 },
244 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]), 171 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
245 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]), 172 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
246 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), 173 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),