1 files changed, 21 insertions, 17 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 2bbff53fcd87..2d9700c6b53a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -41,8 +41,6 @@
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -51,8 +49,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -76,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
 };
 
 static struct clk fll_clk = {
-        .name           = "fll_clk",
-        .id             = -1,
         .ops            = &fll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -98,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -115,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
 };
 
 static struct clk div3_clk = {
-        .name           = "div3_clk",
-        .id             = -1,
         .ops            = &div3_clk_ops,
         .parent         = &pll_clk,
 };
@@ -153,15 +143,15 @@ static struct clk_div4_table div4_table = {
 
 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
-        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
+        [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 };
 
 enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
@@ -234,6 +224,20 @@ static struct clk mstp_clks[HWBLK_NR] = {
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("fll_clk", &fll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+        CLKDEV_CON_ID("div3_clk", &div3_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
+
         /* DIV6 clocks */
         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
         CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),