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Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7722.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c365
1 files changed, 183 insertions, 182 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 8e53829ca078..f777d00d4af6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -646,207 +646,208 @@ static struct clk_ops sh7722_mstpcr_clk_ops = {
646 .recalc = followparent_recalc, 646 .recalc = followparent_recalc,
647}; 647};
648 648
649#define MSTPCR(_name, _parent, regnr, bitnr) \ 649#define MSTPCR(_name, _parent, regnr, bitnr, _flags) \
650{ \ 650{ \
651 .name = _name, \ 651 .name = _name, \
652 .flags = _flags, \
652 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \ 653 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
653 .ops = (void *)_parent, \ 654 .ops = (void *)_parent, \
654} 655}
655 656
656static struct clk sh7722_mstpcr_clocks[] = { 657static struct clk sh7722_mstpcr_clocks[] = {
657#if defined(CONFIG_CPU_SUBTYPE_SH7722) 658#if defined(CONFIG_CPU_SUBTYPE_SH7722)
658 MSTPCR("uram0", "umem_clk", 0, 28), 659 MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
659 MSTPCR("xymem0", "bus_clk", 0, 26), 660 MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
660 MSTPCR("tmu0", "peripheral_clk", 0, 15), 661 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
661 MSTPCR("cmt0", "r_clk", 0, 14), 662 MSTPCR("cmt0", "r_clk", 0, 14, 0),
662 MSTPCR("rwdt0", "r_clk", 0, 13), 663 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
663 MSTPCR("flctl0", "peripheral_clk", 0, 10), 664 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
664 MSTPCR("scif0", "peripheral_clk", 0, 7), 665 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
665 MSTPCR("scif1", "peripheral_clk", 0, 6), 666 MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
666 MSTPCR("scif2", "peripheral_clk", 0, 5), 667 MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
667 MSTPCR("i2c0", "peripheral_clk", 1, 9), 668 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
668 MSTPCR("rtc0", "r_clk", 1, 8), 669 MSTPCR("rtc0", "r_clk", 1, 8, 0),
669 MSTPCR("sdhi0", "peripheral_clk", 2, 18), 670 MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
670 MSTPCR("keysc0", "r_clk", 2, 14), 671 MSTPCR("keysc0", "r_clk", 2, 14, 0),
671 MSTPCR("usbf0", "peripheral_clk", 2, 11), 672 MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
672 MSTPCR("2dg0", "bus_clk", 2, 9), 673 MSTPCR("2dg0", "bus_clk", 2, 9, 0),
673 MSTPCR("siu0", "bus_clk", 2, 8), 674 MSTPCR("siu0", "bus_clk", 2, 8, 0),
674 MSTPCR("vou0", "bus_clk", 2, 5), 675 MSTPCR("vou0", "bus_clk", 2, 5, 0),
675 MSTPCR("jpu0", "bus_clk", 2, 6), 676 MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
676 MSTPCR("beu0", "bus_clk", 2, 4), 677 MSTPCR("beu0", "bus_clk", 2, 4, 0),
677 MSTPCR("ceu0", "bus_clk", 2, 3), 678 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
678 MSTPCR("veu0", "bus_clk", 2, 2), 679 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
679 MSTPCR("vpu0", "bus_clk", 2, 1), 680 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
680 MSTPCR("lcdc0", "bus_clk", 2, 0), 681 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
681#endif 682#endif
682#if defined(CONFIG_CPU_SUBTYPE_SH7723) 683#if defined(CONFIG_CPU_SUBTYPE_SH7723)
683 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 684 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
684 MSTPCR("tlb0", "cpu_clk", 0, 31), 685 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
685 MSTPCR("ic0", "cpu_clk", 0, 30), 686 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
686 MSTPCR("oc0", "cpu_clk", 0, 29), 687 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
687 MSTPCR("l2c0", "sh_clk", 0, 28), 688 MSTPCR("l2c0", "sh_clk", 0, 28, 0),
688 MSTPCR("ilmem0", "cpu_clk", 0, 27), 689 MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
689 MSTPCR("fpu0", "cpu_clk", 0, 24), 690 MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
690 MSTPCR("intc0", "cpu_clk", 0, 22), 691 MSTPCR("intc0", "cpu_clk", 0, 22, 0),
691 MSTPCR("dmac0", "bus_clk", 0, 21), 692 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
692 MSTPCR("sh0", "sh_clk", 0, 20), 693 MSTPCR("sh0", "sh_clk", 0, 20, 0),
693 MSTPCR("hudi0", "peripheral_clk", 0, 19), 694 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
694 MSTPCR("ubc0", "cpu_clk", 0, 17), 695 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
695 MSTPCR("tmu0", "peripheral_clk", 0, 15), 696 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
696 MSTPCR("cmt0", "r_clk", 0, 14), 697 MSTPCR("cmt0", "r_clk", 0, 14, 0),
697 MSTPCR("rwdt0", "r_clk", 0, 13), 698 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
698 MSTPCR("dmac1", "bus_clk", 0, 12), 699 MSTPCR("dmac1", "bus_clk", 0, 12, 0),
699 MSTPCR("tmu1", "peripheral_clk", 0, 11), 700 MSTPCR("tmu1", "peripheral_clk", 0, 11, 0),
700 MSTPCR("flctl0", "peripheral_clk", 0, 10), 701 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
701 MSTPCR("scif0", "peripheral_clk", 0, 9), 702 MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
702 MSTPCR("scif1", "peripheral_clk", 0, 8), 703 MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
703 MSTPCR("scif2", "peripheral_clk", 0, 7), 704 MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
704 MSTPCR("scif3", "bus_clk", 0, 6), 705 MSTPCR("scif3", "bus_clk", 0, 6, 0),
705 MSTPCR("scif4", "bus_clk", 0, 5), 706 MSTPCR("scif4", "bus_clk", 0, 5, 0),
706 MSTPCR("scif5", "bus_clk", 0, 4), 707 MSTPCR("scif5", "bus_clk", 0, 4, 0),
707 MSTPCR("msiof0", "bus_clk", 0, 2), 708 MSTPCR("msiof0", "bus_clk", 0, 2, 0),
708 MSTPCR("msiof1", "bus_clk", 0, 1), 709 MSTPCR("msiof1", "bus_clk", 0, 1, 0),
709 MSTPCR("meram0", "sh_clk", 0, 0), 710 MSTPCR("meram0", "sh_clk", 0, 0, CLK_ENABLE_ON_INIT),
710 MSTPCR("i2c0", "peripheral_clk", 1, 9), 711 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
711 MSTPCR("rtc0", "r_clk", 1, 8), 712 MSTPCR("rtc0", "r_clk", 1, 8, 0),
712 MSTPCR("atapi0", "sh_clk", 2, 28), 713 MSTPCR("atapi0", "sh_clk", 2, 28, 0),
713 MSTPCR("adc0", "peripheral_clk", 2, 28), 714 MSTPCR("adc0", "peripheral_clk", 2, 28, 0),
714 MSTPCR("tpu0", "bus_clk", 2, 25), 715 MSTPCR("tpu0", "bus_clk", 2, 25, 0),
715 MSTPCR("irda0", "peripheral_clk", 2, 24), 716 MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
716 MSTPCR("tsif0", "bus_clk", 2, 22), 717 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
717 MSTPCR("icb0", "bus_clk", 2, 21), 718 MSTPCR("icb0", "bus_clk", 2, 21, 0),
718 MSTPCR("sdhi0", "bus_clk", 2, 18), 719 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
719 MSTPCR("sdhi1", "bus_clk", 2, 17), 720 MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
720 MSTPCR("keysc0", "r_clk", 2, 14), 721 MSTPCR("keysc0", "r_clk", 2, 14, 0),
721 MSTPCR("usb0", "bus_clk", 2, 11), 722 MSTPCR("usb0", "bus_clk", 2, 11, 0),
722 MSTPCR("2dg0", "bus_clk", 2, 10), 723 MSTPCR("2dg0", "bus_clk", 2, 10, 0),
723 MSTPCR("siu0", "bus_clk", 2, 8), 724 MSTPCR("siu0", "bus_clk", 2, 8, 0),
724 MSTPCR("veu1", "bus_clk", 2, 6), 725 MSTPCR("veu1", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
725 MSTPCR("vou0", "bus_clk", 2, 5), 726 MSTPCR("vou0", "bus_clk", 2, 5, 0),
726 MSTPCR("beu0", "bus_clk", 2, 4), 727 MSTPCR("beu0", "bus_clk", 2, 4, 0),
727 MSTPCR("ceu0", "bus_clk", 2, 3), 728 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
728 MSTPCR("veu0", "bus_clk", 2, 2), 729 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
729 MSTPCR("vpu0", "bus_clk", 2, 1), 730 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
730 MSTPCR("lcdc0", "bus_clk", 2, 0), 731 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
731#endif 732#endif
732#if defined(CONFIG_CPU_SUBTYPE_SH7724) 733#if defined(CONFIG_CPU_SUBTYPE_SH7724)
733 /* See Datasheet : Overview -> Block Diagram */ 734 /* See Datasheet : Overview -> Block Diagram */
734 MSTPCR("tlb0", "cpu_clk", 0, 31), 735 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
735 MSTPCR("ic0", "cpu_clk", 0, 30), 736 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
736 MSTPCR("oc0", "cpu_clk", 0, 29), 737 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
737 MSTPCR("rs0", "bus_clk", 0, 28), 738 MSTPCR("rs0", "bus_clk", 0, 28, 0),
738 MSTPCR("ilmem0", "cpu_clk", 0, 27), 739 MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
739 MSTPCR("l2c0", "sh_clk", 0, 26), 740 MSTPCR("l2c0", "sh_clk", 0, 26, 0),
740 MSTPCR("fpu0", "cpu_clk", 0, 24), 741 MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
741 MSTPCR("intc0", "peripheral_clk", 0, 22), 742 MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
742 MSTPCR("dmac0", "bus_clk", 0, 21), 743 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
743 MSTPCR("sh0", "sh_clk", 0, 20), 744 MSTPCR("sh0", "sh_clk", 0, 20, 0),
744 MSTPCR("hudi0", "peripheral_clk", 0, 19), 745 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
745 MSTPCR("ubc0", "cpu_clk", 0, 17), 746 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
746 MSTPCR("tmu0", "peripheral_clk", 0, 15), 747 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
747 MSTPCR("cmt0", "r_clk", 0, 14), 748 MSTPCR("cmt0", "r_clk", 0, 14, 0),
748 MSTPCR("rwdt0", "r_clk", 0, 13), 749 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
749 MSTPCR("dmac1", "bus_clk", 0, 12), 750 MSTPCR("dmac1", "bus_clk", 0, 12, 0),
750 MSTPCR("tmu1", "peripheral_clk", 0, 10), 751 MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
751 MSTPCR("scif0", "peripheral_clk", 0, 9), 752 MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
752 MSTPCR("scif1", "peripheral_clk", 0, 8), 753 MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
753 MSTPCR("scif2", "peripheral_clk", 0, 7), 754 MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
754 MSTPCR("scif3", "bus_clk", 0, 6), 755 MSTPCR("scif3", "bus_clk", 0, 6, 0),
755 MSTPCR("scif4", "bus_clk", 0, 5), 756 MSTPCR("scif4", "bus_clk", 0, 5, 0),
756 MSTPCR("scif5", "bus_clk", 0, 4), 757 MSTPCR("scif5", "bus_clk", 0, 4, 0),
757 MSTPCR("msiof0", "bus_clk", 0, 2), 758 MSTPCR("msiof0", "bus_clk", 0, 2, 0),
758 MSTPCR("msiof1", "bus_clk", 0, 1), 759 MSTPCR("msiof1", "bus_clk", 0, 1, 0),
759 MSTPCR("keysc0", "r_clk", 1, 12), 760 MSTPCR("keysc0", "r_clk", 1, 12, 0),
760 MSTPCR("rtc0", "r_clk", 1, 11), 761 MSTPCR("rtc0", "r_clk", 1, 11, 0),
761 MSTPCR("i2c0", "peripheral_clk", 1, 9), 762 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
762 MSTPCR("i2c1", "peripheral_clk", 1, 8), 763 MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
763 MSTPCR("mmc0", "bus_clk", 2, 29), 764 MSTPCR("mmc0", "bus_clk", 2, 29, 0),
764 MSTPCR("eth0", "bus_clk", 2, 28), 765 MSTPCR("eth0", "bus_clk", 2, 28, 0),
765 MSTPCR("atapi0", "bus_clk", 2, 26), 766 MSTPCR("atapi0", "bus_clk", 2, 26, 0),
766 MSTPCR("tpu0", "bus_clk", 2, 25), 767 MSTPCR("tpu0", "bus_clk", 2, 25, 0),
767 MSTPCR("irda0", "peripheral_clk", 2, 24), 768 MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
768 MSTPCR("tsif0", "bus_clk", 2, 22), 769 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
769 MSTPCR("usb1", "bus_clk", 2, 21), 770 MSTPCR("usb1", "bus_clk", 2, 21, 0),
770 MSTPCR("usb0", "bus_clk", 2, 20), 771 MSTPCR("usb0", "bus_clk", 2, 20, 0),
771 MSTPCR("2dg0", "bus_clk", 2, 19), 772 MSTPCR("2dg0", "bus_clk", 2, 19, 0),
772 MSTPCR("sdhi0", "bus_clk", 2, 18), 773 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
773 MSTPCR("sdhi1", "bus_clk", 2, 17), 774 MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
774 MSTPCR("veu1", "bus_clk", 2, 15), 775 MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
775 MSTPCR("ceu1", "bus_clk", 2, 13), 776 MSTPCR("ceu1", "bus_clk", 2, 13, 0),
776 MSTPCR("beu1", "bus_clk", 2, 12), 777 MSTPCR("beu1", "bus_clk", 2, 12, 0),
777 MSTPCR("2ddmac0", "sh_clk", 2, 10), 778 MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
778 MSTPCR("spu0", "bus_clk", 2, 9), 779 MSTPCR("spu0", "bus_clk", 2, 9, 0),
779 MSTPCR("jpu0", "bus_clk", 2, 6), 780 MSTPCR("jpu0", "bus_clk", 2, 6, 0),
780 MSTPCR("vou0", "bus_clk", 2, 5), 781 MSTPCR("vou0", "bus_clk", 2, 5, 0),
781 MSTPCR("beu0", "bus_clk", 2, 4), 782 MSTPCR("beu0", "bus_clk", 2, 4, 0),
782 MSTPCR("ceu0", "bus_clk", 2, 3), 783 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
783 MSTPCR("veu0", "bus_clk", 2, 2), 784 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
784 MSTPCR("vpu0", "bus_clk", 2, 1), 785 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
785 MSTPCR("lcdc0", "bus_clk", 2, 0), 786 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
786#endif 787#endif
787#if defined(CONFIG_CPU_SUBTYPE_SH7343) 788#if defined(CONFIG_CPU_SUBTYPE_SH7343)
788 MSTPCR("uram0", "umem_clk", 0, 28), 789 MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
789 MSTPCR("xymem0", "bus_clk", 0, 26), 790 MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
790 MSTPCR("tmu0", "peripheral_clk", 0, 15), 791 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
791 MSTPCR("cmt0", "r_clk", 0, 14), 792 MSTPCR("cmt0", "r_clk", 0, 14, 0),
792 MSTPCR("rwdt0", "r_clk", 0, 13), 793 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
793 MSTPCR("scif0", "peripheral_clk", 0, 7), 794 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
794 MSTPCR("scif1", "peripheral_clk", 0, 6), 795 MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
795 MSTPCR("scif2", "peripheral_clk", 0, 5), 796 MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
796 MSTPCR("scif3", "peripheral_clk", 0, 4), 797 MSTPCR("scif3", "peripheral_clk", 0, 4, 0),
797 MSTPCR("i2c0", "peripheral_clk", 1, 9), 798 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
798 MSTPCR("i2c1", "peripheral_clk", 1, 8), 799 MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
799 MSTPCR("sdhi0", "peripheral_clk", 2, 18), 800 MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
800 MSTPCR("keysc0", "r_clk", 2, 14), 801 MSTPCR("keysc0", "r_clk", 2, 14, 0),
801 MSTPCR("usbf0", "peripheral_clk", 2, 11), 802 MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
802 MSTPCR("siu0", "bus_clk", 2, 8), 803 MSTPCR("siu0", "bus_clk", 2, 8, 0),
803 MSTPCR("jpu0", "bus_clk", 2, 6), 804 MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
804 MSTPCR("vou0", "bus_clk", 2, 5), 805 MSTPCR("vou0", "bus_clk", 2, 5, 0),
805 MSTPCR("beu0", "bus_clk", 2, 4), 806 MSTPCR("beu0", "bus_clk", 2, 4, 0),
806 MSTPCR("ceu0", "bus_clk", 2, 3), 807 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
807 MSTPCR("veu0", "bus_clk", 2, 2), 808 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
808 MSTPCR("vpu0", "bus_clk", 2, 1), 809 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
809 MSTPCR("lcdc0", "bus_clk", 2, 0), 810 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
810#endif 811#endif
811#if defined(CONFIG_CPU_SUBTYPE_SH7366) 812#if defined(CONFIG_CPU_SUBTYPE_SH7366)
812 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 813 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
813 MSTPCR("tlb0", "cpu_clk", 0, 31), 814 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
814 MSTPCR("ic0", "cpu_clk", 0, 30), 815 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
815 MSTPCR("oc0", "cpu_clk", 0, 29), 816 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
816 MSTPCR("rsmem0", "sh_clk", 0, 28), 817 MSTPCR("rsmem0", "sh_clk", 0, 28, CLK_ENABLE_ON_INIT),
817 MSTPCR("xymem0", "cpu_clk", 0, 26), 818 MSTPCR("xymem0", "cpu_clk", 0, 26, CLK_ENABLE_ON_INIT),
818 MSTPCR("intc30", "peripheral_clk", 0, 23), 819 MSTPCR("intc30", "peripheral_clk", 0, 23, 0),
819 MSTPCR("intc0", "peripheral_clk", 0, 22), 820 MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
820 MSTPCR("dmac0", "bus_clk", 0, 21), 821 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
821 MSTPCR("sh0", "sh_clk", 0, 20), 822 MSTPCR("sh0", "sh_clk", 0, 20, 0),
822 MSTPCR("hudi0", "peripheral_clk", 0, 19), 823 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
823 MSTPCR("ubc0", "cpu_clk", 0, 17), 824 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
824 MSTPCR("tmu0", "peripheral_clk", 0, 15), 825 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
825 MSTPCR("cmt0", "r_clk", 0, 14), 826 MSTPCR("cmt0", "r_clk", 0, 14, 0),
826 MSTPCR("rwdt0", "r_clk", 0, 13), 827 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
827 MSTPCR("flctl0", "peripheral_clk", 0, 10), 828 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
828 MSTPCR("scif0", "peripheral_clk", 0, 7), 829 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
829 MSTPCR("scif1", "bus_clk", 0, 6), 830 MSTPCR("scif1", "bus_clk", 0, 6, 0),
830 MSTPCR("scif2", "bus_clk", 0, 5), 831 MSTPCR("scif2", "bus_clk", 0, 5, 0),
831 MSTPCR("msiof0", "peripheral_clk", 0, 2), 832 MSTPCR("msiof0", "peripheral_clk", 0, 2, 0),
832 MSTPCR("sbr0", "peripheral_clk", 0, 1), 833 MSTPCR("sbr0", "peripheral_clk", 0, 1, 0),
833 MSTPCR("i2c0", "peripheral_clk", 1, 9), 834 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
834 MSTPCR("icb0", "bus_clk", 2, 27), 835 MSTPCR("icb0", "bus_clk", 2, 27, 0),
835 MSTPCR("meram0", "sh_clk", 2, 26), 836 MSTPCR("meram0", "sh_clk", 2, 26, 0),
836 MSTPCR("dacc0", "peripheral_clk", 2, 24), 837 MSTPCR("dacc0", "peripheral_clk", 2, 24, 0),
837 MSTPCR("dacy0", "peripheral_clk", 2, 23), 838 MSTPCR("dacy0", "peripheral_clk", 2, 23, 0),
838 MSTPCR("tsif0", "bus_clk", 2, 22), 839 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
839 MSTPCR("sdhi0", "bus_clk", 2, 18), 840 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
840 MSTPCR("mmcif0", "bus_clk", 2, 17), 841 MSTPCR("mmcif0", "bus_clk", 2, 17, 0),
841 MSTPCR("usb0", "bus_clk", 2, 11), 842 MSTPCR("usb0", "bus_clk", 2, 11, 0),
842 MSTPCR("siu0", "bus_clk", 2, 8), 843 MSTPCR("siu0", "bus_clk", 2, 8, 0),
843 MSTPCR("veu1", "bus_clk", 2, 7), 844 MSTPCR("veu1", "bus_clk", 2, 7, CLK_ENABLE_ON_INIT),
844 MSTPCR("vou0", "bus_clk", 2, 5), 845 MSTPCR("vou0", "bus_clk", 2, 5, 0),
845 MSTPCR("beu0", "bus_clk", 2, 4), 846 MSTPCR("beu0", "bus_clk", 2, 4, 0),
846 MSTPCR("ceu0", "bus_clk", 2, 3), 847 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
847 MSTPCR("veu0", "bus_clk", 2, 2), 848 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
848 MSTPCR("vpu0", "bus_clk", 2, 1), 849 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
849 MSTPCR("lcdc0", "bus_clk", 2, 0), 850 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
850#endif 851#endif
851}; 852};
852 853
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 08:19:52 -0500