1 files changed, 97 insertions, 88 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index b26e2bc5894d..9d28c88d2f9d 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -10,11 +10,10 @@
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
 #include <linux/init.h>
+#include <linux/io.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
-#include <asm/io.h>
 int __init detect_cpu_and_cache_system(void)
 {
@@ -36,20 +35,20 @@ int __init detect_cpu_and_cache_system(void)
        /*
         * Setup some sane SH-4 defaults for the icache
         */
-        cpu_data->icache.way_incr       = (1 << 13);
+        current_cpu_data.icache.way_incr        = (1 << 13);
-        cpu_data->icache.entry_shift    = 5;
+        current_cpu_data.icache.entry_shift     = 5;
-        cpu_data->icache.sets           = 256;
+        current_cpu_data.icache.sets            = 256;
-        cpu_data->icache.ways           = 1;
+        current_cpu_data.icache.ways            = 1;
-        cpu_data->icache.linesz         = L1_CACHE_BYTES;
+        current_cpu_data.icache.linesz          = L1_CACHE_BYTES;
        /*
         * And again for the dcache ..
         */
-        cpu_data->dcache.way_incr       = (1 << 14);
+        current_cpu_data.dcache.way_incr        = (1 << 14);
-        cpu_data->dcache.entry_shift    = 5;
+        current_cpu_data.dcache.entry_shift     = 5;
-        cpu_data->dcache.sets           = 512;
+        current_cpu_data.dcache.sets            = 512;
-        cpu_data->dcache.ways           = 1;
+        current_cpu_data.dcache.ways            = 1;
-        cpu_data->dcache.linesz         = L1_CACHE_BYTES;
+        current_cpu_data.dcache.linesz          = L1_CACHE_BYTES;
        /*
         * Setup some generic flags we can probe
@@ -57,16 +56,16 @@ int __init detect_cpu_and_cache_system(void)
         */
        if (((pvr >> 16) & 0xff) == 0x10) {
                if ((cvr & 0x02000000) == 0)
-                        cpu_data->flags |= CPU_HAS_L2_CACHE;
+                        current_cpu_data.flags |= CPU_HAS_L2_CACHE;
                if ((cvr & 0x10000000) == 0)
-                        cpu_data->flags |= CPU_HAS_DSP;
+                        current_cpu_data.flags |= CPU_HAS_DSP;
-                cpu_data->flags |= CPU_HAS_LLSC;
+                current_cpu_data.flags |= CPU_HAS_LLSC;
        }
        /* FPU detection works for everyone */
        if ((cvr & 0x20000000) == 1)
-                cpu_data->flags |= CPU_HAS_FPU;
+                current_cpu_data.flags |= CPU_HAS_FPU;
        /* Mask off the upper chip ID */
        pvr &= 0xffff;
@@ -77,147 +76,151 @@ int __init detect_cpu_and_cache_system(void)
         */
        switch (pvr) {
        case 0x205:
-                cpu_data->type = CPU_SH7750;
+                current_cpu_data.type = CPU_SH7750;
-                cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
+                current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
                                   CPU_HAS_PERF_COUNTER;
                break;
        case 0x206:
-                cpu_data->type = CPU_SH7750S;
+                current_cpu_data.type = CPU_SH7750S;
-                cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
+                current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
                                   CPU_HAS_PERF_COUNTER;
                break;
        case 0x1100:
-                cpu_data->type = CPU_SH7751;
+                current_cpu_data.type = CPU_SH7751;
-                cpu_data->flags |= CPU_HAS_FPU;
+                current_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x2000:
-                cpu_data->type = CPU_SH73180;
+                current_cpu_data.type = CPU_SH73180;
-                cpu_data->icache.ways = 4;
+                current_cpu_data.icache.ways = 4;
-                cpu_data->dcache.ways = 4;
+                current_cpu_data.dcache.ways = 4;
-                cpu_data->flags |= CPU_HAS_LLSC;
+                current_cpu_data.flags |= CPU_HAS_LLSC;
                break;
        case 0x2001:
        case 0x2004:
-                cpu_data->type = CPU_SH7770;
+                current_cpu_data.type = CPU_SH7770;
-                cpu_data->icache.ways = 4;
+                current_cpu_data.icache.ways = 4;
-                cpu_data->dcache.ways = 4;
+                current_cpu_data.dcache.ways = 4;
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
+                current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
                break;
        case 0x2006:
        case 0x200A:
                if (prr == 0x61)
-                        cpu_data->type = CPU_SH7781;
+                        current_cpu_data.type = CPU_SH7781;
                else
-                        cpu_data->type = CPU_SH7780;
+                        current_cpu_data.type = CPU_SH7780;
-                cpu_data->icache.ways = 4;
+                current_cpu_data.icache.ways = 4;
-                cpu_data->dcache.ways = 4;
+                current_cpu_data.dcache.ways = 4;
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+                current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
                                   CPU_HAS_LLSC;
                break;
        case 0x3000:
        case 0x3003:
        case 0x3009:
-                cpu_data->type = CPU_SH7343;
+                current_cpu_data.type = CPU_SH7343;
-                cpu_data->icache.ways = 4;
+                current_cpu_data.icache.ways = 4;
-                cpu_data->dcache.ways = 4;
+                current_cpu_data.dcache.ways = 4;
-                cpu_data->flags |= CPU_HAS_LLSC;
+                current_cpu_data.flags |= CPU_HAS_LLSC;
                break;
        case 0x3008:
                if (prr == 0xa0) {
-                        cpu_data->type = CPU_SH7722;
+                        current_cpu_data.type = CPU_SH7722;
-                        cpu_data->icache.ways = 4;
+                        current_cpu_data.icache.ways = 4;
-                        cpu_data->dcache.ways = 4;
+                        current_cpu_data.dcache.ways = 4;
-                        cpu_data->flags |= CPU_HAS_LLSC;
+                        current_cpu_data.flags |= CPU_HAS_LLSC;
                }
                break;
        case 0x8000:
-                cpu_data->type = CPU_ST40RA;
+                current_cpu_data.type = CPU_ST40RA;
-                cpu_data->flags |= CPU_HAS_FPU;
+                current_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x8100:
-                cpu_data->type = CPU_ST40GX1;
+                current_cpu_data.type = CPU_ST40GX1;
-                cpu_data->flags |= CPU_HAS_FPU;
+                current_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x700:
-                cpu_data->type = CPU_SH4_501;
+                current_cpu_data.type = CPU_SH4_501;
-                cpu_data->icache.ways = 2;
+                current_cpu_data.icache.ways = 2;
-                cpu_data->dcache.ways = 2;
+                current_cpu_data.dcache.ways = 2;
                break;
        case 0x600:
-                cpu_data->type = CPU_SH4_202;
+                current_cpu_data.type = CPU_SH4_202;
-                cpu_data->icache.ways = 2;
+                current_cpu_data.icache.ways = 2;
-                cpu_data->dcache.ways = 2;
+                current_cpu_data.dcache.ways = 2;
-                cpu_data->flags |= CPU_HAS_FPU;
+                current_cpu_data.flags |= CPU_HAS_FPU;
                break;
        case 0x500 ... 0x501:
                switch (prr) {
                case 0x10:
-                        cpu_data->type = CPU_SH7750R;
+                        current_cpu_data.type = CPU_SH7750R;
                        break;
                case 0x11:
-                        cpu_data->type = CPU_SH7751R;
+                        current_cpu_data.type = CPU_SH7751R;
                        break;
                case 0x50 ... 0x5f:
-                        cpu_data->type = CPU_SH7760;
+                        current_cpu_data.type = CPU_SH7760;
                        break;
                }
-                cpu_data->icache.ways = 2;
+                current_cpu_data.icache.ways = 2;
-                cpu_data->dcache.ways = 2;
+                current_cpu_data.dcache.ways = 2;
-                cpu_data->flags |= CPU_HAS_FPU;
+                current_cpu_data.flags |= CPU_HAS_FPU;
                break;
        default:
-                cpu_data->type = CPU_SH_NONE;
+                current_cpu_data.type = CPU_SH_NONE;
                break;
        }
 #ifdef CONFIG_SH_DIRECT_MAPPED
-        cpu_data->icache.ways = 1;
+        current_cpu_data.icache.ways = 1;
-        cpu_data->dcache.ways = 1;
+        current_cpu_data.dcache.ways = 1;
+#endif
+#ifdef CONFIG_CPU_HAS_PTEA
+        current_cpu_data.flags |= CPU_HAS_PTEA;
 #endif
        /*
         * On anything that's not a direct-mapped cache, look to the CVR
         * for I/D-cache specifics.
         */
-        if (cpu_data->icache.ways > 1) {
+        if (current_cpu_data.icache.ways > 1) {
                size = sizes[(cvr >> 20) & 0xf];
-                cpu_data->icache.way_incr       = (size >> 1);
+                current_cpu_data.icache.way_incr        = (size >> 1);
-                cpu_data->icache.sets           = (size >> 6);
+                current_cpu_data.icache.sets            = (size >> 6);
        }
        /* Setup the rest of the I-cache info */
-        cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
+        current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
-                                      cpu_data->icache.linesz;
+                                      current_cpu_data.icache.linesz;
-        cpu_data->icache.way_size = cpu_data->icache.sets *
+        current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
-                                    cpu_data->icache.linesz;
+                                    current_cpu_data.icache.linesz;
        /* And the rest of the D-cache */
-        if (cpu_data->dcache.ways > 1) {
+        if (current_cpu_data.dcache.ways > 1) {
                size = sizes[(cvr >> 16) & 0xf];
-                cpu_data->dcache.way_incr       = (size >> 1);
+                current_cpu_data.dcache.way_incr        = (size >> 1);
-                cpu_data->dcache.sets           = (size >> 6);
+                current_cpu_data.dcache.sets            = (size >> 6);
        }
-        cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
+        current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
-                                      cpu_data->dcache.linesz;
+                                      current_cpu_data.dcache.linesz;
-        cpu_data->dcache.way_size = cpu_data->dcache.sets *
+        current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
-                                    cpu_data->dcache.linesz;
+                                    current_cpu_data.dcache.linesz;
        /*
         * Setup the L2 cache desc
         *
         * SH-4A's have an optional PIPT L2.
         */
-        if (cpu_data->flags & CPU_HAS_L2_CACHE) {
+        if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
                /*
                 * Size calculation is much more sensible
                 * than it is for the L1.
@@ -228,16 +231,22 @@ int __init detect_cpu_and_cache_system(void)
                BUG_ON(!size);
-                cpu_data->scache.way_incr       = (1 << 16);
+                current_cpu_data.scache.way_incr        = (1 << 16);
-                cpu_data->scache.entry_shift    = 5;
+                current_cpu_data.scache.entry_shift     = 5;
-                cpu_data->scache.ways           = 4;
+                current_cpu_data.scache.ways            = 4;
-                cpu_data->scache.linesz         = L1_CACHE_BYTES;
+                current_cpu_data.scache.linesz          = L1_CACHE_BYTES;
-                cpu_data->scache.entry_mask     =
-                        (cpu_data->scache.way_incr - cpu_data->scache.linesz);
+                current_cpu_data.scache.entry_mask      =
-                cpu_data->scache.sets           = size /
+                        (current_cpu_data.scache.way_incr -
-                        (cpu_data->scache.linesz * cpu_data->scache.ways);
+                         current_cpu_data.scache.linesz);
-                cpu_data->scache.way_size       =
-                        (cpu_data->scache.sets * cpu_data->scache.linesz);
+                current_cpu_data.scache.sets            = size /
+                        (current_cpu_data.scache.linesz *
+                         current_cpu_data.scache.ways);
+                current_cpu_data.scache.way_size        =
+                        (current_cpu_data.scache.sets *
+                         current_cpu_data.scache.linesz);
        }
        return 0;

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index b26e2bc5894d..9d28c88d2f9d 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -10,11 +10,10 @@
10	* License. See the file "COPYING" in the main directory of this archive	10	* License. See the file "COPYING" in the main directory of this archive
11	* for more details.	11	* for more details.
12	*/	12	*/
13
14	#include <linux/init.h>	13	#include <linux/init.h>
		14	#include <linux/io.h>
15	#include <asm/processor.h>	15	#include <asm/processor.h>
16	#include <asm/cache.h>	16	#include <asm/cache.h>
17	#include <asm/io.h>
18		17
19	int __init detect_cpu_and_cache_system(void)	18	int __init detect_cpu_and_cache_system(void)
20	{	19	{
@@ -36,20 +35,20 @@ int __init detect_cpu_and_cache_system(void)
36	/*	35	/*
37	* Setup some sane SH-4 defaults for the icache	36	* Setup some sane SH-4 defaults for the icache
38	*/	37	*/
39	cpu_data->icache.way_incr = (1 << 13);	38	current_cpu_data.icache.way_incr = (1 << 13);
40	cpu_data->icache.entry_shift = 5;	39	current_cpu_data.icache.entry_shift = 5;
41	cpu_data->icache.sets = 256;	40	current_cpu_data.icache.sets = 256;
42	cpu_data->icache.ways = 1;	41	current_cpu_data.icache.ways = 1;
43	cpu_data->icache.linesz = L1_CACHE_BYTES;	42	current_cpu_data.icache.linesz = L1_CACHE_BYTES;
44		43
45	/*	44	/*
46	* And again for the dcache ..	45	* And again for the dcache ..
47	*/	46	*/
48	cpu_data->dcache.way_incr = (1 << 14);	47	current_cpu_data.dcache.way_incr = (1 << 14);
49	cpu_data->dcache.entry_shift = 5;	48	current_cpu_data.dcache.entry_shift = 5;
50	cpu_data->dcache.sets = 512;	49	current_cpu_data.dcache.sets = 512;
51	cpu_data->dcache.ways = 1;	50	current_cpu_data.dcache.ways = 1;
52	cpu_data->dcache.linesz = L1_CACHE_BYTES;	51	current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53		52
54	/*	53	/*
55	* Setup some generic flags we can probe	54	* Setup some generic flags we can probe
@@ -57,16 +56,16 @@ int __init detect_cpu_and_cache_system(void)
57	*/	56	*/
58	if (((pvr >> 16) & 0xff) == 0x10) {	57	if (((pvr >> 16) & 0xff) == 0x10) {
59	if ((cvr & 0x02000000) == 0)	58	if ((cvr & 0x02000000) == 0)
60	cpu_data->flags \|= CPU_HAS_L2_CACHE;	59	current_cpu_data.flags \|= CPU_HAS_L2_CACHE;
61	if ((cvr & 0x10000000) == 0)	60	if ((cvr & 0x10000000) == 0)
62	cpu_data->flags \|= CPU_HAS_DSP;	61	current_cpu_data.flags \|= CPU_HAS_DSP;
63		62
64	cpu_data->flags \|= CPU_HAS_LLSC;	63	current_cpu_data.flags \|= CPU_HAS_LLSC;
65	}	64	}
66		65
67	/* FPU detection works for everyone */	66	/* FPU detection works for everyone */
68	if ((cvr & 0x20000000) == 1)	67	if ((cvr & 0x20000000) == 1)
69	cpu_data->flags \|= CPU_HAS_FPU;	68	current_cpu_data.flags \|= CPU_HAS_FPU;
70		69
71	/* Mask off the upper chip ID */	70	/* Mask off the upper chip ID */
72	pvr &= 0xffff;	71	pvr &= 0xffff;
@@ -77,147 +76,151 @@ int __init detect_cpu_and_cache_system(void)
77	*/	76	*/
78	switch (pvr) {	77	switch (pvr) {
79	case 0x205:	78	case 0x205:
80	cpu_data->type = CPU_SH7750;	79	current_cpu_data.type = CPU_SH7750;
81	cpu_data->flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_FPU \|	80	current_cpu_data.flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_FPU \|
82	CPU_HAS_PERF_COUNTER;	81	CPU_HAS_PERF_COUNTER;
83	break;	82	break;
84	case 0x206:	83	case 0x206:
85	cpu_data->type = CPU_SH7750S;	84	current_cpu_data.type = CPU_SH7750S;
86	cpu_data->flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_FPU \|	85	current_cpu_data.flags \|= CPU_HAS_P2_FLUSH_BUG \| CPU_HAS_FPU \|
87	CPU_HAS_PERF_COUNTER;	86	CPU_HAS_PERF_COUNTER;
88	break;	87	break;
89	case 0x1100:	88	case 0x1100:
90	cpu_data->type = CPU_SH7751;	89	current_cpu_data.type = CPU_SH7751;
91	cpu_data->flags \|= CPU_HAS_FPU;	90	current_cpu_data.flags \|= CPU_HAS_FPU;
92	break;	91	break;
93	case 0x2000:	92	case 0x2000:
94	cpu_data->type = CPU_SH73180;	93	current_cpu_data.type = CPU_SH73180;
95	cpu_data->icache.ways = 4;	94	current_cpu_data.icache.ways = 4;
96	cpu_data->dcache.ways = 4;	95	current_cpu_data.dcache.ways = 4;
97	cpu_data->flags \|= CPU_HAS_LLSC;	96	current_cpu_data.flags \|= CPU_HAS_LLSC;
98	break;	97	break;
99	case 0x2001:	98	case 0x2001:
100	case 0x2004:	99	case 0x2004:
101	cpu_data->type = CPU_SH7770;	100	current_cpu_data.type = CPU_SH7770;
102	cpu_data->icache.ways = 4;	101	current_cpu_data.icache.ways = 4;
103	cpu_data->dcache.ways = 4;	102	current_cpu_data.dcache.ways = 4;
104		103
105	cpu_data->flags \|= CPU_HAS_FPU \| CPU_HAS_LLSC;	104	current_cpu_data.flags \|= CPU_HAS_FPU \| CPU_HAS_LLSC;
106	break;	105	break;
107	case 0x2006:	106	case 0x2006:
108	case 0x200A:	107	case 0x200A:
109	if (prr == 0x61)	108	if (prr == 0x61)
110	cpu_data->type = CPU_SH7781;	109	current_cpu_data.type = CPU_SH7781;
111	else	110	else
112	cpu_data->type = CPU_SH7780;	111	current_cpu_data.type = CPU_SH7780;
113		112
114	cpu_data->icache.ways = 4;	113	current_cpu_data.icache.ways = 4;
115	cpu_data->dcache.ways = 4;	114	current_cpu_data.dcache.ways = 4;
116		115
117	cpu_data->flags \|= CPU_HAS_FPU \| CPU_HAS_PERF_COUNTER \|	116	current_cpu_data.flags \|= CPU_HAS_FPU \| CPU_HAS_PERF_COUNTER \|
118	CPU_HAS_LLSC;	117	CPU_HAS_LLSC;
119	break;	118	break;
120	case 0x3000:	119	case 0x3000:
121	case 0x3003:	120	case 0x3003:
122	case 0x3009:	121	case 0x3009:
123	cpu_data->type = CPU_SH7343;	122	current_cpu_data.type = CPU_SH7343;
124	cpu_data->icache.ways = 4;	123	current_cpu_data.icache.ways = 4;
125	cpu_data->dcache.ways = 4;	124	current_cpu_data.dcache.ways = 4;
126	cpu_data->flags \|= CPU_HAS_LLSC;	125	current_cpu_data.flags \|= CPU_HAS_LLSC;
127	break;	126	break;
128	case 0x3008:	127	case 0x3008:
129	if (prr == 0xa0) {	128	if (prr == 0xa0) {
130	cpu_data->type = CPU_SH7722;	129	current_cpu_data.type = CPU_SH7722;
131	cpu_data->icache.ways = 4;	130	current_cpu_data.icache.ways = 4;
132	cpu_data->dcache.ways = 4;	131	current_cpu_data.dcache.ways = 4;
133	cpu_data->flags \|= CPU_HAS_LLSC;	132	current_cpu_data.flags \|= CPU_HAS_LLSC;
134	}	133	}
135	break;	134	break;
136	case 0x8000:	135	case 0x8000:
137	cpu_data->type = CPU_ST40RA;	136	current_cpu_data.type = CPU_ST40RA;
138	cpu_data->flags \|= CPU_HAS_FPU;	137	current_cpu_data.flags \|= CPU_HAS_FPU;
139	break;	138	break;
140	case 0x8100:	139	case 0x8100:
141	cpu_data->type = CPU_ST40GX1;	140	current_cpu_data.type = CPU_ST40GX1;
142	cpu_data->flags \|= CPU_HAS_FPU;	141	current_cpu_data.flags \|= CPU_HAS_FPU;
143	break;	142	break;
144	case 0x700:	143	case 0x700:
145	cpu_data->type = CPU_SH4_501;	144	current_cpu_data.type = CPU_SH4_501;
146	cpu_data->icache.ways = 2;	145	current_cpu_data.icache.ways = 2;
147	cpu_data->dcache.ways = 2;	146	current_cpu_data.dcache.ways = 2;
148	break;	147	break;
149	case 0x600:	148	case 0x600:
150	cpu_data->type = CPU_SH4_202;	149	current_cpu_data.type = CPU_SH4_202;
151	cpu_data->icache.ways = 2;	150	current_cpu_data.icache.ways = 2;
152	cpu_data->dcache.ways = 2;	151	current_cpu_data.dcache.ways = 2;
153	cpu_data->flags \|= CPU_HAS_FPU;	152	current_cpu_data.flags \|= CPU_HAS_FPU;
154	break;	153	break;
155	case 0x500 ... 0x501:	154	case 0x500 ... 0x501:
156	switch (prr) {	155	switch (prr) {
157	case 0x10:	156	case 0x10:
158	cpu_data->type = CPU_SH7750R;	157	current_cpu_data.type = CPU_SH7750R;
159	break;	158	break;
160	case 0x11:	159	case 0x11:
161	cpu_data->type = CPU_SH7751R;	160	current_cpu_data.type = CPU_SH7751R;
162	break;	161	break;
163	case 0x50 ... 0x5f:	162	case 0x50 ... 0x5f:
164	cpu_data->type = CPU_SH7760;	163	current_cpu_data.type = CPU_SH7760;
165	break;	164	break;
166	}	165	}
167		166
168	cpu_data->icache.ways = 2;	167	current_cpu_data.icache.ways = 2;
169	cpu_data->dcache.ways = 2;	168	current_cpu_data.dcache.ways = 2;
170		169
171	cpu_data->flags \|= CPU_HAS_FPU;	170	current_cpu_data.flags \|= CPU_HAS_FPU;
172		171
173	break;	172	break;
174	default:	173	default:
175	cpu_data->type = CPU_SH_NONE;	174	current_cpu_data.type = CPU_SH_NONE;
176	break;	175	break;
177	}	176	}
178		177
179	#ifdef CONFIG_SH_DIRECT_MAPPED	178	#ifdef CONFIG_SH_DIRECT_MAPPED
180	cpu_data->icache.ways = 1;	179	current_cpu_data.icache.ways = 1;
181	cpu_data->dcache.ways = 1;	180	current_cpu_data.dcache.ways = 1;
		181	#endif
		182
		183	#ifdef CONFIG_CPU_HAS_PTEA
		184	current_cpu_data.flags \|= CPU_HAS_PTEA;
182	#endif	185	#endif
183		186
184	/*	187	/*
185	* On anything that's not a direct-mapped cache, look to the CVR	188	* On anything that's not a direct-mapped cache, look to the CVR
186	* for I/D-cache specifics.	189	* for I/D-cache specifics.
187	*/	190	*/
188	if (cpu_data->icache.ways > 1) {	191	if (current_cpu_data.icache.ways > 1) {
189	size = sizes[(cvr >> 20) & 0xf];	192	size = sizes[(cvr >> 20) & 0xf];
190	cpu_data->icache.way_incr = (size >> 1);	193	current_cpu_data.icache.way_incr = (size >> 1);
191	cpu_data->icache.sets = (size >> 6);	194	current_cpu_data.icache.sets = (size >> 6);
192		195
193	}	196	}
194		197
195	/* Setup the rest of the I-cache info */	198	/* Setup the rest of the I-cache info */
196	cpu_data->icache.entry_mask = cpu_data->icache.way_incr -	199	current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
197	cpu_data->icache.linesz;	200	current_cpu_data.icache.linesz;
198		201
199	cpu_data->icache.way_size = cpu_data->icache.sets *	202	current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
200	cpu_data->icache.linesz;	203	current_cpu_data.icache.linesz;
201		204
202	/* And the rest of the D-cache */	205	/* And the rest of the D-cache */
203	if (cpu_data->dcache.ways > 1) {	206	if (current_cpu_data.dcache.ways > 1) {
204	size = sizes[(cvr >> 16) & 0xf];	207	size = sizes[(cvr >> 16) & 0xf];
205	cpu_data->dcache.way_incr = (size >> 1);	208	current_cpu_data.dcache.way_incr = (size >> 1);
206	cpu_data->dcache.sets = (size >> 6);	209	current_cpu_data.dcache.sets = (size >> 6);
207	}	210	}
208		211
209	cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -	212	current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
210	cpu_data->dcache.linesz;	213	current_cpu_data.dcache.linesz;
211		214
212	cpu_data->dcache.way_size = cpu_data->dcache.sets *	215	current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
213	cpu_data->dcache.linesz;	216	current_cpu_data.dcache.linesz;
214		217
215	/*	218	/*
216	* Setup the L2 cache desc	219	* Setup the L2 cache desc
217	*	220	*
218	* SH-4A's have an optional PIPT L2.	221	* SH-4A's have an optional PIPT L2.
219	*/	222	*/
220	if (cpu_data->flags & CPU_HAS_L2_CACHE) {	223	if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
221	/*	224	/*
222	* Size calculation is much more sensible	225	* Size calculation is much more sensible
223	* than it is for the L1.	226	* than it is for the L1.
@@ -228,16 +231,22 @@ int __init detect_cpu_and_cache_system(void)
228		231
229	BUG_ON(!size);	232	BUG_ON(!size);
230		233
231	cpu_data->scache.way_incr = (1 << 16);	234	current_cpu_data.scache.way_incr = (1 << 16);
232	cpu_data->scache.entry_shift = 5;	235	current_cpu_data.scache.entry_shift = 5;
233	cpu_data->scache.ways = 4;	236	current_cpu_data.scache.ways = 4;
234	cpu_data->scache.linesz = L1_CACHE_BYTES;	237	current_cpu_data.scache.linesz = L1_CACHE_BYTES;
235	cpu_data->scache.entry_mask =	238
236	(cpu_data->scache.way_incr - cpu_data->scache.linesz);	239	current_cpu_data.scache.entry_mask =
237	cpu_data->scache.sets = size /	240	(current_cpu_data.scache.way_incr -
238	(cpu_data->scache.linesz * cpu_data->scache.ways);	241	current_cpu_data.scache.linesz);
239	cpu_data->scache.way_size =	242
240	(cpu_data->scache.sets * cpu_data->scache.linesz);	243	current_cpu_data.scache.sets = size /
		244	(current_cpu_data.scache.linesz *
		245	current_cpu_data.scache.ways);
		246
		247	current_cpu_data.scache.way_size =
		248	(current_cpu_data.scache.sets *
		249	current_cpu_data.scache.linesz);
241	}	250	}
242		251
243	return 0;	252	return 0;