diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4/clock-sh4-202.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4/clock-sh4-202.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c index a33429463e96..628d50ea6f6b 100644 --- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c | |||
@@ -21,10 +21,10 @@ | |||
21 | static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; | 21 | static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; |
22 | static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; | 22 | static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; |
23 | 23 | ||
24 | static void emi_clk_recalc(struct clk *clk) | 24 | static unsigned long emi_clk_recalc(struct clk *clk) |
25 | { | 25 | { |
26 | int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; | 26 | int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; |
27 | clk->rate = clk->parent->rate / frqcr3_divisors[idx]; | 27 | return clk->parent->rate / frqcr3_divisors[idx]; |
28 | } | 28 | } |
29 | 29 | ||
30 | static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) | 30 | static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) |
@@ -50,10 +50,10 @@ static struct clk sh4202_emi_clk = { | |||
50 | .ops = &sh4202_emi_clk_ops, | 50 | .ops = &sh4202_emi_clk_ops, |
51 | }; | 51 | }; |
52 | 52 | ||
53 | static void femi_clk_recalc(struct clk *clk) | 53 | static unsigned long femi_clk_recalc(struct clk *clk) |
54 | { | 54 | { |
55 | int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; | 55 | int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; |
56 | clk->rate = clk->parent->rate / frqcr3_divisors[idx]; | 56 | return clk->parent->rate / frqcr3_divisors[idx]; |
57 | } | 57 | } |
58 | 58 | ||
59 | static struct clk_ops sh4202_femi_clk_ops = { | 59 | static struct clk_ops sh4202_femi_clk_ops = { |
@@ -90,10 +90,10 @@ static void shoc_clk_init(struct clk *clk) | |||
90 | WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ | 90 | WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ |
91 | } | 91 | } |
92 | 92 | ||
93 | static void shoc_clk_recalc(struct clk *clk) | 93 | static unsigned long shoc_clk_recalc(struct clk *clk) |
94 | { | 94 | { |
95 | int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; | 95 | int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; |
96 | clk->rate = clk->parent->rate / frqcr3_divisors[idx]; | 96 | return clk->parent->rate / frqcr3_divisors[idx]; |
97 | } | 97 | } |
98 | 98 | ||
99 | static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) | 99 | static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) |
@@ -127,7 +127,7 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id) | |||
127 | frqcr3 |= tmp << 6; | 127 | frqcr3 |= tmp << 6; |
128 | ctrl_outl(frqcr3, CPG2_FRQCR3); | 128 | ctrl_outl(frqcr3, CPG2_FRQCR3); |
129 | 129 | ||
130 | clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; | 130 | return clk->parent->rate / frqcr3_divisors[tmp]; |
131 | 131 | ||
132 | return 0; | 132 | return 0; |
133 | } | 133 | } |