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-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile6
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S199
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c97
3 files changed, 302 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
new file mode 100644
index 000000000000..a64532e4dc63
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the Linux/SuperH SH-3 backends.
3#
4
5obj-y := ex.o probe.o
6
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
new file mode 100644
index 000000000000..966c0858b714
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -0,0 +1,199 @@
1/*
2 * arch/sh/kernel/cpu/sh3/ex.S
3 *
4 * The SH-3 exception vector table.
5
6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
7 * Copyright (C) 2003 Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 *
13 */
14#include <linux/linkage.h>
15#include <linux/config.h>
16
17 .align 2
18 .data
19
20ENTRY(exception_handling_table)
21 .long exception_error /* 000 */
22 .long exception_error
23#if defined(CONFIG_MMU)
24 .long tlb_miss_load /* 040 */
25 .long tlb_miss_store
26 .long initial_page_write
27 .long tlb_protection_violation_load
28 .long tlb_protection_violation_store
29 .long address_error_load
30 .long address_error_store /* 100 */
31#else
32 .long exception_error ! tlb miss load /* 040 */
33 .long exception_error ! tlb miss store
34 .long exception_error ! initial page write
35 .long exception_error ! tlb prot violation load
36 .long exception_error ! tlb prot violation store
37 .long exception_error ! address error load
38 .long exception_error ! address error store /* 100 */
39#endif
40 .long exception_error ! fpu_exception /* 120 */
41 .long exception_error /* 140 */
42 .long system_call ! Unconditional Trap /* 160 */
43 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
44 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
45ENTRY(nmi_slot)
46#if defined (CONFIG_KGDB_NMI)
47 .long debug_enter /* 1C0 */ ! Allow trap to debugger
48#else
49 .long exception_none /* 1C0 */ ! Not implemented yet
50#endif
51ENTRY(user_break_point_trap)
52 .long break_point_trap /* 1E0 */
53ENTRY(interrupt_table)
54 ! external hardware
55 .long do_IRQ ! 0000 /* 200 */
56 .long do_IRQ ! 0001
57 .long do_IRQ ! 0010
58 .long do_IRQ ! 0011
59 .long do_IRQ ! 0100
60 .long do_IRQ ! 0101
61 .long do_IRQ ! 0110
62 .long do_IRQ ! 0111
63 .long do_IRQ ! 1000 /* 300 */
64 .long do_IRQ ! 1001
65 .long do_IRQ ! 1010
66 .long do_IRQ ! 1011
67 .long do_IRQ ! 1100
68 .long do_IRQ ! 1101
69 .long do_IRQ ! 1110
70 .long exception_error
71 ! Internal hardware
72 .long do_IRQ ! TMU0 tuni0 /* 400 */
73 .long do_IRQ ! TMU1 tuni1
74 .long do_IRQ ! TMU2 tuni2
75 .long do_IRQ ! ticpi2
76 .long do_IRQ ! RTC ati
77 .long do_IRQ ! pri
78 .long do_IRQ ! cui
79 .long do_IRQ ! SCI eri
80 .long do_IRQ ! rxi /* 500 */
81 .long do_IRQ ! txi
82 .long do_IRQ ! tei
83 .long do_IRQ ! WDT iti /* 560 */
84 .long do_IRQ ! REF rcmi
85 .long do_IRQ ! rovi
86 .long do_IRQ
87 .long do_IRQ /* 5E0 */
88#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
89 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
90 .long do_IRQ ! 32 IRQ irq0 /* 600 */
91 .long do_IRQ ! 33 irq1
92 .long do_IRQ ! 34 irq2
93 .long do_IRQ ! 35 irq3
94 .long do_IRQ ! 36 irq4
95 .long do_IRQ ! 37 irq5
96 .long do_IRQ ! 38
97 .long do_IRQ ! 39
98 .long do_IRQ ! 40 PINT pint0-7 /* 700 */
99 .long do_IRQ ! 41 pint8-15
100 .long do_IRQ ! 42
101 .long do_IRQ ! 43
102 .long do_IRQ ! 44
103 .long do_IRQ ! 45
104 .long do_IRQ ! 46
105 .long do_IRQ ! 47
106 .long do_IRQ ! 48 DMAC dei0 /* 800 */
107 .long do_IRQ ! 49 dei1
108 .long do_IRQ ! 50 dei2
109 .long do_IRQ ! 51 dei3
110 .long do_IRQ ! 52 IrDA eri1
111 .long do_IRQ ! 53 rxi1
112 .long do_IRQ ! 54 bri1
113 .long do_IRQ ! 55 txi1
114 .long do_IRQ ! 56 SCIF eri2
115 .long do_IRQ ! 57 rxi2
116 .long do_IRQ ! 58 bri2
117 .long do_IRQ ! 59 txi2
118 .long do_IRQ ! 60 ADC adi /* 980 */
119#if defined(CONFIG_CPU_SUBTYPE_SH7705)
120 .long exception_none ! 61 /* 9A0 */
121 .long exception_none ! 62
122 .long exception_none ! 63
123 .long exception_none ! 64 /* A00 */
124 .long do_IRQ ! 65 USB usi0
125 .long do_IRQ ! 66 usi1
126 .long exception_none ! 67
127 .long exception_none ! 68
128 .long exception_none ! 69
129 .long exception_none ! 70
130 .long exception_none ! 71
131 .long exception_none ! 72 /* B00 */
132 .long exception_none ! 73
133 .long exception_none ! 74
134 .long exception_none ! 75
135 .long exception_none ! 76
136 .long exception_none ! 77
137 .long exception_none ! 78
138 .long exception_none ! 79
139 .long do_IRQ ! 80 TPU0 tpi0 /* C00 */
140 .long do_IRQ ! 81 TPU1 tpi1
141 .long exception_none ! 82
142 .long exception_none ! 83
143 .long do_IRQ ! 84 TPU2 tpi2
144 .long do_IRQ ! 85 TPU3 tpi3 /* CA0 */
145#endif
146#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7300)
147 .long do_IRQ ! 61 LCDC lcdi /* 9A0 */
148 .long do_IRQ ! 62 PCC pcc0i
149 .long do_IRQ ! 63 pcc1i /* 9E0 */
150#endif
151#if defined(CONFIG_CPU_SUBTYPE_SH7300)
152 .long do_IRQ ! 64
153 .long do_IRQ ! 65
154 .long do_IRQ ! 66
155 .long do_IRQ ! 67
156 .long do_IRQ ! 68
157 .long do_IRQ ! 69
158 .long do_IRQ ! 70
159 .long do_IRQ ! 71
160 .long do_IRQ ! 72
161 .long do_IRQ ! 73
162 .long do_IRQ ! 74
163 .long do_IRQ ! 75
164 .long do_IRQ ! 76
165 .long do_IRQ ! 77
166 .long do_IRQ ! 78
167 .long do_IRQ ! 79
168 .long do_IRQ ! 80 SCIF0(SH7300)
169 .long do_IRQ ! 81
170 .long do_IRQ ! 82
171 .long do_IRQ ! 83
172 .long do_IRQ ! 84
173 .long do_IRQ ! 85
174 .long do_IRQ ! 86
175 .long do_IRQ ! 87
176 .long do_IRQ ! 88
177 .long do_IRQ ! 89
178 .long do_IRQ ! 90
179 .long do_IRQ ! 91
180 .long do_IRQ ! 92
181 .long do_IRQ ! 93
182 .long do_IRQ ! 94
183 .long do_IRQ ! 95
184 .long do_IRQ ! 96
185 .long do_IRQ ! 97
186 .long do_IRQ ! 98
187 .long do_IRQ ! 99
188 .long do_IRQ ! 100
189 .long do_IRQ ! 101
190 .long do_IRQ ! 102
191 .long do_IRQ ! 103
192 .long do_IRQ ! 104
193 .long do_IRQ ! 105
194 .long do_IRQ ! 106
195 .long do_IRQ ! 107
196 .long do_IRQ ! 108
197#endif
198#endif
199
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
new file mode 100644
index 000000000000..5cdc88638601
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -0,0 +1,97 @@
1/*
2 * arch/sh/kernel/cpu/sh3/probe.c
3 *
4 * CPU Subtype Probing for SH-3.
5 *
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2002 Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/init.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/io.h>
18
19int __init detect_cpu_and_cache_system(void)
20{
21 unsigned long addr0, addr1, data0, data1, data2, data3;
22
23 jump_to_P2();
24 /*
25 * Check if the entry shadows or not.
26 * When shadowed, it's 128-entry system.
27 * Otherwise, it's 256-entry system.
28 */
29 addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
31
32 /* First, write back & invalidate */
33 data0 = ctrl_inl(addr0);
34 ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
35 data1 = ctrl_inl(addr1);
36 ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
37
38 /* Next, check if there's shadow or not */
39 data0 = ctrl_inl(addr0);
40 data0 ^= SH_CACHE_VALID;
41 ctrl_outl(data0, addr0);
42 data1 = ctrl_inl(addr1);
43 data2 = data1 ^ SH_CACHE_VALID;
44 ctrl_outl(data2, addr1);
45 data3 = ctrl_inl(addr0);
46
47 /* Lastly, invaliate them. */
48 ctrl_outl(data0&~SH_CACHE_VALID, addr0);
49 ctrl_outl(data2&~SH_CACHE_VALID, addr1);
50
51 back_to_P1();
52
53 cpu_data->dcache.ways = 4;
54 cpu_data->dcache.entry_shift = 4;
55 cpu_data->dcache.linesz = L1_CACHE_BYTES;
56 cpu_data->dcache.flags = 0;
57
58 /*
59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60 * 2K(direct) 7702 is not supported (yet)
61 */
62 if (data0 == data1 && data2 == data3) { /* Shadow */
63 cpu_data->dcache.way_incr = (1 << 11);
64 cpu_data->dcache.entry_mask = 0x7f0;
65 cpu_data->dcache.sets = 128;
66 cpu_data->type = CPU_SH7708;
67
68 cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC;
69 } else { /* 7709A or 7729 */
70 cpu_data->dcache.way_incr = (1 << 12);
71 cpu_data->dcache.entry_mask = 0xff0;
72 cpu_data->dcache.sets = 256;
73 cpu_data->type = CPU_SH7729;
74
75#if defined(CONFIG_CPU_SUBTYPE_SH7705)
76 cpu_data->type = CPU_SH7705;
77
78#if defined(CONFIG_SH7705_CACHE_32KB)
79 cpu_data->dcache.way_incr = (1 << 13);
80 cpu_data->dcache.entry_mask = 0x1ff0;
81 cpu_data->dcache.sets = 512;
82 ctrl_outl(CCR_CACHE_32KB, CCR3);
83#else
84 ctrl_outl(CCR_CACHE_16KB, CCR3);
85#endif
86#endif
87 }
88
89 /*
90 * SH-3 doesn't have separate caches
91 */
92 cpu_data->dcache.flags |= SH_CACHE_COMBINED;
93 cpu_data->icache = cpu_data->dcache;
94
95 return 0;
96}
97
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