5 files changed, 133 insertions, 14 deletions

diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 83905e4e4387..09faa056cd43 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7708)	+= setup-sh7708.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7709)        += setup-sh7709.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7300)        += setup-sh7300.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7710)        += setup-sh7710.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7712)        += setup-sh7710.o
 
 # Primary on-chip clocks (common)
 clock-$(CONFIG_CPU_SH3)                 := clock-sh3.o
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 821b0ab7b528..647623b22edc 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -78,6 +78,9 @@ int __init detect_cpu_and_cache_system(void)
 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
                 current_cpu_data.type = CPU_SH7710;
 #endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7712)
+                current_cpu_data.type = CPU_SH7712;
+#endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
                 current_cpu_data.type = CPU_SH7705;
 
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index a8e41c5241fa..1983fb7ad6ea 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -2,6 +2,7 @@
  * SH7705 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2007  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -14,15 +15,15 @@
 
 static struct plat_sci_port sci_platform_data[] = {
         {
-                .mapbase        = 0xa4400000,
+                .mapbase        = 0xa4410000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
-                .irqs           = { 52, 53, 55, 54 },
+                .irqs           = { 56, 57, 59 },
         }, {
-                .mapbase        = 0xa4410000,
+                .mapbase        = 0xa4400000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
-                .irqs           = { 56, 57, 59, 58 },
+                .irqs           = { 52, 53, 55 },
         }, {
                 .flags = 0,
         }
@@ -46,3 +47,48 @@ static int __init sh7705_devices_setup(void)
                                     ARRAY_SIZE(sh7705_devices));
 }
 __initcall(sh7705_devices_setup);
+
+static struct ipr_data sh7705_ipr_map[] = {
+        /* IRQ, IPR-idx, shift, priority */
+        { 16, 0, 12, 2 }, /* TMU0 TUNI*/
+        { 17, 0,  8, 2 }, /* TMU1 TUNI */
+        { 18, 0,  4, 2 }, /* TMU2 TUNI */
+        { 27, 1, 12, 2 }, /* WDT ITI */
+        { 20, 0,  0, 2 }, /* RTC ATI (alarm) */
+        { 21, 0,  0, 2 }, /* RTC PRI (period) */
+        { 22, 0,  0, 2 }, /* RTC CUI (carry) */
+        { 48, 4, 12, 7 }, /* DMAC DMTE0 */
+        { 49, 4, 12, 7 }, /* DMAC DMTE1 */
+        { 50, 4, 12, 7 }, /* DMAC DMTE2 */
+        { 51, 4, 12, 7 }, /* DMAC DMTE3 */
+        { 52, 4,  8, 3 }, /* SCIF0 ERI */
+        { 53, 4,  8, 3 }, /* SCIF0 RXI */
+        { 55, 4,  8, 3 }, /* SCIF0 TXI */
+        { 56, 4,  4, 3 }, /* SCIF1 ERI */
+        { 57, 4,  4, 3 }, /* SCIF1 RXI */
+        { 59, 4,  4, 3 }, /* SCIF1 TXI */
+};
+
+static unsigned long ipr_offsets[] = {
+        0xFFFFFEE2      /* 0: IPRA */
+,       0xFFFFFEE4      /* 1: IPRB */
+,       0xA4000016      /* 2: IPRC */
+,       0xA4000018      /* 3: IPRD */
+,       0xA400001A      /* 4: IPRE */
+,       0xA4080000      /* 5: IPRF */
+,       0xA4080002      /* 6: IPRG */
+,       0xA4080004      /* 7: IPRH */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+        if (idx >= ARRAY_SIZE(ipr_offsets))
+                return 0;
+        return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+        make_ipr_irq(sh7705_ipr_map, ARRAY_SIZE(sh7705_ipr_map));
+}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
index dc9b211cf87f..c7d7c35fc834 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
@@ -48,24 +48,33 @@ static struct platform_device *sh7709_devices[] __initdata = {
 static int __init sh7709_devices_setup(void)
 {
         return platform_add_devices(sh7709_devices,
-                                    ARRAY_SIZE(sh7709_devices));
+                ARRAY_SIZE(sh7709_devices));
 }
 __initcall(sh7709_devices_setup);
 
-#define IPRx(A,N) .addr=A, .shift=0*N*-1
+#define IPRx(A,N)       .addr=A, .shift=N
 #define IPRA(N) IPRx(0xfffffee2UL,N)
 #define IPRB(N) IPRx(0xfffffee4UL,N)
+#define IPRC(N) IPRx(0xa4000016UL,N)
+#define IPRD(N) IPRx(0xa4000018UL,N)
 #define IPRE(N) IPRx(0xa400001aUL,N)
 
 static struct ipr_data sh7709_ipr_map[] = {
-        [16]            = { IPRA(15-12), 2 }, /* TMU TUNI0 */
-        [17]            = { IPRA(11-8),  4 }, /* TMU TUNI1 */
-        [22]            = { IPRA(3-0),   2 }, /* RTC CUI */
-        [23 ... 26]     = { IPRB(7-4),   3 }, /* SCI */
-        [27]            = { IPRB(15-12), 2 }, /* WDT ITI */
-        [48 ... 51]     = { IPRE(15-12), 7 }, /* DMA */
-        [52 ... 55]     = { IPRE(11-8),  3 }, /* IRDA */
-        [56 ... 59]     = { IPRE(7-4),   3 }, /* SCIF */
+        [16]            = { IPRA(12), 2 }, /* TMU TUNI0 */
+        [17]            = { IPRA(8),  4 }, /* TMU TUNI1 */
+        [18 ... 19]     = { IPRA(4),  1 }, /* TMU TUNI1 */
+        [20 ... 22]     = { IPRA(0),  2 }, /* RTC CUI */
+        [23 ... 26]     = { IPRB(4),  3 }, /* SCI */
+        [27]            = { IPRB(12), 2 }, /* WDT ITI */
+        [32]            = { IPRC(0),  1 }, /* IRQ 0 */
+        [33]            = { IPRC(4),  1 }, /* IRQ 1 */
+        [34]            = { IPRC(8),  1 }, /* IRQ 2 APM */
+        [35]            = { IPRC(12), 1 }, /* IRQ 3 TOUCHSCREEN */
+        [36]            = { IPRD(0),  1 }, /* IRQ 4 */
+        [37]            = { IPRD(4),  1 }, /* IRQ 5 */
+        [48 ... 51]     = { IPRE(12), 7 }, /* DMA */
+        [52 ... 55]     = { IPRE(8),  3 }, /* IRDA */
+        [56 ... 59]     = { IPRE(4),  3 }, /* SCIF */
 };
 
 void __init init_IRQ_ipr()
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 895f99ee6a95..51760a7e7f1c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -2,6 +2,7 @@
  * SH7710 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2007  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -19,6 +20,12 @@ static struct plat_sci_port sci_platform_data[] = {
                 .type           = PORT_SCIF,
                 .irqs           = { 52, 53, 55, 54 },
         }, {
+                .mapbase        = 0xa4420000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 56, 57, 59, 58 },
+        }, {
+
                 .flags = 0,
         }
 };
@@ -41,3 +48,56 @@ static int __init sh7710_devices_setup(void)
                                     ARRAY_SIZE(sh7710_devices));
 }
 __initcall(sh7710_devices_setup);
+
+static struct ipr_data sh7710_ipr_map[] = {
+        /* IRQ, IPR-idx, shift, priority */
+        { 16, 0, 12, 2 }, /* TMU0 TUNI*/
+        { 17, 0,  8, 2 }, /* TMU1 TUNI */
+        { 18, 0,  4, 2 }, /* TMU2 TUNI */
+        { 27, 1, 12, 2 }, /* WDT ITI */
+        { 20, 0,  0, 2 }, /* RTC ATI (alarm) */
+        { 21, 0,  0, 2 }, /* RTC PRI (period) */
+        { 22, 0,  0, 2 }, /* RTC CUI (carry) */
+        { 48, 4, 12, 7 }, /* DMAC DMTE0 */
+        { 49, 4, 12, 7 }, /* DMAC DMTE1 */
+        { 50, 4, 12, 7 }, /* DMAC DMTE2 */
+        { 51, 4, 12, 7 }, /* DMAC DMTE3 */
+        { 52, 4,  8, 3 }, /* SCIF0 ERI */
+        { 53, 4,  8, 3 }, /* SCIF0 RXI */
+        { 54, 4,  8, 3 }, /* SCIF0 BRI */
+        { 55, 4,  8, 3 }, /* SCIF0 TXI */
+        { 56, 4,  4, 3 }, /* SCIF1 ERI */
+        { 57, 4,  4, 3 }, /* SCIF1 RXI */
+        { 58, 4,  4, 3 }, /* SCIF1 BRI */
+        { 59, 4,  4, 3 }, /* SCIF1 TXI */
+        { 76, 5,  8, 7 }, /* DMAC DMTE4 */
+        { 77, 5,  8, 7 }, /* DMAC DMTE5 */
+        { 80, 6, 12, 5 }, /* EDMAC EINT0 */
+        { 81, 6,  8, 5 }, /* EDMAC EINT1 */
+        { 82, 6,  4, 5 }, /* EDMAC EINT2 */
+};
+
+static unsigned long ipr_offsets[] = {
+        0xA414FEE2      /* 0: IPRA */
+,       0xA414FEE4      /* 1: IPRB */
+,       0xA4140016      /* 2: IPRC */
+,       0xA4140018      /* 3: IPRD */
+,       0xA414001A      /* 4: IPRE */
+,       0xA4080000      /* 5: IPRF */
+,       0xA4080002      /* 6: IPRG */
+,       0xA4080004      /* 7: IPRH */
+,       0xA4080006      /* 8: IPRI */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+        if (idx >= ARRAY_SIZE(ipr_offsets))
+                return 0;
+        return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+        make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map));
+}