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Diffstat (limited to 'arch/sh/kernel/cpu/sh3/probe.c')
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index c2db65719f4d..295ec4c99e98 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -30,23 +30,23 @@ int detect_cpu_and_cache_system(void)
30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12); 30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
31 31
32 /* First, write back & invalidate */ 32 /* First, write back & invalidate */
33 data0 = ctrl_inl(addr0); 33 data0 = __raw_readl(addr0);
34 ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); 34 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
35 data1 = ctrl_inl(addr1); 35 data1 = __raw_readl(addr1);
36 ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); 36 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
37 37
38 /* Next, check if there's shadow or not */ 38 /* Next, check if there's shadow or not */
39 data0 = ctrl_inl(addr0); 39 data0 = __raw_readl(addr0);
40 data0 ^= SH_CACHE_VALID; 40 data0 ^= SH_CACHE_VALID;
41 ctrl_outl(data0, addr0); 41 __raw_writel(data0, addr0);
42 data1 = ctrl_inl(addr1); 42 data1 = __raw_readl(addr1);
43 data2 = data1 ^ SH_CACHE_VALID; 43 data2 = data1 ^ SH_CACHE_VALID;
44 ctrl_outl(data2, addr1); 44 __raw_writel(data2, addr1);
45 data3 = ctrl_inl(addr0); 45 data3 = __raw_readl(addr0);
46 46
47 /* Lastly, invaliate them. */ 47 /* Lastly, invaliate them. */
48 ctrl_outl(data0&~SH_CACHE_VALID, addr0); 48 __raw_writel(data0&~SH_CACHE_VALID, addr0);
49 ctrl_outl(data2&~SH_CACHE_VALID, addr1); 49 __raw_writel(data2&~SH_CACHE_VALID, addr1);
50 50
51 back_to_cached(); 51 back_to_cached();
52 52
@@ -94,9 +94,9 @@ int detect_cpu_and_cache_system(void)
94 boot_cpu_data.dcache.way_incr = (1 << 13); 94 boot_cpu_data.dcache.way_incr = (1 << 13);
95 boot_cpu_data.dcache.entry_mask = 0x1ff0; 95 boot_cpu_data.dcache.entry_mask = 0x1ff0;
96 boot_cpu_data.dcache.sets = 512; 96 boot_cpu_data.dcache.sets = 512;
97 ctrl_outl(CCR_CACHE_32KB, CCR3_REG); 97 __raw_writel(CCR_CACHE_32KB, CCR3_REG);
98#else 98#else
99 ctrl_outl(CCR_CACHE_16KB, CCR3_REG); 99 __raw_writel(CCR_CACHE_16KB, CCR3_REG);
100#endif 100#endif
101#endif 101#endif
102 } 102 }