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Diffstat (limited to 'arch/sh/kernel/cpu/sh2a/setup-sh7203.c')
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c119
1 files changed, 70 insertions, 49 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index a78d2a219f3b..a43124e608c3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -173,60 +173,83 @@ static struct intc_mask_reg mask_registers[] __initdata = {
173static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, 173static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL); 174 mask_registers, prio_registers, NULL);
175 175
176static struct plat_sci_port sci_platform_data[] = { 176static struct plat_sci_port scif0_platform_data = {
177 { 177 .mapbase = 0xfffe8000,
178 .mapbase = 0xfffe8000, 178 .flags = UPF_BOOT_AUTOCONF,
179 .flags = UPF_BOOT_AUTOCONF, 179 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
180 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 180 .scbrr_algo_id = SCBRR_ALGO_2,
181 .scbrr_algo_id = SCBRR_ALGO_2, 181 .type = PORT_SCIF,
182 .type = PORT_SCIF, 182 .irqs = { 192, 192, 192, 192 },
183 .irqs = { 192, 192, 192, 192 },
184 }, {
185 .mapbase = 0xfffe8800,
186 .flags = UPF_BOOT_AUTOCONF,
187 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
188 .scbrr_algo_id = SCBRR_ALGO_2,
189 .type = PORT_SCIF,
190 .irqs = { 196, 196, 196, 196 },
191 }, {
192 .mapbase = 0xfffe9000,
193 .flags = UPF_BOOT_AUTOCONF,
194 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
195 .scbrr_algo_id = SCBRR_ALGO_2,
196 .type = PORT_SCIF,
197 .irqs = { 200, 200, 200, 200 },
198 }, {
199 .mapbase = 0xfffe9800,
200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF,
204 .irqs = { 204, 204, 204, 204 },
205 }, {
206 .flags = 0,
207 }
208}; 183};
209 184
210static struct platform_device sci_device = { 185static struct platform_device scif0_device = {
211 .name = "sh-sci", 186 .name = "sh-sci",
212 .id = -1, 187 .id = 0,
188 .dev = {
189 .platform_data = &scif0_platform_data,
190 },
191};
192
193static struct plat_sci_port scif1_platform_data = {
194 .mapbase = 0xfffe8800,
195 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCIF,
199 .irqs = { 196, 196, 196, 196 },
200};
201
202static struct platform_device scif1_device = {
203 .name = "sh-sci",
204 .id = 1,
205 .dev = {
206 .platform_data = &scif1_platform_data,
207 },
208};
209
210static struct plat_sci_port scif2_platform_data = {
211 .mapbase = 0xfffe9000,
212 .flags = UPF_BOOT_AUTOCONF,
213 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
214 .scbrr_algo_id = SCBRR_ALGO_2,
215 .type = PORT_SCIF,
216 .irqs = { 200, 200, 200, 200 },
217};
218
219static struct platform_device scif2_device = {
220 .name = "sh-sci",
221 .id = 2,
222 .dev = {
223 .platform_data = &scif2_platform_data,
224 },
225};
226
227static struct plat_sci_port scif3_platform_data = {
228 .mapbase = 0xfffe9800,
229 .flags = UPF_BOOT_AUTOCONF,
230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
231 .scbrr_algo_id = SCBRR_ALGO_2,
232 .type = PORT_SCIF,
233 .irqs = { 204, 204, 204, 204 },
234};
235
236static struct platform_device scif3_device = {
237 .name = "sh-sci",
238 .id = 3,
213 .dev = { 239 .dev = {
214 .platform_data = sci_platform_data, 240 .platform_data = &scif3_platform_data,
215 }, 241 },
216}; 242};
217 243
218static struct sh_timer_config cmt0_platform_data = { 244static struct sh_timer_config cmt0_platform_data = {
219 .name = "CMT0",
220 .channel_offset = 0x02, 245 .channel_offset = 0x02,
221 .timer_bit = 0, 246 .timer_bit = 0,
222 .clk = "peripheral_clk",
223 .clockevent_rating = 125, 247 .clockevent_rating = 125,
224 .clocksource_rating = 0, /* disabled due to code generation issues */ 248 .clocksource_rating = 0, /* disabled due to code generation issues */
225}; 249};
226 250
227static struct resource cmt0_resources[] = { 251static struct resource cmt0_resources[] = {
228 [0] = { 252 [0] = {
229 .name = "CMT0",
230 .start = 0xfffec002, 253 .start = 0xfffec002,
231 .end = 0xfffec007, 254 .end = 0xfffec007,
232 .flags = IORESOURCE_MEM, 255 .flags = IORESOURCE_MEM,
@@ -248,17 +271,14 @@ static struct platform_device cmt0_device = {
248}; 271};
249 272
250static struct sh_timer_config cmt1_platform_data = { 273static struct sh_timer_config cmt1_platform_data = {
251 .name = "CMT1",
252 .channel_offset = 0x08, 274 .channel_offset = 0x08,
253 .timer_bit = 1, 275 .timer_bit = 1,
254 .clk = "peripheral_clk",
255 .clockevent_rating = 125, 276 .clockevent_rating = 125,
256 .clocksource_rating = 0, /* disabled due to code generation issues */ 277 .clocksource_rating = 0, /* disabled due to code generation issues */
257}; 278};
258 279
259static struct resource cmt1_resources[] = { 280static struct resource cmt1_resources[] = {
260 [0] = { 281 [0] = {
261 .name = "CMT1",
262 .start = 0xfffec008, 282 .start = 0xfffec008,
263 .end = 0xfffec00d, 283 .end = 0xfffec00d,
264 .flags = IORESOURCE_MEM, 284 .flags = IORESOURCE_MEM,
@@ -280,16 +300,13 @@ static struct platform_device cmt1_device = {
280}; 300};
281 301
282static struct sh_timer_config mtu2_0_platform_data = { 302static struct sh_timer_config mtu2_0_platform_data = {
283 .name = "MTU2_0",
284 .channel_offset = -0x80, 303 .channel_offset = -0x80,
285 .timer_bit = 0, 304 .timer_bit = 0,
286 .clk = "peripheral_clk",
287 .clockevent_rating = 200, 305 .clockevent_rating = 200,
288}; 306};
289 307
290static struct resource mtu2_0_resources[] = { 308static struct resource mtu2_0_resources[] = {
291 [0] = { 309 [0] = {
292 .name = "MTU2_0",
293 .start = 0xfffe4300, 310 .start = 0xfffe4300,
294 .end = 0xfffe4326, 311 .end = 0xfffe4326,
295 .flags = IORESOURCE_MEM, 312 .flags = IORESOURCE_MEM,
@@ -311,16 +328,13 @@ static struct platform_device mtu2_0_device = {
311}; 328};
312 329
313static struct sh_timer_config mtu2_1_platform_data = { 330static struct sh_timer_config mtu2_1_platform_data = {
314 .name = "MTU2_1",
315 .channel_offset = -0x100, 331 .channel_offset = -0x100,
316 .timer_bit = 1, 332 .timer_bit = 1,
317 .clk = "peripheral_clk",
318 .clockevent_rating = 200, 333 .clockevent_rating = 200,
319}; 334};
320 335
321static struct resource mtu2_1_resources[] = { 336static struct resource mtu2_1_resources[] = {
322 [0] = { 337 [0] = {
323 .name = "MTU2_1",
324 .start = 0xfffe4380, 338 .start = 0xfffe4380,
325 .end = 0xfffe4390, 339 .end = 0xfffe4390,
326 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -362,7 +376,10 @@ static struct platform_device rtc_device = {
362}; 376};
363 377
364static struct platform_device *sh7203_devices[] __initdata = { 378static struct platform_device *sh7203_devices[] __initdata = {
365 &sci_device, 379 &scif0_device,
380 &scif1_device,
381 &scif2_device,
382 &scif3_device,
366 &cmt0_device, 383 &cmt0_device,
367 &cmt1_device, 384 &cmt1_device,
368 &mtu2_0_device, 385 &mtu2_0_device,
@@ -375,7 +392,7 @@ static int __init sh7203_devices_setup(void)
375 return platform_add_devices(sh7203_devices, 392 return platform_add_devices(sh7203_devices,
376 ARRAY_SIZE(sh7203_devices)); 393 ARRAY_SIZE(sh7203_devices));
377} 394}
378__initcall(sh7203_devices_setup); 395arch_initcall(sh7203_devices_setup);
379 396
380void __init plat_irq_setup(void) 397void __init plat_irq_setup(void)
381{ 398{
@@ -383,6 +400,10 @@ void __init plat_irq_setup(void)
383} 400}
384 401
385static struct platform_device *sh7203_early_devices[] __initdata = { 402static struct platform_device *sh7203_early_devices[] __initdata = {
403 &scif0_device,
404 &scif1_device,
405 &scif2_device,
406 &scif3_device,
386 &cmt0_device, 407 &cmt0_device,
387 &cmt1_device, 408 &cmt1_device,
388 &mtu2_0_device, 409 &mtu2_0_device,