diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh2a/setup-sh7201.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/setup-sh7201.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index d08bf4c07d60..9df558dcdb86 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c | |||
@@ -180,6 +180,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, | |||
180 | static struct plat_sci_port scif0_platform_data = { | 180 | static struct plat_sci_port scif0_platform_data = { |
181 | .mapbase = 0xfffe8000, | 181 | .mapbase = 0xfffe8000, |
182 | .flags = UPF_BOOT_AUTOCONF, | 182 | .flags = UPF_BOOT_AUTOCONF, |
183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
184 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
183 | .type = PORT_SCIF, | 185 | .type = PORT_SCIF, |
184 | .irqs = { 180, 180, 180, 180 } | 186 | .irqs = { 180, 180, 180, 180 } |
185 | }; | 187 | }; |
@@ -195,6 +197,8 @@ static struct platform_device scif0_device = { | |||
195 | static struct plat_sci_port scif1_platform_data = { | 197 | static struct plat_sci_port scif1_platform_data = { |
196 | .mapbase = 0xfffe8800, | 198 | .mapbase = 0xfffe8800, |
197 | .flags = UPF_BOOT_AUTOCONF, | 199 | .flags = UPF_BOOT_AUTOCONF, |
200 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
201 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
198 | .type = PORT_SCIF, | 202 | .type = PORT_SCIF, |
199 | .irqs = { 184, 184, 184, 184 } | 203 | .irqs = { 184, 184, 184, 184 } |
200 | }; | 204 | }; |
@@ -210,6 +214,8 @@ static struct platform_device scif1_device = { | |||
210 | static struct plat_sci_port scif2_platform_data = { | 214 | static struct plat_sci_port scif2_platform_data = { |
211 | .mapbase = 0xfffe9000, | 215 | .mapbase = 0xfffe9000, |
212 | .flags = UPF_BOOT_AUTOCONF, | 216 | .flags = UPF_BOOT_AUTOCONF, |
217 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
218 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
213 | .type = PORT_SCIF, | 219 | .type = PORT_SCIF, |
214 | .irqs = { 188, 188, 188, 188 } | 220 | .irqs = { 188, 188, 188, 188 } |
215 | }; | 221 | }; |
@@ -225,6 +231,8 @@ static struct platform_device scif2_device = { | |||
225 | static struct plat_sci_port scif3_platform_data = { | 231 | static struct plat_sci_port scif3_platform_data = { |
226 | .mapbase = 0xfffe9800, | 232 | .mapbase = 0xfffe9800, |
227 | .flags = UPF_BOOT_AUTOCONF, | 233 | .flags = UPF_BOOT_AUTOCONF, |
234 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
235 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
228 | .type = PORT_SCIF, | 236 | .type = PORT_SCIF, |
229 | .irqs = { 192, 192, 192, 192 } | 237 | .irqs = { 192, 192, 192, 192 } |
230 | }; | 238 | }; |
@@ -240,6 +248,8 @@ static struct platform_device scif3_device = { | |||
240 | static struct plat_sci_port scif4_platform_data = { | 248 | static struct plat_sci_port scif4_platform_data = { |
241 | .mapbase = 0xfffea000, | 249 | .mapbase = 0xfffea000, |
242 | .flags = UPF_BOOT_AUTOCONF, | 250 | .flags = UPF_BOOT_AUTOCONF, |
251 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
252 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
243 | .type = PORT_SCIF, | 253 | .type = PORT_SCIF, |
244 | .irqs = { 196, 196, 196, 196 } | 254 | .irqs = { 196, 196, 196, 196 } |
245 | }; | 255 | }; |
@@ -255,6 +265,8 @@ static struct platform_device scif4_device = { | |||
255 | static struct plat_sci_port scif5_platform_data = { | 265 | static struct plat_sci_port scif5_platform_data = { |
256 | .mapbase = 0xfffea800, | 266 | .mapbase = 0xfffea800, |
257 | .flags = UPF_BOOT_AUTOCONF, | 267 | .flags = UPF_BOOT_AUTOCONF, |
268 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
269 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
258 | .type = PORT_SCIF, | 270 | .type = PORT_SCIF, |
259 | .irqs = { 200, 200, 200, 200 } | 271 | .irqs = { 200, 200, 200, 200 } |
260 | }; | 272 | }; |
@@ -270,6 +282,8 @@ static struct platform_device scif5_device = { | |||
270 | static struct plat_sci_port scif6_platform_data = { | 282 | static struct plat_sci_port scif6_platform_data = { |
271 | .mapbase = 0xfffeb000, | 283 | .mapbase = 0xfffeb000, |
272 | .flags = UPF_BOOT_AUTOCONF, | 284 | .flags = UPF_BOOT_AUTOCONF, |
285 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
286 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
273 | .type = PORT_SCIF, | 287 | .type = PORT_SCIF, |
274 | .irqs = { 204, 204, 204, 204 } | 288 | .irqs = { 204, 204, 204, 204 } |
275 | }; | 289 | }; |
@@ -285,6 +299,8 @@ static struct platform_device scif6_device = { | |||
285 | static struct plat_sci_port scif7_platform_data = { | 299 | static struct plat_sci_port scif7_platform_data = { |
286 | .mapbase = 0xfffeb800, | 300 | .mapbase = 0xfffeb800, |
287 | .flags = UPF_BOOT_AUTOCONF, | 301 | .flags = UPF_BOOT_AUTOCONF, |
302 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
303 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
288 | .type = PORT_SCIF, | 304 | .type = PORT_SCIF, |
289 | .irqs = { 208, 208, 208, 208 } | 305 | .irqs = { 208, 208, 208, 208 } |
290 | }; | 306 | }; |