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Diffstat (limited to 'arch/sh/kernel/cpu/irq/ipr.c')
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c111
1 files changed, 51 insertions, 60 deletions
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 8944abdf6e1c..a0089563cbfc 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -23,93 +23,81 @@
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/machvec.h> 24#include <asm/machvec.h>
25 25
26struct ipr_data {
27 unsigned int addr; /* Address of Interrupt Priority Register */
28 int shift; /* Shifts of the 16-bit data */
29 int priority; /* The priority */
30};
31 26
32static void disable_ipr_irq(unsigned int irq) 27static void disable_ipr_irq(unsigned int irq)
33{ 28{
34 struct ipr_data *p = get_irq_chip_data(irq); 29 struct ipr_data *p = get_irq_chip_data(irq);
30 int shift = p->shift*4;
35 /* Set the priority in IPR to 0 */ 31 /* Set the priority in IPR to 0 */
36 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); 32 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
37} 33}
38 34
39static void enable_ipr_irq(unsigned int irq) 35static void enable_ipr_irq(unsigned int irq)
40{ 36{
41 struct ipr_data *p = get_irq_chip_data(irq); 37 struct ipr_data *p = get_irq_chip_data(irq);
38 int shift = p->shift*4;
42 /* Set priority in IPR back to original value */ 39 /* Set priority in IPR back to original value */
43 ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); 40 ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
44} 41}
45 42
46static struct irq_chip ipr_irq_chip = { 43static struct irq_chip ipr_irq_chip = {
47 .name = "ipr", 44 .name = "IPR",
48 .mask = disable_ipr_irq, 45 .mask = disable_ipr_irq,
49 .unmask = enable_ipr_irq, 46 .unmask = enable_ipr_irq,
50 .mask_ack = disable_ipr_irq, 47 .mask_ack = disable_ipr_irq,
51}; 48};
52 49
53void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 50void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
54{ 51{
55 struct ipr_data ipr_data; 52 int i;
56 53
57 disable_irq_nosync(irq); 54 for (i = 0; i < nr_irqs; i++) {
58 55 unsigned int irq = table[i].irq;
59 ipr_data.addr = addr; 56 disable_irq_nosync(irq);
60 ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */ 57 set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
61 ipr_data.priority = priority; 58 handle_level_irq, "level");
62 59 set_irq_chip_data(irq, &table[i]);
63 set_irq_chip_and_handler(irq, &ipr_irq_chip, handle_level_irq); 60 enable_ipr_irq(irq);
64 set_irq_chip_data(irq, &ipr_data); 61 }
65
66 enable_ipr_irq(irq);
67} 62}
63EXPORT_SYMBOL(make_ipr_irq);
68 64
69/* XXX: This needs to die a horrible death.. */ 65static struct ipr_data sys_ipr_map[] = {
70void __init init_IRQ(void)
71{
72#ifndef CONFIG_CPU_SUBTYPE_SH7780 66#ifndef CONFIG_CPU_SUBTYPE_SH7780
73 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); 67 { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
74 make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); 68 { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
75#ifdef RTC_IRQ 69#ifdef RTC_IRQ
76 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); 70 { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
77#endif 71#endif
78
79#ifdef SCI_ERI_IRQ 72#ifdef SCI_ERI_IRQ
80 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 73 { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
81 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 74 { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
82 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 75 { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
83#endif 76#endif
84
85#ifdef SCIF1_ERI_IRQ 77#ifdef SCIF1_ERI_IRQ
86 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 78 { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
87 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 79 { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
88 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 80 { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
89 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 81 { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
90#endif 82#endif
91
92#if defined(CONFIG_CPU_SUBTYPE_SH7300) 83#if defined(CONFIG_CPU_SUBTYPE_SH7300)
93 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); 84 { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
94 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 85 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
95 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 86 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
96 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 87 { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
97#endif 88#endif
98
99#ifdef SCIF_ERI_IRQ 89#ifdef SCIF_ERI_IRQ
100 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 90 { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
101 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 91 { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
102 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 92 { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
103 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 93 { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
104#endif 94#endif
105
106#ifdef IRDA_ERI_IRQ 95#ifdef IRDA_ERI_IRQ
107 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 96 { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
108 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 97 { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
109 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 98 { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
110 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 99 { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
111#endif 100#endif
112
113#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 101#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
114 defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 102 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
115 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 103 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
@@ -123,14 +111,19 @@ void __init init_IRQ(void)
123 * You should set corresponding bits of PFC to "00" 111 * You should set corresponding bits of PFC to "00"
124 * to enable these interrupts. 112 * to enable these interrupts.
125 */ 113 */
126 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); 114 { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
127 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); 115 { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
128 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); 116 { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
129 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); 117 { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
130 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); 118 { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
131 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); 119 { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
132#endif 120#endif
133#endif 121#endif
122};
123
124void __init init_IRQ(void)
125{
126 make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
134 127
135#ifdef CONFIG_CPU_HAS_PINT_IRQ 128#ifdef CONFIG_CPU_HAS_PINT_IRQ
136 init_IRQ_pint(); 129 init_IRQ_pint();
@@ -152,5 +145,3 @@ int ipr_irq_demux(int irq)
152 return irq; 145 return irq;
153} 146}
154#endif 147#endif
155
156EXPORT_SYMBOL(make_ipr_irq);