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-rw-r--r--arch/sh/kernel/cpu/irq/intc.c710
1 files changed, 0 insertions, 710 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
deleted file mode 100644
index 8c70e201bde0..000000000000
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ /dev/null
@@ -1,710 +0,0 @@
1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24
25#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
28
29#define _INTC_SHIFT(h) (h & 0x1f)
30#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31#define _INTC_FN(h) ((h >> 9) & 0xf)
32#define _INTC_MODE(h) ((h >> 13) & 0x7)
33#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
35
36struct intc_handle_int {
37 unsigned int irq;
38 unsigned long handle;
39};
40
41struct intc_desc_int {
42 unsigned long *reg;
43#ifdef CONFIG_SMP
44 unsigned long *smp;
45#endif
46 unsigned int nr_reg;
47 struct intc_handle_int *prio;
48 unsigned int nr_prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
51 struct irq_chip chip;
52};
53
54#ifdef CONFIG_SMP
55#define IS_SMP(x) x.smp
56#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
58#else
59#define IS_SMP(x) 0
60#define INTC_REG(d, x, c) (d->reg[(x)])
61#define SMP_NR(d, x) 1
62#endif
63
64static unsigned int intc_prio_level[NR_IRQS]; /* for now */
65#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
66static unsigned long ack_handle[NR_IRQS];
67#endif
68
69static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
70{
71 struct irq_chip *chip = get_irq_chip(irq);
72 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
73}
74
75static inline unsigned int set_field(unsigned int value,
76 unsigned int field_value,
77 unsigned int handle)
78{
79 unsigned int width = _INTC_WIDTH(handle);
80 unsigned int shift = _INTC_SHIFT(handle);
81
82 value &= ~(((1 << width) - 1) << shift);
83 value |= field_value << shift;
84 return value;
85}
86
87static void write_8(unsigned long addr, unsigned long h, unsigned long data)
88{
89 ctrl_outb(set_field(0, data, h), addr);
90}
91
92static void write_16(unsigned long addr, unsigned long h, unsigned long data)
93{
94 ctrl_outw(set_field(0, data, h), addr);
95}
96
97static void write_32(unsigned long addr, unsigned long h, unsigned long data)
98{
99 ctrl_outl(set_field(0, data, h), addr);
100}
101
102static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
103{
104 unsigned long flags;
105 local_irq_save(flags);
106 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
107 local_irq_restore(flags);
108}
109
110static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
111{
112 unsigned long flags;
113 local_irq_save(flags);
114 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
115 local_irq_restore(flags);
116}
117
118static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
119{
120 unsigned long flags;
121 local_irq_save(flags);
122 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
123 local_irq_restore(flags);
124}
125
126enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
127
128static void (*intc_reg_fns[])(unsigned long addr,
129 unsigned long h,
130 unsigned long data) = {
131 [REG_FN_WRITE_BASE + 0] = write_8,
132 [REG_FN_WRITE_BASE + 1] = write_16,
133 [REG_FN_WRITE_BASE + 3] = write_32,
134 [REG_FN_MODIFY_BASE + 0] = modify_8,
135 [REG_FN_MODIFY_BASE + 1] = modify_16,
136 [REG_FN_MODIFY_BASE + 3] = modify_32,
137};
138
139enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
140 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
141 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
142 MODE_PRIO_REG, /* Priority value written to enable interrupt */
143 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
144};
145
146static void intc_mode_field(unsigned long addr,
147 unsigned long handle,
148 void (*fn)(unsigned long,
149 unsigned long,
150 unsigned long),
151 unsigned int irq)
152{
153 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
154}
155
156static void intc_mode_zero(unsigned long addr,
157 unsigned long handle,
158 void (*fn)(unsigned long,
159 unsigned long,
160 unsigned long),
161 unsigned int irq)
162{
163 fn(addr, handle, 0);
164}
165
166static void intc_mode_prio(unsigned long addr,
167 unsigned long handle,
168 void (*fn)(unsigned long,
169 unsigned long,
170 unsigned long),
171 unsigned int irq)
172{
173 fn(addr, handle, intc_prio_level[irq]);
174}
175
176static void (*intc_enable_fns[])(unsigned long addr,
177 unsigned long handle,
178 void (*fn)(unsigned long,
179 unsigned long,
180 unsigned long),
181 unsigned int irq) = {
182 [MODE_ENABLE_REG] = intc_mode_field,
183 [MODE_MASK_REG] = intc_mode_zero,
184 [MODE_DUAL_REG] = intc_mode_field,
185 [MODE_PRIO_REG] = intc_mode_prio,
186 [MODE_PCLR_REG] = intc_mode_prio,
187};
188
189static void (*intc_disable_fns[])(unsigned long addr,
190 unsigned long handle,
191 void (*fn)(unsigned long,
192 unsigned long,
193 unsigned long),
194 unsigned int irq) = {
195 [MODE_ENABLE_REG] = intc_mode_zero,
196 [MODE_MASK_REG] = intc_mode_field,
197 [MODE_DUAL_REG] = intc_mode_field,
198 [MODE_PRIO_REG] = intc_mode_zero,
199 [MODE_PCLR_REG] = intc_mode_field,
200};
201
202static inline void _intc_enable(unsigned int irq, unsigned long handle)
203{
204 struct intc_desc_int *d = get_intc_desc(irq);
205 unsigned long addr;
206 unsigned int cpu;
207
208 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
209 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
210 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
211 [_INTC_FN(handle)], irq);
212 }
213}
214
215static void intc_enable(unsigned int irq)
216{
217 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
218}
219
220static void intc_disable(unsigned int irq)
221{
222 struct intc_desc_int *d = get_intc_desc(irq);
223 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
224 unsigned long addr;
225 unsigned int cpu;
226
227 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
228 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
229 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
230 [_INTC_FN(handle)], irq);
231 }
232}
233
234#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
235static void intc_mask_ack(unsigned int irq)
236{
237 struct intc_desc_int *d = get_intc_desc(irq);
238 unsigned long handle = ack_handle[irq];
239 unsigned long addr;
240
241 intc_disable(irq);
242
243 /* read register and write zero only to the assocaited bit */
244
245 if (handle) {
246 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
247 switch (_INTC_FN(handle)) {
248 case REG_FN_MODIFY_BASE + 0: /* 8bit */
249 ctrl_inb(addr);
250 ctrl_outb(0xff ^ set_field(0, 1, handle), addr);
251 break;
252 case REG_FN_MODIFY_BASE + 1: /* 16bit */
253 ctrl_inw(addr);
254 ctrl_outw(0xffff ^ set_field(0, 1, handle), addr);
255 break;
256 case REG_FN_MODIFY_BASE + 3: /* 32bit */
257 ctrl_inl(addr);
258 ctrl_outl(0xffffffff ^ set_field(0, 1, handle), addr);
259 break;
260 default:
261 BUG();
262 break;
263 }
264 }
265}
266#endif
267
268static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
269 unsigned int nr_hp,
270 unsigned int irq)
271{
272 int i;
273
274 /* this doesn't scale well, but...
275 *
276 * this function should only be used for cerain uncommon
277 * operations such as intc_set_priority() and intc_set_sense()
278 * and in those rare cases performance doesn't matter that much.
279 * keeping the memory footprint low is more important.
280 *
281 * one rather simple way to speed this up and still keep the
282 * memory footprint down is to make sure the array is sorted
283 * and then perform a bisect to lookup the irq.
284 */
285
286 for (i = 0; i < nr_hp; i++) {
287 if ((hp + i)->irq != irq)
288 continue;
289
290 return hp + i;
291 }
292
293 return NULL;
294}
295
296int intc_set_priority(unsigned int irq, unsigned int prio)
297{
298 struct intc_desc_int *d = get_intc_desc(irq);
299 struct intc_handle_int *ihp;
300
301 if (!intc_prio_level[irq] || prio <= 1)
302 return -EINVAL;
303
304 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
305 if (ihp) {
306 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
307 return -EINVAL;
308
309 intc_prio_level[irq] = prio;
310
311 /*
312 * only set secondary masking method directly
313 * primary masking method is using intc_prio_level[irq]
314 * priority level will be set during next enable()
315 */
316
317 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
318 _intc_enable(irq, ihp->handle);
319 }
320 return 0;
321}
322
323#define VALID(x) (x | 0x80)
324
325static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
326 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
327 [IRQ_TYPE_EDGE_RISING] = VALID(1),
328 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
329 /* SH7706, SH7707 and SH7709 do not support high level triggered */
330#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
331 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
332 !defined(CONFIG_CPU_SUBTYPE_SH7709)
333 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
334#endif
335};
336
337static int intc_set_sense(unsigned int irq, unsigned int type)
338{
339 struct intc_desc_int *d = get_intc_desc(irq);
340 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
341 struct intc_handle_int *ihp;
342 unsigned long addr;
343
344 if (!value)
345 return -EINVAL;
346
347 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
348 if (ihp) {
349 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
350 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
351 }
352 return 0;
353}
354
355static unsigned int __init intc_get_reg(struct intc_desc_int *d,
356 unsigned long address)
357{
358 unsigned int k;
359
360 for (k = 0; k < d->nr_reg; k++) {
361 if (d->reg[k] == address)
362 return k;
363 }
364
365 BUG();
366 return 0;
367}
368
369static intc_enum __init intc_grp_id(struct intc_desc *desc,
370 intc_enum enum_id)
371{
372 struct intc_group *g = desc->groups;
373 unsigned int i, j;
374
375 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
376 g = desc->groups + i;
377
378 for (j = 0; g->enum_ids[j]; j++) {
379 if (g->enum_ids[j] != enum_id)
380 continue;
381
382 return g->enum_id;
383 }
384 }
385
386 return 0;
387}
388
389static unsigned int __init intc_mask_data(struct intc_desc *desc,
390 struct intc_desc_int *d,
391 intc_enum enum_id, int do_grps)
392{
393 struct intc_mask_reg *mr = desc->mask_regs;
394 unsigned int i, j, fn, mode;
395 unsigned long reg_e, reg_d;
396
397 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
398 mr = desc->mask_regs + i;
399
400 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
401 if (mr->enum_ids[j] != enum_id)
402 continue;
403
404 if (mr->set_reg && mr->clr_reg) {
405 fn = REG_FN_WRITE_BASE;
406 mode = MODE_DUAL_REG;
407 reg_e = mr->clr_reg;
408 reg_d = mr->set_reg;
409 } else {
410 fn = REG_FN_MODIFY_BASE;
411 if (mr->set_reg) {
412 mode = MODE_ENABLE_REG;
413 reg_e = mr->set_reg;
414 reg_d = mr->set_reg;
415 } else {
416 mode = MODE_MASK_REG;
417 reg_e = mr->clr_reg;
418 reg_d = mr->clr_reg;
419 }
420 }
421
422 fn += (mr->reg_width >> 3) - 1;
423 return _INTC_MK(fn, mode,
424 intc_get_reg(d, reg_e),
425 intc_get_reg(d, reg_d),
426 1,
427 (mr->reg_width - 1) - j);
428 }
429 }
430
431 if (do_grps)
432 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
433
434 return 0;
435}
436
437static unsigned int __init intc_prio_data(struct intc_desc *desc,
438 struct intc_desc_int *d,
439 intc_enum enum_id, int do_grps)
440{
441 struct intc_prio_reg *pr = desc->prio_regs;
442 unsigned int i, j, fn, mode, bit;
443 unsigned long reg_e, reg_d;
444
445 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
446 pr = desc->prio_regs + i;
447
448 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
449 if (pr->enum_ids[j] != enum_id)
450 continue;
451
452 if (pr->set_reg && pr->clr_reg) {
453 fn = REG_FN_WRITE_BASE;
454 mode = MODE_PCLR_REG;
455 reg_e = pr->set_reg;
456 reg_d = pr->clr_reg;
457 } else {
458 fn = REG_FN_MODIFY_BASE;
459 mode = MODE_PRIO_REG;
460 if (!pr->set_reg)
461 BUG();
462 reg_e = pr->set_reg;
463 reg_d = pr->set_reg;
464 }
465
466 fn += (pr->reg_width >> 3) - 1;
467 bit = pr->reg_width - ((j + 1) * pr->field_width);
468
469 BUG_ON(bit < 0);
470
471 return _INTC_MK(fn, mode,
472 intc_get_reg(d, reg_e),
473 intc_get_reg(d, reg_d),
474 pr->field_width, bit);
475 }
476 }
477
478 if (do_grps)
479 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
480
481 return 0;
482}
483
484#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
485static unsigned int __init intc_ack_data(struct intc_desc *desc,
486 struct intc_desc_int *d,
487 intc_enum enum_id)
488{
489 struct intc_mask_reg *mr = desc->ack_regs;
490 unsigned int i, j, fn, mode;
491 unsigned long reg_e, reg_d;
492
493 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
494 mr = desc->ack_regs + i;
495
496 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
497 if (mr->enum_ids[j] != enum_id)
498 continue;
499
500 fn = REG_FN_MODIFY_BASE;
501 mode = MODE_ENABLE_REG;
502 reg_e = mr->set_reg;
503 reg_d = mr->set_reg;
504
505 fn += (mr->reg_width >> 3) - 1;
506 return _INTC_MK(fn, mode,
507 intc_get_reg(d, reg_e),
508 intc_get_reg(d, reg_d),
509 1,
510 (mr->reg_width - 1) - j);
511 }
512 }
513
514 return 0;
515}
516#endif
517
518static unsigned int __init intc_sense_data(struct intc_desc *desc,
519 struct intc_desc_int *d,
520 intc_enum enum_id)
521{
522 struct intc_sense_reg *sr = desc->sense_regs;
523 unsigned int i, j, fn, bit;
524
525 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
526 sr = desc->sense_regs + i;
527
528 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
529 if (sr->enum_ids[j] != enum_id)
530 continue;
531
532 fn = REG_FN_MODIFY_BASE;
533 fn += (sr->reg_width >> 3) - 1;
534 bit = sr->reg_width - ((j + 1) * sr->field_width);
535
536 BUG_ON(bit < 0);
537
538 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
539 0, sr->field_width, bit);
540 }
541 }
542
543 return 0;
544}
545
546static void __init intc_register_irq(struct intc_desc *desc,
547 struct intc_desc_int *d,
548 intc_enum enum_id,
549 unsigned int irq)
550{
551 struct intc_handle_int *hp;
552 unsigned int data[2], primary;
553
554 /* Prefer single interrupt source bitmap over other combinations:
555 * 1. bitmap, single interrupt source
556 * 2. priority, single interrupt source
557 * 3. bitmap, multiple interrupt sources (groups)
558 * 4. priority, multiple interrupt sources (groups)
559 */
560
561 data[0] = intc_mask_data(desc, d, enum_id, 0);
562 data[1] = intc_prio_data(desc, d, enum_id, 0);
563
564 primary = 0;
565 if (!data[0] && data[1])
566 primary = 1;
567
568 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
569 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
570
571 if (!data[primary])
572 primary ^= 1;
573
574 BUG_ON(!data[primary]); /* must have primary masking method */
575
576 disable_irq_nosync(irq);
577 set_irq_chip_and_handler_name(irq, &d->chip,
578 handle_level_irq, "level");
579 set_irq_chip_data(irq, (void *)data[primary]);
580
581 /* set priority level
582 * - this needs to be at least 2 for 5-bit priorities on 7780
583 */
584 intc_prio_level[irq] = 2;
585
586 /* enable secondary masking method if present */
587 if (data[!primary])
588 _intc_enable(irq, data[!primary]);
589
590 /* add irq to d->prio list if priority is available */
591 if (data[1]) {
592 hp = d->prio + d->nr_prio;
593 hp->irq = irq;
594 hp->handle = data[1];
595
596 if (primary) {
597 /*
598 * only secondary priority should access registers, so
599 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
600 */
601
602 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
603 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
604 }
605 d->nr_prio++;
606 }
607
608 /* add irq to d->sense list if sense is available */
609 data[0] = intc_sense_data(desc, d, enum_id);
610 if (data[0]) {
611 (d->sense + d->nr_sense)->irq = irq;
612 (d->sense + d->nr_sense)->handle = data[0];
613 d->nr_sense++;
614 }
615
616 /* irq should be disabled by default */
617 d->chip.mask(irq);
618
619#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
620 if (desc->ack_regs)
621 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
622#endif
623}
624
625static unsigned int __init save_reg(struct intc_desc_int *d,
626 unsigned int cnt,
627 unsigned long value,
628 unsigned int smp)
629{
630 if (value) {
631 d->reg[cnt] = value;
632#ifdef CONFIG_SMP
633 d->smp[cnt] = smp;
634#endif
635 return 1;
636 }
637
638 return 0;
639}
640
641
642void __init register_intc_controller(struct intc_desc *desc)
643{
644 unsigned int i, k, smp;
645 struct intc_desc_int *d;
646
647 d = alloc_bootmem(sizeof(*d));
648
649 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
650 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
651 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
652
653#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
654 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
655#endif
656 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
657#ifdef CONFIG_SMP
658 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
659#endif
660 k = 0;
661
662 if (desc->mask_regs) {
663 for (i = 0; i < desc->nr_mask_regs; i++) {
664 smp = IS_SMP(desc->mask_regs[i]);
665 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
666 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
667 }
668 }
669
670 if (desc->prio_regs) {
671 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
672
673 for (i = 0; i < desc->nr_prio_regs; i++) {
674 smp = IS_SMP(desc->prio_regs[i]);
675 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
676 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
677 }
678 }
679
680 if (desc->sense_regs) {
681 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
682
683 for (i = 0; i < desc->nr_sense_regs; i++) {
684 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
685 }
686 }
687
688 d->chip.name = desc->name;
689 d->chip.mask = intc_disable;
690 d->chip.unmask = intc_enable;
691 d->chip.mask_ack = intc_disable;
692 d->chip.set_type = intc_set_sense;
693
694#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
695 if (desc->ack_regs) {
696 for (i = 0; i < desc->nr_ack_regs; i++)
697 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
698
699 d->chip.mask_ack = intc_mask_ack;
700 }
701#endif
702
703 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
704
705 for (i = 0; i < desc->nr_vectors; i++) {
706 struct intc_vect *vect = desc->vectors + i;
707
708 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
709 }
710}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 18:18:50 -0500