diff options
Diffstat (limited to 'arch/sh/kernel/cpu/init.c')
-rw-r--r-- | arch/sh/kernel/cpu/init.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 6c3c7687e81f..4b339a640b13 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c | |||
@@ -48,7 +48,7 @@ static void __init cache_init(void) | |||
48 | { | 48 | { |
49 | unsigned long ccr, flags; | 49 | unsigned long ccr, flags; |
50 | 50 | ||
51 | if (cpu_data->type == CPU_SH_NONE) | 51 | if (current_cpu_data.type == CPU_SH_NONE) |
52 | panic("Unknown CPU"); | 52 | panic("Unknown CPU"); |
53 | 53 | ||
54 | jump_to_P2(); | 54 | jump_to_P2(); |
@@ -68,7 +68,7 @@ static void __init cache_init(void) | |||
68 | if (ccr & CCR_CACHE_ENABLE) { | 68 | if (ccr & CCR_CACHE_ENABLE) { |
69 | unsigned long ways, waysize, addrstart; | 69 | unsigned long ways, waysize, addrstart; |
70 | 70 | ||
71 | waysize = cpu_data->dcache.sets; | 71 | waysize = current_cpu_data.dcache.sets; |
72 | 72 | ||
73 | #ifdef CCR_CACHE_ORA | 73 | #ifdef CCR_CACHE_ORA |
74 | /* | 74 | /* |
@@ -79,7 +79,7 @@ static void __init cache_init(void) | |||
79 | waysize >>= 1; | 79 | waysize >>= 1; |
80 | #endif | 80 | #endif |
81 | 81 | ||
82 | waysize <<= cpu_data->dcache.entry_shift; | 82 | waysize <<= current_cpu_data.dcache.entry_shift; |
83 | 83 | ||
84 | #ifdef CCR_CACHE_EMODE | 84 | #ifdef CCR_CACHE_EMODE |
85 | /* If EMODE is not set, we only have 1 way to flush. */ | 85 | /* If EMODE is not set, we only have 1 way to flush. */ |
@@ -87,7 +87,7 @@ static void __init cache_init(void) | |||
87 | ways = 1; | 87 | ways = 1; |
88 | else | 88 | else |
89 | #endif | 89 | #endif |
90 | ways = cpu_data->dcache.ways; | 90 | ways = current_cpu_data.dcache.ways; |
91 | 91 | ||
92 | addrstart = CACHE_OC_ADDRESS_ARRAY; | 92 | addrstart = CACHE_OC_ADDRESS_ARRAY; |
93 | do { | 93 | do { |
@@ -95,10 +95,10 @@ static void __init cache_init(void) | |||
95 | 95 | ||
96 | for (addr = addrstart; | 96 | for (addr = addrstart; |
97 | addr < addrstart + waysize; | 97 | addr < addrstart + waysize; |
98 | addr += cpu_data->dcache.linesz) | 98 | addr += current_cpu_data.dcache.linesz) |
99 | ctrl_outl(0, addr); | 99 | ctrl_outl(0, addr); |
100 | 100 | ||
101 | addrstart += cpu_data->dcache.way_incr; | 101 | addrstart += current_cpu_data.dcache.way_incr; |
102 | } while (--ways); | 102 | } while (--ways); |
103 | } | 103 | } |
104 | 104 | ||
@@ -110,7 +110,7 @@ static void __init cache_init(void) | |||
110 | 110 | ||
111 | #ifdef CCR_CACHE_EMODE | 111 | #ifdef CCR_CACHE_EMODE |
112 | /* Force EMODE if possible */ | 112 | /* Force EMODE if possible */ |
113 | if (cpu_data->dcache.ways > 1) | 113 | if (current_cpu_data.dcache.ways > 1) |
114 | flags |= CCR_CACHE_EMODE; | 114 | flags |= CCR_CACHE_EMODE; |
115 | else | 115 | else |
116 | flags &= ~CCR_CACHE_EMODE; | 116 | flags &= ~CCR_CACHE_EMODE; |
@@ -127,10 +127,10 @@ static void __init cache_init(void) | |||
127 | #ifdef CONFIG_SH_OCRAM | 127 | #ifdef CONFIG_SH_OCRAM |
128 | /* Turn on OCRAM -- halve the OC */ | 128 | /* Turn on OCRAM -- halve the OC */ |
129 | flags |= CCR_CACHE_ORA; | 129 | flags |= CCR_CACHE_ORA; |
130 | cpu_data->dcache.sets >>= 1; | 130 | current_cpu_data.dcache.sets >>= 1; |
131 | 131 | ||
132 | cpu_data->dcache.way_size = cpu_data->dcache.sets * | 132 | current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * |
133 | cpu_data->dcache.linesz; | 133 | current_cpu_data.dcache.linesz; |
134 | #endif | 134 | #endif |
135 | 135 | ||
136 | ctrl_outl(flags, CCR); | 136 | ctrl_outl(flags, CCR); |
@@ -172,7 +172,7 @@ static void __init dsp_init(void) | |||
172 | 172 | ||
173 | /* If the DSP bit is still set, this CPU has a DSP */ | 173 | /* If the DSP bit is still set, this CPU has a DSP */ |
174 | if (sr & SR_DSP) | 174 | if (sr & SR_DSP) |
175 | cpu_data->flags |= CPU_HAS_DSP; | 175 | current_cpu_data.flags |= CPU_HAS_DSP; |
176 | 176 | ||
177 | /* Now that we've determined the DSP status, clear the DSP bit. */ | 177 | /* Now that we've determined the DSP status, clear the DSP bit. */ |
178 | release_dsp(); | 178 | release_dsp(); |
@@ -204,18 +204,18 @@ asmlinkage void __init sh_cpu_init(void) | |||
204 | cache_init(); | 204 | cache_init(); |
205 | 205 | ||
206 | shm_align_mask = max_t(unsigned long, | 206 | shm_align_mask = max_t(unsigned long, |
207 | cpu_data->dcache.way_size - 1, | 207 | current_cpu_data.dcache.way_size - 1, |
208 | PAGE_SIZE - 1); | 208 | PAGE_SIZE - 1); |
209 | 209 | ||
210 | /* Disable the FPU */ | 210 | /* Disable the FPU */ |
211 | if (fpu_disabled) { | 211 | if (fpu_disabled) { |
212 | printk("FPU Disabled\n"); | 212 | printk("FPU Disabled\n"); |
213 | cpu_data->flags &= ~CPU_HAS_FPU; | 213 | current_cpu_data.flags &= ~CPU_HAS_FPU; |
214 | disable_fpu(); | 214 | disable_fpu(); |
215 | } | 215 | } |
216 | 216 | ||
217 | /* FPU initialization */ | 217 | /* FPU initialization */ |
218 | if ((cpu_data->flags & CPU_HAS_FPU)) { | 218 | if ((current_cpu_data.flags & CPU_HAS_FPU)) { |
219 | clear_thread_flag(TIF_USEDFPU); | 219 | clear_thread_flag(TIF_USEDFPU); |
220 | clear_used_math(); | 220 | clear_used_math(); |
221 | } | 221 | } |
@@ -233,7 +233,7 @@ asmlinkage void __init sh_cpu_init(void) | |||
233 | /* Disable the DSP */ | 233 | /* Disable the DSP */ |
234 | if (dsp_disabled) { | 234 | if (dsp_disabled) { |
235 | printk("DSP Disabled\n"); | 235 | printk("DSP Disabled\n"); |
236 | cpu_data->flags &= ~CPU_HAS_DSP; | 236 | current_cpu_data.flags &= ~CPU_HAS_DSP; |
237 | release_dsp(); | 237 | release_dsp(); |
238 | } | 238 | } |
239 | #endif | 239 | #endif |