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-rw-r--r--arch/sh/include/asm/Kbuild2
-rw-r--r--arch/sh/include/asm/elf.h27
-rw-r--r--arch/sh/include/asm/fixmap.h4
-rw-r--r--arch/sh/include/asm/gpio.h6
-rw-r--r--arch/sh/include/asm/irq.h2
-rw-r--r--arch/sh/include/asm/kprobes.h1
-rw-r--r--arch/sh/include/asm/pci.h2
-rw-r--r--arch/sh/include/asm/processor_32.h3
-rw-r--r--arch/sh/include/asm/processor_64.h3
-rw-r--r--arch/sh/include/asm/ptrace.h169
-rw-r--r--arch/sh/include/asm/ptrace_32.h83
-rw-r--r--arch/sh/include/asm/ptrace_64.h20
-rw-r--r--arch/sh/include/asm/sizes.h1
-rw-r--r--arch/sh/include/asm/sram.h38
-rw-r--r--arch/sh/include/asm/system.h2
-rw-r--r--arch/sh/include/asm/system_32.h15
-rw-r--r--arch/sh/include/asm/tlbflush.h2
-rw-r--r--arch/sh/include/asm/unistd_32.h27
-rw-r--r--arch/sh/include/asm/unistd_64.h5
-rw-r--r--arch/sh/include/cpu-sh3/cpu/mmu_context.h1
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7757.h301
-rw-r--r--arch/sh/include/cpu-sh4/cpu/shx3.h64
-rw-r--r--arch/sh/include/mach-common/mach/sh2007.h117
-rw-r--r--arch/sh/include/mach-sdk7786/mach/fpga.h26
-rw-r--r--arch/sh/include/mach-x3proto/mach/hardware.h12
-rw-r--r--arch/sh/include/mach-x3proto/mach/ilsel.h (renamed from arch/sh/include/asm/ilsel.h)0
27 files changed, 657 insertions, 280 deletions
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index 0eed47b236ab..7beb42322f60 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -5,5 +5,7 @@ header-y += cpu-features.h
5header-y += hw_breakpoint.h 5header-y += hw_breakpoint.h
6header-y += posix_types_32.h 6header-y += posix_types_32.h
7header-y += posix_types_64.h 7header-y += posix_types_64.h
8header-y += ptrace_32.h
9header-y += ptrace_64.h
8header-y += unistd_32.h 10header-y += unistd_32.h
9header-y += unistd_64.h 11header-y += unistd_64.h
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
index ce830faeebbf..f38112be67d2 100644
--- a/arch/sh/include/asm/elf.h
+++ b/arch/sh/include/asm/elf.h
@@ -50,25 +50,14 @@
50#define R_SH_GOTPC 167 50#define R_SH_GOTPC 167
51 51
52/* FDPIC relocs */ 52/* FDPIC relocs */
53#define R_SH_GOT20 70 53#define R_SH_GOT20 201
54#define R_SH_GOTOFF20 71 54#define R_SH_GOTOFF20 202
55#define R_SH_GOTFUNCDESC 72 55#define R_SH_GOTFUNCDESC 203
56#define R_SH_GOTFUNCDESC20 73 56#define R_SH_GOTFUNCDESC20 204
57#define R_SH_GOTOFFFUNCDESC 74 57#define R_SH_GOTOFFFUNCDESC 205
58#define R_SH_GOTOFFFUNCDESC20 75 58#define R_SH_GOTOFFFUNCDESC20 206
59#define R_SH_FUNCDESC 76 59#define R_SH_FUNCDESC 207
60#define R_SH_FUNCDESC_VALUE 77 60#define R_SH_FUNCDESC_VALUE 208
61
62#if 0 /* XXX - later .. */
63#define R_SH_GOT20 198
64#define R_SH_GOTOFF20 199
65#define R_SH_GOTFUNCDESC 200
66#define R_SH_GOTFUNCDESC20 201
67#define R_SH_GOTOFFFUNCDESC 202
68#define R_SH_GOTOFFFUNCDESC20 203
69#define R_SH_FUNCDESC 204
70#define R_SH_FUNCDESC_VALUE 205
71#endif
72 61
73/* SHmedia relocs */ 62/* SHmedia relocs */
74#define R_SH_IMM_LOW16 246 63#define R_SH_IMM_LOW16 246
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
index 6e7cea453895..bd7e79a12653 100644
--- a/arch/sh/include/asm/fixmap.h
+++ b/arch/sh/include/asm/fixmap.h
@@ -58,7 +58,7 @@ enum fixed_addresses {
58 58
59#ifdef CONFIG_HIGHMEM 59#ifdef CONFIG_HIGHMEM
60 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ 60 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
61 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, 61 FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1,
62#endif 62#endif
63 63
64#ifdef CONFIG_IOREMAP_FIXED 64#ifdef CONFIG_IOREMAP_FIXED
@@ -69,7 +69,7 @@ enum fixed_addresses {
69 */ 69 */
70#define FIX_N_IOREMAPS 32 70#define FIX_N_IOREMAPS 32
71 FIX_IOREMAP_BEGIN, 71 FIX_IOREMAP_BEGIN,
72 FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS, 72 FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1,
73#endif 73#endif
74 74
75 __end_of_fixed_addresses 75 __end_of_fixed_addresses
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
index f8d9a731e903..04f53d31489f 100644
--- a/arch/sh/include/asm/gpio.h
+++ b/arch/sh/include/asm/gpio.h
@@ -41,14 +41,12 @@ static inline int gpio_cansleep(unsigned gpio)
41 41
42static inline int gpio_to_irq(unsigned gpio) 42static inline int gpio_to_irq(unsigned gpio)
43{ 43{
44 WARN_ON(1); 44 return __gpio_to_irq(gpio);
45 return -ENOSYS;
46} 45}
47 46
48static inline int irq_to_gpio(unsigned int irq) 47static inline int irq_to_gpio(unsigned int irq)
49{ 48{
50 WARN_ON(1); 49 return -ENOSYS;
51 return -EINVAL;
52} 50}
53 51
54#endif /* CONFIG_GPIOLIB */ 52#endif /* CONFIG_GPIOLIB */
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 02c2f0102cfa..45d08b6a5ef7 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -9,7 +9,7 @@
9 * advised to cap this at the hard limit that they're interested in 9 * advised to cap this at the hard limit that they're interested in
10 * through the machvec. 10 * through the machvec.
11 */ 11 */
12#define NR_IRQS 256 12#define NR_IRQS 512
13#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */ 13#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */
14 14
15/* 15/*
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 036c3311233c..134f3980e44a 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -16,7 +16,6 @@ typedef insn_size_t kprobe_opcode_t;
16 ? (MAX_STACK_SIZE) \ 16 ? (MAX_STACK_SIZE) \
17 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) 17 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
18 18
19#define regs_return_value(_regs) ((_regs)->regs[0])
20#define flush_insn_slot(p) do { } while (0) 19#define flush_insn_slot(p) do { } while (0)
21#define kretprobe_blacklist_size 0 20#define kretprobe_blacklist_size 0
22 21
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 8bd952fcf3ba..f0efe97f1750 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -37,6 +37,8 @@ struct pci_channel {
37}; 37};
38 38
39/* arch/sh/drivers/pci/pci.c */ 39/* arch/sh/drivers/pci/pci.c */
40extern raw_spinlock_t pci_config_lock;
41
40extern int register_pci_controller(struct pci_channel *hose); 42extern int register_pci_controller(struct pci_channel *hose);
41extern void pcibios_report_status(unsigned int status_mask, int warn); 43extern void pcibios_report_status(unsigned int status_mask, int warn);
42 44
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index 61a445d2d02a..46d5179c9f49 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -13,7 +13,6 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <asm/page.h> 14#include <asm/page.h>
15#include <asm/types.h> 15#include <asm/types.h>
16#include <asm/ptrace.h>
17#include <asm/hw_breakpoint.h> 16#include <asm/hw_breakpoint.h>
18 17
19/* 18/*
@@ -194,8 +193,6 @@ extern unsigned long get_wchan(struct task_struct *p);
194#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) 193#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
195#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) 194#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
196 195
197#define user_stack_pointer(_regs) ((_regs)->regs[15])
198
199#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) 196#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
200#define PREFETCH_STRIDE L1_CACHE_BYTES 197#define PREFETCH_STRIDE L1_CACHE_BYTES
201#define ARCH_HAS_PREFETCH 198#define ARCH_HAS_PREFETCH
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index 621bc4618c6b..2a541ddb5a1b 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -17,7 +17,6 @@
17#include <linux/compiler.h> 17#include <linux/compiler.h>
18#include <asm/page.h> 18#include <asm/page.h>
19#include <asm/types.h> 19#include <asm/types.h>
20#include <asm/ptrace.h>
21#include <cpu/registers.h> 20#include <cpu/registers.h>
22 21
23/* 22/*
@@ -231,7 +230,5 @@ extern unsigned long get_wchan(struct task_struct *p);
231#define KSTK_EIP(tsk) ((tsk)->thread.pc) 230#define KSTK_EIP(tsk) ((tsk)->thread.pc)
232#define KSTK_ESP(tsk) ((tsk)->thread.sp) 231#define KSTK_ESP(tsk) ((tsk)->thread.sp)
233 232
234#define user_stack_pointer(_regs) ((_regs)->regs[15])
235
236#endif /* __ASSEMBLY__ */ 233#endif /* __ASSEMBLY__ */
237#endif /* __ASM_SH_PROCESSOR_64_H */ 234#endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 2168fde25611..f6edc10aa0d3 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -3,90 +3,7 @@
3 3
4/* 4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka 5 * Copyright (C) 1999, 2000 Niibe Yutaka
6 *
7 */
8#if defined(__SH5__)
9struct pt_regs {
10 unsigned long long pc;
11 unsigned long long sr;
12 long long syscall_nr;
13 unsigned long long regs[63];
14 unsigned long long tregs[8];
15 unsigned long long pad[2];
16};
17#else
18/*
19 * GCC defines register number like this:
20 * -----------------------------
21 * 0 - 15 are integer registers
22 * 17 - 22 are control/special registers
23 * 24 - 39 fp registers
24 * 40 - 47 xd registers
25 * 48 - fpscr register
26 * -----------------------------
27 *
28 * We follows above, except:
29 * 16 --- program counter (PC)
30 * 22 --- syscall #
31 * 23 --- floating point communication register
32 */ 6 */
33#define REG_REG0 0
34#define REG_REG15 15
35
36#define REG_PC 16
37
38#define REG_PR 17
39#define REG_SR 18
40#define REG_GBR 19
41#define REG_MACH 20
42#define REG_MACL 21
43
44#define REG_SYSCALL 22
45
46#define REG_FPREG0 23
47#define REG_FPREG15 38
48#define REG_XFREG0 39
49#define REG_XFREG15 54
50
51#define REG_FPSCR 55
52#define REG_FPUL 56
53
54/*
55 * This struct defines the way the registers are stored on the
56 * kernel stack during a system call or other kernel entry.
57 */
58struct pt_regs {
59 unsigned long regs[16];
60 unsigned long pc;
61 unsigned long pr;
62 unsigned long sr;
63 unsigned long gbr;
64 unsigned long mach;
65 unsigned long macl;
66 long tra;
67};
68
69/*
70 * This struct defines the way the DSP registers are stored on the
71 * kernel stack during a system call or other kernel entry.
72 */
73struct pt_dspregs {
74 unsigned long a1;
75 unsigned long a0g;
76 unsigned long a1g;
77 unsigned long m0;
78 unsigned long m1;
79 unsigned long a0;
80 unsigned long x0;
81 unsigned long x1;
82 unsigned long y0;
83 unsigned long y1;
84 unsigned long dsr;
85 unsigned long rs;
86 unsigned long re;
87 unsigned long mod;
88};
89#endif
90 7
91#define PTRACE_GETREGS 12 /* General registers */ 8#define PTRACE_GETREGS 12 /* General registers */
92#define PTRACE_SETREGS 13 9#define PTRACE_SETREGS 13
@@ -107,22 +24,102 @@ struct pt_dspregs {
107#define PT_DATA_ADDR 248 /* &(struct user)->start_data */ 24#define PT_DATA_ADDR 248 /* &(struct user)->start_data */
108#define PT_TEXT_LEN 252 25#define PT_TEXT_LEN 252
109 26
27#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
28#include "ptrace_64.h"
29#else
30#include "ptrace_32.h"
31#endif
32
110#ifdef __KERNEL__ 33#ifdef __KERNEL__
34
35#include <linux/stringify.h>
36#include <linux/stddef.h>
37#include <linux/thread_info.h>
111#include <asm/addrspace.h> 38#include <asm/addrspace.h>
112#include <asm/page.h> 39#include <asm/page.h>
113#include <asm/system.h> 40#include <asm/system.h>
114 41
115#define user_mode(regs) (((regs)->sr & 0x40000000)==0) 42#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
43#define user_stack_pointer(regs) ((unsigned long)(regs)->regs[15])
44#define kernel_stack_pointer(regs) ((unsigned long)(regs)->regs[15])
116#define instruction_pointer(regs) ((unsigned long)(regs)->pc) 45#define instruction_pointer(regs) ((unsigned long)(regs)->pc)
117 46
118extern void show_regs(struct pt_regs *); 47extern void show_regs(struct pt_regs *);
119 48
49#define arch_has_single_step() (1)
50
120/* 51/*
121 * These are defined as per linux/ptrace.h. 52 * kprobe-based event tracer support
122 */ 53 */
123struct task_struct; 54struct pt_regs_offset {
55 const char *name;
56 int offset;
57};
124 58
125#define arch_has_single_step() (1) 59#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
60#define REGS_OFFSET_NAME(num) \
61 {.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])}
62#define TREGS_OFFSET_NAME(num) \
63 {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])}
64#define REG_OFFSET_END {.name = NULL, .offset = 0}
65
66/* Query offset/name of register from its name/offset */
67extern int regs_query_register_offset(const char *name);
68extern const char *regs_query_register_name(unsigned int offset);
69
70extern const struct pt_regs_offset regoffset_table[];
71
72/**
73 * regs_get_register() - get register value from its offset
74 * @regs: pt_regs from which register value is gotten.
75 * @offset: offset number of the register.
76 *
77 * regs_get_register returns the value of a register. The @offset is the
78 * offset of the register in struct pt_regs address which specified by @regs.
79 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
80 */
81static inline unsigned long regs_get_register(struct pt_regs *regs,
82 unsigned int offset)
83{
84 if (unlikely(offset > MAX_REG_OFFSET))
85 return 0;
86 return *(unsigned long *)((unsigned long)regs + offset);
87}
88
89/**
90 * regs_within_kernel_stack() - check the address in the stack
91 * @regs: pt_regs which contains kernel stack pointer.
92 * @addr: address which is checked.
93 *
94 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
95 * If @addr is within the kernel stack, it returns true. If not, returns false.
96 */
97static inline int regs_within_kernel_stack(struct pt_regs *regs,
98 unsigned long addr)
99{
100 return ((addr & ~(THREAD_SIZE - 1)) ==
101 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
102}
103
104/**
105 * regs_get_kernel_stack_nth() - get Nth entry of the stack
106 * @regs: pt_regs which contains kernel stack pointer.
107 * @n: stack entry number.
108 *
109 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
110 * is specified by @regs. If the @n th entry is NOT in the kernel stack,
111 * this returns 0.
112 */
113static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
114 unsigned int n)
115{
116 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
117 addr += n;
118 if (regs_within_kernel_stack(regs, (unsigned long)addr))
119 return *addr;
120 else
121 return 0;
122}
126 123
127struct perf_event; 124struct perf_event;
128struct perf_sample_data; 125struct perf_sample_data;
diff --git a/arch/sh/include/asm/ptrace_32.h b/arch/sh/include/asm/ptrace_32.h
new file mode 100644
index 000000000000..35d9e257558c
--- /dev/null
+++ b/arch/sh/include/asm/ptrace_32.h
@@ -0,0 +1,83 @@
1#ifndef __ASM_SH_PTRACE_32_H
2#define __ASM_SH_PTRACE_32_H
3
4/*
5 * GCC defines register number like this:
6 * -----------------------------
7 * 0 - 15 are integer registers
8 * 17 - 22 are control/special registers
9 * 24 - 39 fp registers
10 * 40 - 47 xd registers
11 * 48 - fpscr register
12 * -----------------------------
13 *
14 * We follows above, except:
15 * 16 --- program counter (PC)
16 * 22 --- syscall #
17 * 23 --- floating point communication register
18 */
19#define REG_REG0 0
20#define REG_REG15 15
21
22#define REG_PC 16
23
24#define REG_PR 17
25#define REG_SR 18
26#define REG_GBR 19
27#define REG_MACH 20
28#define REG_MACL 21
29
30#define REG_SYSCALL 22
31
32#define REG_FPREG0 23
33#define REG_FPREG15 38
34#define REG_XFREG0 39
35#define REG_XFREG15 54
36
37#define REG_FPSCR 55
38#define REG_FPUL 56
39
40/*
41 * This struct defines the way the registers are stored on the
42 * kernel stack during a system call or other kernel entry.
43 */
44struct pt_regs {
45 unsigned long regs[16];
46 unsigned long pc;
47 unsigned long pr;
48 unsigned long sr;
49 unsigned long gbr;
50 unsigned long mach;
51 unsigned long macl;
52 long tra;
53};
54
55/*
56 * This struct defines the way the DSP registers are stored on the
57 * kernel stack during a system call or other kernel entry.
58 */
59struct pt_dspregs {
60 unsigned long a1;
61 unsigned long a0g;
62 unsigned long a1g;
63 unsigned long m0;
64 unsigned long m1;
65 unsigned long a0;
66 unsigned long x0;
67 unsigned long x1;
68 unsigned long y0;
69 unsigned long y1;
70 unsigned long dsr;
71 unsigned long rs;
72 unsigned long re;
73 unsigned long mod;
74};
75
76#ifdef __KERNEL__
77
78#define MAX_REG_OFFSET offsetof(struct pt_regs, tra)
79#define regs_return_value(regs) ((regs)->regs[0])
80
81#endif /* __KERNEL__ */
82
83#endif /* __ASM_SH_PTRACE_32_H */
diff --git a/arch/sh/include/asm/ptrace_64.h b/arch/sh/include/asm/ptrace_64.h
new file mode 100644
index 000000000000..d43c1cb0bbe7
--- /dev/null
+++ b/arch/sh/include/asm/ptrace_64.h
@@ -0,0 +1,20 @@
1#ifndef __ASM_SH_PTRACE_64_H
2#define __ASM_SH_PTRACE_64_H
3
4struct pt_regs {
5 unsigned long long pc;
6 unsigned long long sr;
7 long long syscall_nr;
8 unsigned long long regs[63];
9 unsigned long long tregs[8];
10 unsigned long long pad[2];
11};
12
13#ifdef __KERNEL__
14
15#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7])
16#define regs_return_value(regs) ((regs)->regs[3])
17
18#endif /* __KERNEL__ */
19
20#endif /* __ASM_SH_PTRACE_64_H */
diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h
index 3a1fb97770f1..0b9fe2d5c36d 100644
--- a/arch/sh/include/asm/sizes.h
+++ b/arch/sh/include/asm/sizes.h
@@ -32,6 +32,7 @@
32#define SZ_512 0x00000200 32#define SZ_512 0x00000200
33 33
34#define SZ_1K 0x00000400 34#define SZ_1K 0x00000400
35#define SZ_2K 0x00000800
35#define SZ_4K 0x00001000 36#define SZ_4K 0x00001000
36#define SZ_8K 0x00002000 37#define SZ_8K 0x00002000
37#define SZ_16K 0x00004000 38#define SZ_16K 0x00004000
diff --git a/arch/sh/include/asm/sram.h b/arch/sh/include/asm/sram.h
new file mode 100644
index 000000000000..a2808ce4c0aa
--- /dev/null
+++ b/arch/sh/include/asm/sram.h
@@ -0,0 +1,38 @@
1#ifndef __ASM_SRAM_H
2#define __ASM_SRAM_H
3
4#ifdef CONFIG_HAVE_SRAM_POOL
5
6#include <linux/spinlock.h>
7#include <linux/genalloc.h>
8
9/* arch/sh/mm/sram.c */
10extern struct gen_pool *sram_pool;
11
12static inline unsigned long sram_alloc(size_t len)
13{
14 if (!sram_pool)
15 return 0UL;
16
17 return gen_pool_alloc(sram_pool, len);
18}
19
20static inline void sram_free(unsigned long addr, size_t len)
21{
22 return gen_pool_free(sram_pool, addr, len);
23}
24
25#else
26
27static inline unsigned long sram_alloc(size_t len)
28{
29 return 0;
30}
31
32static inline void sram_free(unsigned long addr, size_t len)
33{
34}
35
36#endif /* CONFIG_HAVE_SRAM_POOL */
37
38#endif /* __ASM_SRAM_H */
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index 0bd7a17d5e1a..1f1af5afff03 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -140,8 +140,6 @@ extern unsigned int instruction_size(unsigned int insn);
140extern unsigned long cached_to_uncached; 140extern unsigned long cached_to_uncached;
141extern unsigned long uncached_size; 141extern unsigned long uncached_size;
142 142
143extern struct dentry *sh_debugfs_root;
144
145void per_cpu_trap_init(void); 143void per_cpu_trap_init(void);
146void default_idle(void); 144void default_idle(void);
147void cpu_idle_wait(void); 145void cpu_idle_wait(void);
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 51296b36770e..c941b2739405 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -212,17 +212,16 @@ static inline reg_size_t register_align(void *val)
212} 212}
213 213
214int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 214int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
215 struct mem_access *ma, int); 215 struct mem_access *ma, int, unsigned long address);
216 216
217static inline void trigger_address_error(void) 217static inline void trigger_address_error(void)
218{ 218{
219 if (__in_29bit_mode()) 219 __asm__ __volatile__ (
220 __asm__ __volatile__ ( 220 "ldc %0, sr\n\t"
221 "ldc %0, sr\n\t" 221 "mov.l @%1, %0"
222 "mov.l @%1, %0" 222 :
223 : 223 : "r" (0x10000000), "r" (0x80000001)
224 : "r" (0x10000000), "r" (0x80000001) 224 );
225 );
226} 225}
227 226
228asmlinkage void do_address_error(struct pt_regs *regs, 227asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/tlbflush.h b/arch/sh/include/asm/tlbflush.h
index e0ac97221ae6..0df66f0c7284 100644
--- a/arch/sh/include/asm/tlbflush.h
+++ b/arch/sh/include/asm/tlbflush.h
@@ -21,6 +21,8 @@ extern void local_flush_tlb_kernel_range(unsigned long start,
21 unsigned long end); 21 unsigned long end);
22extern void local_flush_tlb_one(unsigned long asid, unsigned long page); 22extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
23 23
24extern void __flush_tlb_global(void);
25
24#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
25 27
26extern void flush_tlb_all(void); 28extern void flush_tlb_all(void);
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 0e7f0fc8f086..903cd618eb74 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -345,12 +345,33 @@
345#define __NR_pwritev 334 345#define __NR_pwritev 334
346#define __NR_rt_tgsigqueueinfo 335 346#define __NR_rt_tgsigqueueinfo 335
347#define __NR_perf_event_open 336 347#define __NR_perf_event_open 336
348#define __NR_fanotify_init 337
349#define __NR_fanotify_mark 338
350#define __NR_prlimit64 339
348 351
349#define NR_syscalls 337 352/* Non-multiplexed socket family */
353#define __NR_socket 340
354#define __NR_bind 341
355#define __NR_connect 342
356#define __NR_listen 343
357#define __NR_accept 344
358#define __NR_getsockname 345
359#define __NR_getpeername 346
360#define __NR_socketpair 347
361#define __NR_send 348
362#define __NR_sendto 349
363#define __NR_recv 350
364#define __NR_recvfrom 351
365#define __NR_shutdown 352
366#define __NR_setsockopt 353
367#define __NR_getsockopt 354
368#define __NR_sendmsg 355
369#define __NR_recvmsg 356
370#define __NR_recvmmsg 357
350 371
351#ifdef __KERNEL__ 372#define NR_syscalls 358
352 373
353#define __IGNORE_recvmmsg 374#ifdef __KERNEL__
354 375
355#define __ARCH_WANT_IPC_PARSE_VERSION 376#define __ARCH_WANT_IPC_PARSE_VERSION
356#define __ARCH_WANT_OLD_READDIR 377#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 0580c33a1e04..09aa93f9eb70 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -387,10 +387,13 @@
387#define __NR_perf_event_open 364 387#define __NR_perf_event_open 364
388#define __NR_recvmmsg 365 388#define __NR_recvmmsg 365
389#define __NR_accept4 366 389#define __NR_accept4 366
390#define __NR_fanotify_init 367
391#define __NR_fanotify_mark 368
392#define __NR_prlimit64 369
390 393
391#ifdef __KERNEL__ 394#ifdef __KERNEL__
392 395
393#define NR_syscalls 367 396#define NR_syscalls 370
394 397
395#define __ARCH_WANT_IPC_PARSE_VERSION 398#define __ARCH_WANT_IPC_PARSE_VERSION
396#define __ARCH_WANT_OLD_READDIR 399#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
index ab09da73ce77..0c7c735ea82a 100644
--- a/arch/sh/include/cpu-sh3/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
@@ -16,6 +16,7 @@
16#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ 16#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
17 17
18#define MMUCR 0xFFFFFFE0 /* MMU Control Register */ 18#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
19#define MMUCR_TI (1 << 2) /* TLB flush bit */
19 20
20#define MMU_TLB_ADDRESS_ARRAY 0xF2000000 21#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
21#define MMU_PAGE_ASSOC_BIT 0x80 22#define MMU_PAGE_ASSOC_BIT 0x80
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index e1e90960ee9a..cffd25ed0240 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -56,7 +56,9 @@
56#define FRQCR1 0xffc40004 56#define FRQCR1 0xffc40004
57#define FRQMR1 0xffc40014 57#define FRQMR1 0xffc40014
58#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 58#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
59#define FRQCR 0xffc00014 59#define FRQCR0 0xffc00000
60#define FRQCR1 0xffc00004
61#define FRQMR1 0xffc00014
60#else 62#else
61#define FRQCR 0xffc00000 63#define FRQCR 0xffc00000
62#define FRQCR_PSTBY 0x0200 64#define FRQCR_PSTBY 0x0200
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
index f4d267efad71..15f3de11c55a 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7757.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -3,241 +3,252 @@
3 3
4enum { 4enum {
5 /* PTA */ 5 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, 6 GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3,
7 GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, 7 GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7,
8 8
9 /* PTB */ 9 /* PTB */
10 GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, 10 GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3,
11 GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, 11 GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7,
12 12
13 /* PTC */ 13 /* PTC */
14 GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, 14 GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3,
15 GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, 15 GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7,
16 16
17 /* PTD */ 17 /* PTD */
18 GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, 18 GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3,
19 GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, 19 GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7,
20 20
21 /* PTE */ 21 /* PTE */
22 GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, 22 GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3,
23 GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, 23 GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7,
24 24
25 /* PTF */ 25 /* PTF */
26 GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, 26 GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3,
27 GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, 27 GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7,
28 28
29 /* PTG */ 29 /* PTG */
30 GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4, 30 GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3,
31 GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, 31 GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7,
32 32
33 /* PTH */ 33 /* PTH */
34 GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, 34 GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3,
35 GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, 35 GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7,
36 36
37 /* PTI */ 37 /* PTI */
38 GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4, 38 GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3,
39 GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0, 39 GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7,
40 40
41 /* PTJ */ 41 /* PTJ */
42 GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, 42 GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,
43 GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, 43 GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV,
44 44
45 /* PTK */ 45 /* PTK */
46 GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, 46 GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,
47 GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, 47 GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7,
48 48
49 /* PTL */ 49 /* PTL */
50 GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, 50 GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,
51 GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, 51 GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV,
52 52
53 /* PTM */ 53 /* PTM */
54 GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, 54 GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,
55 GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, 55 GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7,
56 56
57 /* PTN */ 57 /* PTN */
58 GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, 58 GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,
59 GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, 59 GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV,
60 60
61 /* PTO */ 61 /* PTO */
62 GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4, 62 GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,
63 GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0, 63 GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7,
64 64
65 /* PTP */ 65 /* PTP */
66 GPIO_PTP6, GPIO_PTP5, GPIO_PTP4, 66 GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3,
67 GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0, 67 GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7,
68 68
69 /* PTQ */ 69 /* PTQ */
70 GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, 70 GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,
71 GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, 71 GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV,
72 72
73 /* PTR */ 73 /* PTR */
74 GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, 74 GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,
75 GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, 75 GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7,
76 76
77 /* PTS */ 77 /* PTS */
78 GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4, 78 GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3,
79 GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, 79 GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7,
80 80
81 /* PTT */ 81 /* PTT */
82 GPIO_PTT5, GPIO_PTT4, 82 GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3,
83 GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, 83 GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7,
84 84
85 /* PTU */ 85 /* PTU */
86 GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4, 86 GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3,
87 GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, 87 GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7,
88 88
89 /* PTV */ 89 /* PTV */
90 GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4, 90 GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3,
91 GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, 91 GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7,
92 92
93 /* PTW */ 93 /* PTW */
94 GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, 94 GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3,
95 GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, 95 GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7,
96 96
97 /* PTX */ 97 /* PTX */
98 GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, 98 GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3,
99 GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, 99 GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7,
100 100
101 /* PTY */ 101 /* PTY */
102 GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4, 102 GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3,
103 GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, 103 GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7,
104 104
105 /* PTZ */ 105 /* PTZ */
106 GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4, 106 GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3,
107 GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0, 107 GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7,
108 108
109 109
110 /* PTA (mobule: LBSC, CPG, LPC) */ 110 /* PTA (mobule: LBSC, RGMII) */
111 GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY, 111 GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
112 GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8, 112 GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
113 GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, 113 GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
114 GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
115
116 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
117 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
118 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
119 GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
120 GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
121 GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
122 GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ,
123 GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL,
124 114
125 /* PTC (mobule: SD) */ 115 /* PTB (mobule: INTC, ONFI, TMU) */
126 GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, 116 GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
127 GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, 117 GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
118 GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0,
119 GPIO_FN_ON_R_B0, GPIO_FN_ON_ALE, GPIO_FN_ON_CLE,
120 GPIO_FN_TCLK,
128 121
129 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ 122 /* PTC (mobule: IRQ, PWMU) */
130 GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4, 123 GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
131 GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, 124 GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
132 GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2, 125 GPIO_FN_PWMU0, GPIO_FN_PWMU1, GPIO_FN_PWMU2, GPIO_FN_PWMU3,
133 GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, 126 GPIO_FN_PWMU4, GPIO_FN_PWMU5,
134 127
135 /* PTE (mobule: EtherC) */ 128 /* PTD (mobule: SPI0, DMAC) */
136 GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1, 129 GPIO_FN_SP0_MOSI, GPIO_FN_SP0_MISO, GPIO_FN_SP0_SCK,
137 GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN, 130 GPIO_FN_SP0_SCK_FB, GPIO_FN_SP0_SS0, GPIO_FN_SP0_SS1,
138 GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1, 131 GPIO_FN_SP0_SS2, GPIO_FN_SP0_SS3, GPIO_FN_DREQ0,
139 GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER, 132 GPIO_FN_DACK0, GPIO_FN_TEND0,
140 133
141 /* PTF (mobule: EtherC) */ 134 /* PTE (mobule: RMII) */
142 GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1, 135 GPIO_FN_RMII0_CRS_DV, GPIO_FN_RMII0_TXD1, GPIO_FN_RMII0_TXD0,
143 GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN, 136 GPIO_FN_RMII0_TXEN, GPIO_FN_RMII0_REFCLK, GPIO_FN_RMII0_RXD1,
144 GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1, 137 GPIO_FN_RMII0_RXD0, GPIO_FN_RMII0_RX_ER,
145 GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER, 138
146 139 /* PTF (mobule: RMII, SerMux) */
147 /* PTG (mobule: SYSTEM, PWMX, LPC) */ 140 GPIO_FN_RMII1_CRS_DV, GPIO_FN_RMII1_TXD1, GPIO_FN_RMII1_TXD0,
148 GPIO_FN_STATUS0, GPIO_FN_STATUS1, 141 GPIO_FN_RMII1_TXEN, GPIO_FN_RMII1_REFCLK, GPIO_FN_RMII1_RXD1,
149 GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3, 142 GPIO_FN_RMII1_RXD0, GPIO_FN_RMII1_RX_ER, GPIO_FN_RAC_RI,
150 GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ, 143
151 144 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
152 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ 145 GPIO_FN_BOOTFMS, GPIO_FN_BOOTWP,
153 GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4, 146 GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_SERIRQ, GPIO_FN_WDTOVF,
147 GPIO_FN_LPCPD, GPIO_FN_LDRQ, GPIO_FN_MMCCLK, GPIO_FN_MMCCMD,
148
149 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
154 GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO, 150 GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
155 GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB, 151 GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
156 GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1, 152 GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
157 GPIO_FN_SP0_SS1, 153 GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_TEND1, GPIO_FN_DREQ1,
158 154 GPIO_FN_DACK1, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
159 /* PTI (mobule: INTC) */
160 GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
161 GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
162
163 /* PTJ (mobule: SCIF234, SERMUX) */
164 GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2,
165 GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD,
166 GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
167
168 /* PTK (mobule: SERMUX) */
169 GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD,
170 GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS,
171 GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
172 GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI,
173 155
174 /* PTL (mobule: SERMUX) */ 156 /* PTI (mobule: LBSC, SDHI) */
175 GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD, 157 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
176 GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, 158 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
177 GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, 159 GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
178 GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI, 160 GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
179 161
180 /* PTM (mobule: IIC, LPC) */ 162 /* PTJ (mobule: SCIF234) */
163 GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3,
164 GPIO_FN_RTS4, GPIO_FN_RXD4, GPIO_FN_TXD4,
165
166 /* PTK (mobule: SERMUX, LBSC, SCIF) */
167 GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, GPIO_FN_COM2_RTS,
168 GPIO_FN_COM2_CTS, GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
169 GPIO_FN_COM2_DCD, GPIO_FN_CLKOUT,
170 GPIO_FN_SCK2, GPIO_FN_SCK4, GPIO_FN_SCK3,
171
172 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
173 GPIO_FN_RAC_RXD, GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
174 GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, GPIO_FN_RAC_DCD,
175 GPIO_FN_RAC_TXD, GPIO_FN_RXD2, GPIO_FN_CS5,
176 GPIO_FN_CS6, GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
177 GPIO_FN_TXD2,
178
179 /* PTM (mobule: LBSC, IIC) */
180 GPIO_FN_CS4, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_CS0,
181 GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7, 181 GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
182 GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1,
183
184 /* PTN (mobule: SCIF234, EVC) */
185 GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2,
186 GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2,
187 GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
188 GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
189 182
190 /* PTO (mobule: SGPIO) */ 183 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
191 GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, 184 GPIO_FN_VBUS_EN, GPIO_FN_VBUS_OC, GPIO_FN_JMCTCK,
192 GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO, 185 GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
193 GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, 186 GPIO_FN_JMCTRST,
194 GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO, 187 GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, GPIO_FN_SGPIO1_DI,
188 GPIO_FN_SGPIO1_DO, GPIO_FN_SUB_CLKIN,
195 189
196 /* PTP (mobule: JMC, SCIF234) */ 190 /* PTO (mobule: SGPIO, SerMux) */
197 GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, 191 GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, GPIO_FN_SGPIO0_DI,
198 GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3, 192 GPIO_FN_SGPIO0_DO, GPIO_FN_SGPIO2_CLK, GPIO_FN_SGPIO2_LOAD,
193 GPIO_FN_SGPIO2_DI, GPIO_FN_SGPIO2_DO, GPIO_FN_COM1_TXD,
194 GPIO_FN_COM1_RXD, GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
199 195
200 /* PTQ (mobule: LPC) */ 196 /* PTQ (mobule: LPC) */
201 GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0, 197 GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
202 GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK, 198 GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
203 199
204 /* PTR (mobule: GRA, IIC) */ 200 /* PTR (mobule: GRA, IIC) */
205 GPIO_FN_DDC3, GPIO_FN_DDC2, 201 GPIO_FN_DDC3, GPIO_FN_DDC2, GPIO_FN_SDA2, GPIO_FN_SCL2,
206 GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2,
207 GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0, 202 GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
203 GPIO_FN_SDA8, GPIO_FN_SCL8,
208 204
209 /* PTS (mobule: GRA, IIC) */ 205 /* PTS (mobule: GRA, IIC) */
210 GPIO_FN_DDC1, GPIO_FN_DDC0, 206 GPIO_FN_DDC1, GPIO_FN_DDC0, GPIO_FN_SDA5, GPIO_FN_SCL5,
211 GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5,
212 GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3, 207 GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
208 GPIO_FN_SDA9, GPIO_FN_SCL9,
213 209
214 /* PTT (mobule: SYSTEM, PWMX) */ 210 /* PTT (mobule: PWMX, AUD) */
215 GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, 211 GPIO_FN_PWMX7, GPIO_FN_PWMX6, GPIO_FN_PWMX5, GPIO_FN_PWMX4,
216 GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, 212 GPIO_FN_PWMX3, GPIO_FN_PWMX2, GPIO_FN_PWMX1, GPIO_FN_PWMX0,
217 GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, 213 GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1,
218 GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4, 214 GPIO_FN_AUDATA0, GPIO_FN_STATUS1, GPIO_FN_STATUS0,
219 215
220 /* PTU (mobule: LBSC, DMAC) */ 216 /* PTU (mobule: LPC, APM) */
221 GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0, 217 GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
222 GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24, 218 GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
223 GPIO_FN_DREQ0, GPIO_FN_DACK0, 219 GPIO_FN_APMONCTL_O, GPIO_FN_APMPWBTOUT_O, GPIO_FN_APMSCI_O,
220 GPIO_FN_APMVDDON, GPIO_FN_APMSLPBTN, GPIO_FN_APMPWRBTN,
221 GPIO_FN_APMS5N, GPIO_FN_APMS3N,
224 222
225 /* PTV (mobule: LBSC, DMAC) */ 223 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
226 GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, 224 GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
227 GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, 225 GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
228 GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1, 226 GPIO_FN_COM2_RI, GPIO_FN_R_SPI_MOSI, GPIO_FN_R_SPI_MISO,
227 GPIO_FN_R_SPI_RSPCK, GPIO_FN_R_SPI_SSL0, GPIO_FN_R_SPI_SSL1,
228 GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_VBIOS_DI,
229 GPIO_FN_VBIOS_DO, GPIO_FN_VBIOS_CLK, GPIO_FN_VBIOS_CS,
229 230
230 /* PTW (mobule: LBSC) */ 231 /* PTW (mobule: LBSC, EVC, SCIF) */
231 GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, 232 GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
232 GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, 233 GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
234 GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2,
235 GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4, GPIO_FN_CTS2,
233 236
234 /* PTX (mobule: LBSC) */ 237 /* PTX (mobule: LBSC, SCIF, SIM) */
235 GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, 238 GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
236 GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, 239 GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
240 GPIO_FN_RTS2, GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
237 241
238 /* PTY (mobule: LBSC) */ 242 /* PTY (mobule: LBSC) */
239 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, 243 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
240 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, 244 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
245
246 /* PTZ (mobule: eMMC, ONFI) */
247 GPIO_FN_MMCDAT7, GPIO_FN_MMCDAT6, GPIO_FN_MMCDAT5,
248 GPIO_FN_MMCDAT4, GPIO_FN_MMCDAT3, GPIO_FN_MMCDAT2,
249 GPIO_FN_MMCDAT1, GPIO_FN_MMCDAT0,
250 GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4,
251 GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0,
241}; 252};
242 253
243#endif /* __ASM_SH7757_H__ */ 254#endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/shx3.h b/arch/sh/include/cpu-sh4/cpu/shx3.h
new file mode 100644
index 000000000000..68d9080a8da9
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/shx3.h
@@ -0,0 +1,64 @@
1#ifndef __CPU_SHX3_H
2#define __CPU_SHX3_H
3
4enum {
5 /* PA */
6 GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
7 GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
8
9 /* PB */
10 GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
11 GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
12
13 /* PC */
14 GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
15 GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
16
17 /* PD */
18 GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
19 GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
20
21 /* PE */
22 GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
23 GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
24
25 /* PF */
26 GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
27 GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
28
29 /* PG */
30 GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
31 GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
32
33 /* PH */
34 GPIO_PH5, GPIO_PH4,
35 GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
36
37 /* SCIF */
38 GPIO_FN_SCK3, GPIO_FN_TXD3, GPIO_FN_RXD3,
39 GPIO_FN_SCK2, GPIO_FN_TXD2, GPIO_FN_RXD2,
40 GPIO_FN_SCK1, GPIO_FN_TXD1, GPIO_FN_RXD1,
41 GPIO_FN_SCK0, GPIO_FN_TXD0, GPIO_FN_RXD0,
42
43 /* LBSC */
44 GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
45 GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
46 GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
47 GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
48 GPIO_FN_WE3, GPIO_FN_WE2, GPIO_FN_CS6, GPIO_FN_CS5,
49 GPIO_FN_CS4, GPIO_FN_CLKOUTENB, GPIO_FN_BREQ,
50 GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK,
51
52 /* DMAC */
53 GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0,
54 GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1,
55 GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2,
56 GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3,
57
58 /* INTC */
59 GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
60 GPIO_FN_IRL3, GPIO_FN_IRL2, GPIO_FN_IRL1, GPIO_FN_IRL0,
61 GPIO_FN_IRQOUT, GPIO_FN_STATUS1, GPIO_FN_STATUS0,
62};
63
64#endif /* __CPU_SHX3_H */
diff --git a/arch/sh/include/mach-common/mach/sh2007.h b/arch/sh/include/mach-common/mach/sh2007.h
new file mode 100644
index 000000000000..48180b9aa03d
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh2007.h
@@ -0,0 +1,117 @@
1#ifndef __MACH_SH2007_H
2#define __MACH_SH2007_H
3
4#define CS5BCR 0xff802050
5#define CS5WCR 0xff802058
6#define CS5PCR 0xff802070
7
8#define BUS_SZ8 1
9#define BUS_SZ16 2
10#define BUS_SZ32 3
11
12#define PCMCIA_IODYN 1
13#define PCMCIA_ATA 0
14#define PCMCIA_IO8 2
15#define PCMCIA_IO16 3
16#define PCMCIA_COMM8 4
17#define PCMCIA_COMM16 5
18#define PCMCIA_ATTR8 6
19#define PCMCIA_ATTR16 7
20
21#define TYPE_SRAM 0
22#define TYPE_PCMCIA 4
23
24/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
25#define IWW5 0
26#define IWW6 3
27/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
28#define IWRWD5 2
29#define IWRWD6 2
30/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31#define IWRWS5 2
32#define IWRWS6 2
33/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
34#define IWRRD5 2
35#define IWRRD6 2
36/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37#define IWRRS5 0
38#define IWRRS6 2
39/* burst count (0-3:4,8,16,32) */
40#define BST5 0
41#define BST6 0
42/* bus size */
43#define SZ5 BUS_SZ16
44#define SZ6 BUS_SZ16
45/* RD hold for SRAM (0-1:0,1) */
46#define RDSPL5 0
47#define RDSPL6 0
48/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
49#define BW5 0
50#define BW6 0
51/* Multiplex (0-1:0,1) */
52#define MPX5 0
53#define MPX6 0
54/* device type */
55#define TYPE5 TYPE_PCMCIA
56#define TYPE6 TYPE_PCMCIA
57/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
58#define ADS5 0
59#define ADS6 0
60/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
61#define ADH5 0
62#define ADH6 0
63/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
64#define RDS5 0
65#define RDS6 0
66/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
67#define RDH5 0
68#define RDH6 0
69/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
70#define WTS5 0
71#define WTS6 0
72/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
73#define WTH5 0
74#define WTH6 0
75/* BS hold (0-1:1,2) */
76#define BSH5 0
77#define BSH6 0
78/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
79#define IW5 6 /* 60ns PIO mode 4 */
80#define IW6 15 /* 250ns */
81
82#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */
83#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */
84#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */
85#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */
86/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
87#define PCIW5 12
88/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
89#define TEDA5 2
90/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
91#define TEDB5 4
92/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
93#define TEHA5 2
94/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
95#define TEHB5 3
96
97#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \
98 (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \
99 (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
100#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \
101 (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5)
102#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \
103 (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \
104 (TEDB5<<8)|(TEHA5<<4)|TEHB5)
105
106#define SMC0_BASE 0xb0800000 /* eth0 */
107#define SMC1_BASE 0xb0900000 /* eth1 */
108#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */
109#define IDE_BASE 0xb4000000 /* IDE */
110#define PC104_IO_BASE 0xb8000000
111#define PC104_MEM_BASE 0xba000000
112#define SMC_IO_SIZE 0x100
113
114#define CF_OFFSET 0x1f0
115#define IDE_OFFSET 0x170
116
117#endif /* __MACH_SH2007_H */
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
index 416b621d94d1..40f0c2d3690c 100644
--- a/arch/sh/include/mach-sdk7786/mach/fpga.h
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -31,11 +31,35 @@
31#define EXTASR 0x110 31#define EXTASR 0x110
32#define SPCAR 0x120 32#define SPCAR 0x120
33#define INTMSR 0x130 33#define INTMSR 0x130
34
34#define PCIECR 0x140 35#define PCIECR 0x140
36#define PCIECR_PCIEMUX1 BIT(15)
37#define PCIECR_PCIEMUX0 BIT(14)
38#define PCIECR_PRST4 BIT(12) /* slot 4 card present */
39#define PCIECR_PRST3 BIT(11) /* slot 3 card present */
40#define PCIECR_PRST2 BIT(10) /* slot 2 card present */
41#define PCIECR_PRST1 BIT(9) /* slot 1 card present */
42#define PCIECR_CLKEN BIT(4) /* oscillator enable */
43
35#define FAER 0x150 44#define FAER 0x150
36#define USRGPIR 0x160 45#define USRGPIR 0x160
46
37/* 0x170 reserved */ 47/* 0x170 reserved */
38#define LCLASR 0x180 48
49#define LCLASR 0x180
50#define LCLASR_FRAMEN BIT(15)
51
52#define LCLASR_FPGA_SEL_SHIFT 12
53#define LCLASR_NAND_SEL_SHIFT 8
54#define LCLASR_NORB_SEL_SHIFT 4
55#define LCLASR_NORA_SEL_SHIFT 0
56
57#define LCLASR_AREA_MASK 0x7
58
59#define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
60#define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
61#define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
62#define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
39 63
40#define SBCR 0x190 64#define SBCR 0x190
41#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ 65#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
diff --git a/arch/sh/include/mach-x3proto/mach/hardware.h b/arch/sh/include/mach-x3proto/mach/hardware.h
new file mode 100644
index 000000000000..52bca57bfeb6
--- /dev/null
+++ b/arch/sh/include/mach-x3proto/mach/hardware.h
@@ -0,0 +1,12 @@
1#ifndef __MACH_X3PROTO_HARDWARE_H
2#define __MACH_X3PROTO_HARDWARE_H
3
4struct gpio_chip;
5
6/* arch/sh/boards/mach-x3proto/gpio.c */
7int x3proto_gpio_setup(void);
8extern struct gpio_chip x3proto_gpio_chip;
9
10#define NR_BASEBOARD_GPIOS 16
11
12#endif /* __MACH_X3PROTO_HARDWARE_H */
diff --git a/arch/sh/include/asm/ilsel.h b/arch/sh/include/mach-x3proto/mach/ilsel.h
index e3d304b280f6..e3d304b280f6 100644
--- a/arch/sh/include/asm/ilsel.h
+++ b/arch/sh/include/mach-x3proto/mach/ilsel.h
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 08:06:21 -0500