diff options
Diffstat (limited to 'arch/sh/include')
| -rw-r--r-- | arch/sh/include/cpu-sh2/cpu/cache.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/cache.h | 4 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/cache.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/cache.h | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h index 673515bc4135..aa1b2b9088a7 100644 --- a/arch/sh/include/cpu-sh2/cpu/cache.h +++ b/arch/sh/include/cpu-sh2/cpu/cache.h | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #define SH_CACHE_ASSOC 8 | 18 | #define SH_CACHE_ASSOC 8 |
| 19 | 19 | ||
| 20 | #if defined(CONFIG_CPU_SUBTYPE_SH7619) | 20 | #if defined(CONFIG_CPU_SUBTYPE_SH7619) |
| 21 | #define CCR 0xffffffec | 21 | #define SH_CCR 0xffffffec |
| 22 | 22 | ||
| 23 | #define CCR_CACHE_CE 0x01 /* Cache enable */ | 23 | #define CCR_CACHE_CE 0x01 /* Cache enable */ |
| 24 | #define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ | 24 | #define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ |
diff --git a/arch/sh/include/cpu-sh2a/cpu/cache.h b/arch/sh/include/cpu-sh2a/cpu/cache.h index defb0baa5a06..b27ce92cb600 100644 --- a/arch/sh/include/cpu-sh2a/cpu/cache.h +++ b/arch/sh/include/cpu-sh2a/cpu/cache.h | |||
| @@ -17,8 +17,8 @@ | |||
| 17 | #define SH_CACHE_COMBINED 4 | 17 | #define SH_CACHE_COMBINED 4 |
| 18 | #define SH_CACHE_ASSOC 8 | 18 | #define SH_CACHE_ASSOC 8 |
| 19 | 19 | ||
| 20 | #define CCR 0xfffc1000 /* CCR1 */ | 20 | #define SH_CCR 0xfffc1000 /* CCR1 */ |
| 21 | #define CCR2 0xfffc1004 | 21 | #define SH_CCR2 0xfffc1004 |
| 22 | 22 | ||
| 23 | /* | 23 | /* |
| 24 | * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not | 24 | * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not |
diff --git a/arch/sh/include/cpu-sh3/cpu/cache.h b/arch/sh/include/cpu-sh3/cpu/cache.h index bee2d81c56bf..29700fd88c75 100644 --- a/arch/sh/include/cpu-sh3/cpu/cache.h +++ b/arch/sh/include/cpu-sh3/cpu/cache.h | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #define SH_CACHE_COMBINED 4 | 17 | #define SH_CACHE_COMBINED 4 |
| 18 | #define SH_CACHE_ASSOC 8 | 18 | #define SH_CACHE_ASSOC 8 |
| 19 | 19 | ||
| 20 | #define CCR 0xffffffec /* Address of Cache Control Register */ | 20 | #define SH_CCR 0xffffffec /* Address of Cache Control Register */ |
| 21 | 21 | ||
| 22 | #define CCR_CACHE_CE 0x01 /* Cache Enable */ | 22 | #define CCR_CACHE_CE 0x01 /* Cache Enable */ |
| 23 | #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ | 23 | #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ |
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h index 7bfb9e8b069c..92c4cd119b66 100644 --- a/arch/sh/include/cpu-sh4/cpu/cache.h +++ b/arch/sh/include/cpu-sh4/cpu/cache.h | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #define SH_CACHE_COMBINED 4 | 17 | #define SH_CACHE_COMBINED 4 |
| 18 | #define SH_CACHE_ASSOC 8 | 18 | #define SH_CACHE_ASSOC 8 |
| 19 | 19 | ||
| 20 | #define CCR 0xff00001c /* Address of Cache Control Register */ | 20 | #define SH_CCR 0xff00001c /* Address of Cache Control Register */ |
| 21 | #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ | 21 | #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ |
| 22 | #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ | 22 | #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ |
| 23 | #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ | 23 | #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ |