9 files changed, 109 insertions, 46 deletions

diff --git a/arch/sh/include/asm/a.out.h b/arch/sh/include/asm/a.out.h
deleted file mode 100644
index 1f93130e179c..000000000000
--- a/arch/sh/include/asm/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_SH_A_OUT_H
-#define __ASM_SH_A_OUT_H
-
-struct exec
-{
-  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif /* __ASM_SH_A_OUT_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 643ab5a7cf3b..b86aeabba61a 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -104,6 +104,15 @@ struct pt_dspregs {
 
 extern void show_regs(struct pt_regs *);
 
+/*
+ * These are defined as per linux/ptrace.h.
+ */
+struct task_struct;
+
+#define arch_has_single_step()  (1)
+extern void user_enable_single_step(struct task_struct *);
+extern void user_disable_single_step(struct task_struct *);
+
 #ifdef CONFIG_SH_DSP
 #define task_pt_regs(task) \
         ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
diff --git a/arch/sh/include/asm/seccomp.h b/arch/sh/include/asm/seccomp.h
new file mode 100644
index 000000000000..3280ed3802ef
--- /dev/null
+++ b/arch/sh/include/asm/seccomp.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#endif /* __ASM_SECCOMP_H */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index eeb4c747119e..0a894cafb1dd 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -117,24 +117,45 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NEED_RESCHED        2       /* rescheduling necessary */
 #define TIF_RESTORE_SIGMASK     3       /* restore signal mask in do_signal() */
 #define TIF_SINGLESTEP          4       /* singlestepping active */
-#define TIF_SYSCALL_AUDIT       5
+#define TIF_SYSCALL_AUDIT       5       /* syscall auditing active */
+#define TIF_SECCOMP             6       /* secure computing */
+#define TIF_NOTIFY_RESUME       7       /* callback before returning to user */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
 #define TIF_MEMDIE              18
-#define TIF_FREEZE              19
-
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
-#define _TIF_SYSCALL_AUDIT              (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
-
-#define _TIF_WORK_MASK          0x000000FE      /* work to do on interrupt/exception return */
-#define _TIF_ALLWORK_MASK       0x000000FF      /* work to do on any return to u-space */
+#define TIF_FREEZE              19      /* Freezing for suspend */
+
+#define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
+#define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
+#define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_USEDFPU            (1 << TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE             (1 << TIF_FREEZE)
+
+/*
+ * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within a byte, or we
+ * blow the tst immediate size constraints and need to fix up
+ * arch/sh/kernel/entry-common.S.
+ */
+
+/* work to do in syscall trace */
+#define _TIF_WORK_SYSCALL_MASK  (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
+                                 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP)
+
+/* work to do on any return to u-space */
+#define _TIF_ALLWORK_MASK       (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING      | \
+                                 _TIF_NEED_RESCHED  | _TIF_SYSCALL_AUDIT   | \
+                                 _TIF_SINGLESTEP    | _TIF_RESTORE_SIGMASK | \
+                                 _TIF_NOTIFY_RESUME)
+
+/* work to do on interrupt/exception return */
+#define _TIF_WORK_MASK          (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \
+                                 _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP))
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/sh/include/asm/tlb_64.h b/arch/sh/include/asm/tlb_64.h
index 0a96f3af69e3..ef0ae2a28f23 100644
--- a/arch/sh/include/asm/tlb_64.h
+++ b/arch/sh/include/asm/tlb_64.h
@@ -21,11 +21,9 @@
 #ifndef __ASSEMBLY__
 
 /**
- * for_each_dtlb_entry
+ * for_each_dtlb_entry - Iterate over free (non-wired) DTLB entries
  *
  * @tlb:        TLB entry
- *
- * Iterate over free (non-wired) DTLB entries
  */
 #define for_each_dtlb_entry(tlb)                \
         for (tlb  = cpu_data->dtlb.first;       \
@@ -33,11 +31,9 @@
              tlb += cpu_data->dtlb.step)
 
 /**
- * for_each_itlb_entry
+ * for_each_itlb_entry - Iterate over free (non-wired) ITLB entries
  *
  * @tlb:        TLB entry
- *
- * Iterate over free (non-wired) ITLB entries
  */
 #define for_each_itlb_entry(tlb)                \
         for (tlb  = cpu_data->itlb.first;       \
@@ -45,11 +41,9 @@
              tlb += cpu_data->itlb.step)
 
 /**
- * __flush_tlb_slot
+ * __flush_tlb_slot - Flushes TLB slot @slot.
  *
  * @slot:       Address of TLB slot.
- *
- * Flushes TLB slot @slot.
  */
 static inline void __flush_tlb_slot(unsigned long long slot)
 {
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h
index 4e0b16500686..673515bc4135 100644
--- a/arch/sh/include/cpu-sh2/cpu/cache.h
+++ b/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -21,11 +21,11 @@
 #define CCR             0xffffffec
 
 #define CCR_CACHE_CE    0x01    /* Cache enable */
-#define CCR_CACHE_WT    0x06    /* CCR[bit1=1,bit2=1] */
+#define CCR_CACHE_WT    0x02    /* CCR[bit1=1,bit2=1] */
                                 /* 0x00000000-0x7fffffff: Write-through  */
                                 /* 0x80000000-0x9fffffff: Write-back     */
                                 /* 0xc0000000-0xdfffffff: Write-through  */
-#define CCR_CACHE_CB    0x00    /* CCR[bit1=0,bit2=0] */
+#define CCR_CACHE_CB    0x04    /* CCR[bit1=0,bit2=0] */
                                 /* 0x00000000-0x7fffffff: Write-back     */
                                 /* 0x80000000-0x9fffffff: Write-through  */
                                 /* 0xc0000000-0xdfffffff: Write-back     */
@@ -36,6 +36,8 @@
 
 #define CCR_CACHE_ENABLE        CCR_CACHE_CE
 #define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+#define CACHE_PHYSADDR_MASK     0x1ffffc00
+
 #endif
 
 #endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/addrspace.h b/arch/sh/include/cpu-sh2a/cpu/addrspace.h
new file mode 100644
index 000000000000..31eb4b58aa6d
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/addrspace.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H
+#define __ASM_SH_CPU_SH2A_ADDRSPACE_H
+
+#define P0SEG           0x00000000
+#define P1SEG           0x00000000
+#define P2SEG           0x20000000
+#define P3SEG           0x40000000
+#define P4SEG           0x60000000
+
+#endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/cache.h b/arch/sh/include/cpu-sh2a/cpu/cache.h
index afe228b3f493..defb0baa5a06 100644
--- a/arch/sh/include/cpu-sh2a/cpu/cache.h
+++ b/arch/sh/include/cpu-sh2a/cpu/cache.h
@@ -36,5 +36,8 @@
 
 #define CCR_CACHE_ENABLE        (CCR_CACHE_OCE | CCR_CACHE_ICE)
 #define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI | CCR_CACHE_ICI)
+#define CCR_ICACHE_INVALIDATE   CCR_CACHE_ICI
+#define CCR_OCACHE_INVALIDATE   CCR_CACHE_OCI
+#define CACHE_PHYSADDR_MASK     0x1ffffc00
 
 #endif /* __ASM_CPU_SH2A_CACHE_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
new file mode 100644
index 000000000000..3d3b9205d2ac
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H
+#define __ASM_CPU_SH2A_CACHEFLUSH_H
+
+/* 
+ * Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_dup mm(mm) handles cache flushing when forking
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *  - flush_icache_range(start, end) flushes(invalidates) a range for icache
+ *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
+ *
+ *  Caches are indexed (effectively) by physical address on SH-2, so
+ *  we don't need them.
+ */
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_sigtramp(vaddr)             do { } while (0)
+
+#define p3_cache_init()                         do { } while (0)
+#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */