aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/addrspace.h4
-rw-r--r--arch/sh/include/asm/atomic-irq.h16
-rw-r--r--arch/sh/include/asm/bitops-llsc.h72
-rw-r--r--arch/sh/include/asm/clock.h1
-rw-r--r--arch/sh/include/asm/cmpxchg-llsc.h38
-rw-r--r--arch/sh/include/asm/cpu-features.h1
-rw-r--r--arch/sh/include/asm/dma-sh.h118
-rw-r--r--arch/sh/include/asm/dma.h4
-rw-r--r--arch/sh/include/asm/entry-macros.S5
-rw-r--r--arch/sh/include/asm/gpio.h70
-rw-r--r--arch/sh/include/asm/hd64461.h1
-rw-r--r--arch/sh/include/asm/io.h4
-rw-r--r--arch/sh/include/asm/kprobes.h2
-rw-r--r--arch/sh/include/asm/mmu_context.h15
-rw-r--r--arch/sh/include/asm/mmu_context_32.h12
-rw-r--r--arch/sh/include/asm/page.h7
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/asm/processor_32.h15
-rw-r--r--arch/sh/include/asm/processor_64.h14
-rw-r--r--arch/sh/include/asm/ptrace.h8
-rw-r--r--arch/sh/include/asm/sections.h1
-rw-r--r--arch/sh/include/asm/suspend.h22
-rw-r--r--arch/sh/include/asm/timer.h4
-rw-r--r--arch/sh/include/asm/tlb.h100
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h17
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h94
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh7780.h39
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h30
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/mmu_context.h35
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7786.h192
-rw-r--r--arch/sh/include/mach-common/mach/urquell.h68
32 files changed, 794 insertions, 221 deletions
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
index 36736c7e93db..80d40813e057 100644
--- a/arch/sh/include/asm/addrspace.h
+++ b/arch/sh/include/asm/addrspace.h
@@ -31,7 +31,7 @@
31/* Returns the physical address of a PnSEG (n=1,2) address */ 31/* Returns the physical address of a PnSEG (n=1,2) address */
32#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) 32#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
33 33
34#ifdef CONFIG_29BIT 34#if defined(CONFIG_29BIT) || defined(CONFIG_PMB_FIXED)
35/* 35/*
36 * Map an address to a certain privileged segment 36 * Map an address to a certain privileged segment
37 */ 37 */
@@ -43,7 +43,7 @@
43 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) 43 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
44#define P4SEGADDR(a) \ 44#define P4SEGADDR(a) \
45 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) 45 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
46#endif /* 29BIT */ 46#endif /* 29BIT || PMB_FIXED */
47#endif /* P1SEG */ 47#endif /* P1SEG */
48 48
49/* Check if an address can be reached in 29 bits */ 49/* Check if an address can be reached in 29 bits */
diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-irq.h
index 74f7943cff6f..a0b348068cae 100644
--- a/arch/sh/include/asm/atomic-irq.h
+++ b/arch/sh/include/asm/atomic-irq.h
@@ -11,7 +11,7 @@ static inline void atomic_add(int i, atomic_t *v)
11 unsigned long flags; 11 unsigned long flags;
12 12
13 local_irq_save(flags); 13 local_irq_save(flags);
14 *(long *)v += i; 14 v->counter += i;
15 local_irq_restore(flags); 15 local_irq_restore(flags);
16} 16}
17 17
@@ -20,7 +20,7 @@ static inline void atomic_sub(int i, atomic_t *v)
20 unsigned long flags; 20 unsigned long flags;
21 21
22 local_irq_save(flags); 22 local_irq_save(flags);
23 *(long *)v -= i; 23 v->counter -= i;
24 local_irq_restore(flags); 24 local_irq_restore(flags);
25} 25}
26 26
@@ -29,9 +29,9 @@ static inline int atomic_add_return(int i, atomic_t *v)
29 unsigned long temp, flags; 29 unsigned long temp, flags;
30 30
31 local_irq_save(flags); 31 local_irq_save(flags);
32 temp = *(long *)v; 32 temp = v->counter;
33 temp += i; 33 temp += i;
34 *(long *)v = temp; 34 v->counter = temp;
35 local_irq_restore(flags); 35 local_irq_restore(flags);
36 36
37 return temp; 37 return temp;
@@ -42,9 +42,9 @@ static inline int atomic_sub_return(int i, atomic_t *v)
42 unsigned long temp, flags; 42 unsigned long temp, flags;
43 43
44 local_irq_save(flags); 44 local_irq_save(flags);
45 temp = *(long *)v; 45 temp = v->counter;
46 temp -= i; 46 temp -= i;
47 *(long *)v = temp; 47 v->counter = temp;
48 local_irq_restore(flags); 48 local_irq_restore(flags);
49 49
50 return temp; 50 return temp;
@@ -55,7 +55,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
55 unsigned long flags; 55 unsigned long flags;
56 56
57 local_irq_save(flags); 57 local_irq_save(flags);
58 *(long *)v &= ~mask; 58 v->counter &= ~mask;
59 local_irq_restore(flags); 59 local_irq_restore(flags);
60} 60}
61 61
@@ -64,7 +64,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
64 unsigned long flags; 64 unsigned long flags;
65 65
66 local_irq_save(flags); 66 local_irq_save(flags);
67 *(long *)v |= mask; 67 v->counter |= mask;
68 local_irq_restore(flags); 68 local_irq_restore(flags);
69} 69}
70 70
diff --git a/arch/sh/include/asm/bitops-llsc.h b/arch/sh/include/asm/bitops-llsc.h
index 1d2fc0b010ad..d8328be06191 100644
--- a/arch/sh/include/asm/bitops-llsc.h
+++ b/arch/sh/include/asm/bitops-llsc.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_SH_BITOPS_LLSC_H 1#ifndef __ASM_SH_BITOPS_LLSC_H
2#define __ASM_SH_BITOPS_LLSC_H 2#define __ASM_SH_BITOPS_LLSC_H
3 3
4static inline void set_bit(int nr, volatile void * addr) 4static inline void set_bit(int nr, volatile void *addr)
5{ 5{
6 int mask; 6 int mask;
7 volatile unsigned int *a = addr; 7 volatile unsigned int *a = addr;
@@ -13,16 +13,16 @@ static inline void set_bit(int nr, volatile void * addr)
13 __asm__ __volatile__ ( 13 __asm__ __volatile__ (
14 "1: \n\t" 14 "1: \n\t"
15 "movli.l @%1, %0 ! set_bit \n\t" 15 "movli.l @%1, %0 ! set_bit \n\t"
16 "or %3, %0 \n\t" 16 "or %2, %0 \n\t"
17 "movco.l %0, @%1 \n\t" 17 "movco.l %0, @%1 \n\t"
18 "bf 1b \n\t" 18 "bf 1b \n\t"
19 : "=&z" (tmp), "=r" (a) 19 : "=&z" (tmp)
20 : "1" (a), "r" (mask) 20 : "r" (a), "r" (mask)
21 : "t", "memory" 21 : "t", "memory"
22 ); 22 );
23} 23}
24 24
25static inline void clear_bit(int nr, volatile void * addr) 25static inline void clear_bit(int nr, volatile void *addr)
26{ 26{
27 int mask; 27 int mask;
28 volatile unsigned int *a = addr; 28 volatile unsigned int *a = addr;
@@ -34,16 +34,16 @@ static inline void clear_bit(int nr, volatile void * addr)
34 __asm__ __volatile__ ( 34 __asm__ __volatile__ (
35 "1: \n\t" 35 "1: \n\t"
36 "movli.l @%1, %0 ! clear_bit \n\t" 36 "movli.l @%1, %0 ! clear_bit \n\t"
37 "and %3, %0 \n\t" 37 "and %2, %0 \n\t"
38 "movco.l %0, @%1 \n\t" 38 "movco.l %0, @%1 \n\t"
39 "bf 1b \n\t" 39 "bf 1b \n\t"
40 : "=&z" (tmp), "=r" (a) 40 : "=&z" (tmp)
41 : "1" (a), "r" (~mask) 41 : "r" (a), "r" (~mask)
42 : "t", "memory" 42 : "t", "memory"
43 ); 43 );
44} 44}
45 45
46static inline void change_bit(int nr, volatile void * addr) 46static inline void change_bit(int nr, volatile void *addr)
47{ 47{
48 int mask; 48 int mask;
49 volatile unsigned int *a = addr; 49 volatile unsigned int *a = addr;
@@ -55,16 +55,16 @@ static inline void change_bit(int nr, volatile void * addr)
55 __asm__ __volatile__ ( 55 __asm__ __volatile__ (
56 "1: \n\t" 56 "1: \n\t"
57 "movli.l @%1, %0 ! change_bit \n\t" 57 "movli.l @%1, %0 ! change_bit \n\t"
58 "xor %3, %0 \n\t" 58 "xor %2, %0 \n\t"
59 "movco.l %0, @%1 \n\t" 59 "movco.l %0, @%1 \n\t"
60 "bf 1b \n\t" 60 "bf 1b \n\t"
61 : "=&z" (tmp), "=r" (a) 61 : "=&z" (tmp)
62 : "1" (a), "r" (mask) 62 : "r" (a), "r" (mask)
63 : "t", "memory" 63 : "t", "memory"
64 ); 64 );
65} 65}
66 66
67static inline int test_and_set_bit(int nr, volatile void * addr) 67static inline int test_and_set_bit(int nr, volatile void *addr)
68{ 68{
69 int mask, retval; 69 int mask, retval;
70 volatile unsigned int *a = addr; 70 volatile unsigned int *a = addr;
@@ -75,21 +75,21 @@ static inline int test_and_set_bit(int nr, volatile void * addr)
75 75
76 __asm__ __volatile__ ( 76 __asm__ __volatile__ (
77 "1: \n\t" 77 "1: \n\t"
78 "movli.l @%1, %0 ! test_and_set_bit \n\t" 78 "movli.l @%2, %0 ! test_and_set_bit \n\t"
79 "mov %0, %2 \n\t" 79 "mov %0, %1 \n\t"
80 "or %4, %0 \n\t" 80 "or %3, %0 \n\t"
81 "movco.l %0, @%1 \n\t" 81 "movco.l %0, @%2 \n\t"
82 "bf 1b \n\t" 82 "bf 1b \n\t"
83 "and %4, %2 \n\t" 83 "and %3, %1 \n\t"
84 : "=&z" (tmp), "=r" (a), "=&r" (retval) 84 : "=&z" (tmp), "=&r" (retval)
85 : "1" (a), "r" (mask) 85 : "r" (a), "r" (mask)
86 : "t", "memory" 86 : "t", "memory"
87 ); 87 );
88 88
89 return retval != 0; 89 return retval != 0;
90} 90}
91 91
92static inline int test_and_clear_bit(int nr, volatile void * addr) 92static inline int test_and_clear_bit(int nr, volatile void *addr)
93{ 93{
94 int mask, retval; 94 int mask, retval;
95 volatile unsigned int *a = addr; 95 volatile unsigned int *a = addr;
@@ -100,22 +100,22 @@ static inline int test_and_clear_bit(int nr, volatile void * addr)
100 100
101 __asm__ __volatile__ ( 101 __asm__ __volatile__ (
102 "1: \n\t" 102 "1: \n\t"
103 "movli.l @%1, %0 ! test_and_clear_bit \n\t" 103 "movli.l @%2, %0 ! test_and_clear_bit \n\t"
104 "mov %0, %2 \n\t" 104 "mov %0, %1 \n\t"
105 "and %5, %0 \n\t" 105 "and %4, %0 \n\t"
106 "movco.l %0, @%1 \n\t" 106 "movco.l %0, @%2 \n\t"
107 "bf 1b \n\t" 107 "bf 1b \n\t"
108 "and %4, %2 \n\t" 108 "and %3, %1 \n\t"
109 "synco \n\t" 109 "synco \n\t"
110 : "=&z" (tmp), "=r" (a), "=&r" (retval) 110 : "=&z" (tmp), "=&r" (retval)
111 : "1" (a), "r" (mask), "r" (~mask) 111 : "r" (a), "r" (mask), "r" (~mask)
112 : "t", "memory" 112 : "t", "memory"
113 ); 113 );
114 114
115 return retval != 0; 115 return retval != 0;
116} 116}
117 117
118static inline int test_and_change_bit(int nr, volatile void * addr) 118static inline int test_and_change_bit(int nr, volatile void *addr)
119{ 119{
120 int mask, retval; 120 int mask, retval;
121 volatile unsigned int *a = addr; 121 volatile unsigned int *a = addr;
@@ -126,15 +126,15 @@ static inline int test_and_change_bit(int nr, volatile void * addr)
126 126
127 __asm__ __volatile__ ( 127 __asm__ __volatile__ (
128 "1: \n\t" 128 "1: \n\t"
129 "movli.l @%1, %0 ! test_and_change_bit \n\t" 129 "movli.l @%2, %0 ! test_and_change_bit \n\t"
130 "mov %0, %2 \n\t" 130 "mov %0, %1 \n\t"
131 "xor %4, %0 \n\t" 131 "xor %3, %0 \n\t"
132 "movco.l %0, @%1 \n\t" 132 "movco.l %0, @%2 \n\t"
133 "bf 1b \n\t" 133 "bf 1b \n\t"
134 "and %4, %2 \n\t" 134 "and %3, %1 \n\t"
135 "synco \n\t" 135 "synco \n\t"
136 : "=&z" (tmp), "=r" (a), "=&r" (retval) 136 : "=&z" (tmp), "=&r" (retval)
137 : "1" (a), "r" (mask) 137 : "r" (a), "r" (mask)
138 : "t", "memory" 138 : "t", "memory"
139 ); 139 );
140 140
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index f9c88583d90a..2f6c9627bc1f 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -15,6 +15,7 @@ struct clk_ops {
15 void (*disable)(struct clk *clk); 15 void (*disable)(struct clk *clk);
16 void (*recalc)(struct clk *clk); 16 void (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent);
18 long (*round_rate)(struct clk *clk, unsigned long rate); 19 long (*round_rate)(struct clk *clk, unsigned long rate);
19}; 20};
20 21
diff --git a/arch/sh/include/asm/cmpxchg-llsc.h b/arch/sh/include/asm/cmpxchg-llsc.h
index aee3bf286581..0fac3da536ca 100644
--- a/arch/sh/include/asm/cmpxchg-llsc.h
+++ b/arch/sh/include/asm/cmpxchg-llsc.h
@@ -8,14 +8,14 @@ static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
8 8
9 __asm__ __volatile__ ( 9 __asm__ __volatile__ (
10 "1: \n\t" 10 "1: \n\t"
11 "movli.l @%1, %0 ! xchg_u32 \n\t" 11 "movli.l @%2, %0 ! xchg_u32 \n\t"
12 "mov %0, %2 \n\t" 12 "mov %0, %1 \n\t"
13 "mov %4, %0 \n\t" 13 "mov %3, %0 \n\t"
14 "movco.l %0, @%1 \n\t" 14 "movco.l %0, @%2 \n\t"
15 "bf 1b \n\t" 15 "bf 1b \n\t"
16 "synco \n\t" 16 "synco \n\t"
17 : "=&z"(tmp), "=r" (m), "=&r" (retval) 17 : "=&z"(tmp), "=&r" (retval)
18 : "1" (m), "r" (val) 18 : "r" (m), "r" (val)
19 : "t", "memory" 19 : "t", "memory"
20 ); 20 );
21 21
@@ -29,14 +29,14 @@ static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
29 29
30 __asm__ __volatile__ ( 30 __asm__ __volatile__ (
31 "1: \n\t" 31 "1: \n\t"
32 "movli.l @%1, %0 ! xchg_u8 \n\t" 32 "movli.l @%2, %0 ! xchg_u8 \n\t"
33 "mov %0, %2 \n\t" 33 "mov %0, %1 \n\t"
34 "mov %4, %0 \n\t" 34 "mov %3, %0 \n\t"
35 "movco.l %0, @%1 \n\t" 35 "movco.l %0, @%2 \n\t"
36 "bf 1b \n\t" 36 "bf 1b \n\t"
37 "synco \n\t" 37 "synco \n\t"
38 : "=&z"(tmp), "=r" (m), "=&r" (retval) 38 : "=&z"(tmp), "=&r" (retval)
39 : "1" (m), "r" (val & 0xff) 39 : "r" (m), "r" (val & 0xff)
40 : "t", "memory" 40 : "t", "memory"
41 ); 41 );
42 42
@@ -51,17 +51,17 @@ __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
51 51
52 __asm__ __volatile__ ( 52 __asm__ __volatile__ (
53 "1: \n\t" 53 "1: \n\t"
54 "movli.l @%1, %0 ! __cmpxchg_u32 \n\t" 54 "movli.l @%2, %0 ! __cmpxchg_u32 \n\t"
55 "mov %0, %2 \n\t" 55 "mov %0, %1 \n\t"
56 "cmp/eq %2, %4 \n\t" 56 "cmp/eq %1, %3 \n\t"
57 "bf 2f \n\t" 57 "bf 2f \n\t"
58 "mov %5, %0 \n\t" 58 "mov %3, %0 \n\t"
59 "2: \n\t" 59 "2: \n\t"
60 "movco.l %0, @%1 \n\t" 60 "movco.l %0, @%2 \n\t"
61 "bf 1b \n\t" 61 "bf 1b \n\t"
62 "synco \n\t" 62 "synco \n\t"
63 : "=&z" (tmp), "=r" (m), "=&r" (retval) 63 : "=&z" (tmp), "=&r" (retval)
64 : "1" (m), "r" (old), "r" (new) 64 : "r" (m), "r" (old), "r" (new)
65 : "t", "memory" 65 : "t", "memory"
66 ); 66 );
67 67
diff --git a/arch/sh/include/asm/cpu-features.h b/arch/sh/include/asm/cpu-features.h
index 86308aa39731..694abe490edb 100644
--- a/arch/sh/include/asm/cpu-features.h
+++ b/arch/sh/include/asm/cpu-features.h
@@ -21,5 +21,6 @@
21#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ 21#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ 22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ 23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
24#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
24 25
25#endif /* __ASM_SH_CPU_FEATURES_H */ 26#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
new file mode 100644
index 000000000000..0c8f8e14622a
--- /dev/null
+++ b/arch/sh/include/asm/dma-sh.h
@@ -0,0 +1,118 @@
1/*
2 * arch/sh/include/asm/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <asm/dma.h>
15#include <cpu/dma.h>
16
17/* DMAOR contorl: The DMAOR access size is different by CPU.*/
18#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7785)
21#define dmaor_read_reg(n) \
22 (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
23 : ctrl_inw(SH_DMAC_BASE0 + DMAOR))
24#define dmaor_write_reg(n, data) \
25 (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
26 : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
27#else /* Other CPU */
28#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
29#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
30#endif
31
32static int dmte_irq_map[] __maybe_unused = {
33#if (MAX_DMA_CHANNELS >= 4)
34 DMTE0_IRQ,
35 DMTE0_IRQ + 1,
36 DMTE0_IRQ + 2,
37 DMTE0_IRQ + 3,
38#endif
39#if (MAX_DMA_CHANNELS >= 6)
40 DMTE4_IRQ,
41 DMTE4_IRQ + 1,
42#endif
43#if (MAX_DMA_CHANNELS >= 8)
44 DMTE6_IRQ,
45 DMTE6_IRQ + 1,
46#endif
47#if (MAX_DMA_CHANNELS >= 12)
48 DMTE8_IRQ,
49 DMTE9_IRQ,
50 DMTE10_IRQ,
51 DMTE11_IRQ,
52#endif
53};
54
55/* Definitions for the SuperH DMAC */
56#define REQ_L 0x00000000
57#define REQ_E 0x00080000
58#define RACK_H 0x00000000
59#define RACK_L 0x00040000
60#define ACK_R 0x00000000
61#define ACK_W 0x00020000
62#define ACK_H 0x00000000
63#define ACK_L 0x00010000
64#define DM_INC 0x00004000
65#define DM_DEC 0x00008000
66#define SM_INC 0x00001000
67#define SM_DEC 0x00002000
68#define RS_IN 0x00000200
69#define RS_OUT 0x00000300
70#define TS_BLK 0x00000040
71#define TM_BUR 0x00000020
72#define CHCR_DE 0x00000001
73#define CHCR_TE 0x00000002
74#define CHCR_IE 0x00000004
75
76/* DMAOR definitions */
77#define DMAOR_AE 0x00000004
78#define DMAOR_NMIF 0x00000002
79#define DMAOR_DME 0x00000001
80
81/*
82 * Define the default configuration for dual address memory-memory transfer.
83 * The 0x400 value represents auto-request, external->external.
84 */
85#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
86
87/* DMA base address */
88static u32 dma_base_addr[] __maybe_unused = {
89#if (MAX_DMA_CHANNELS >= 4)
90 SH_DMAC_BASE0 + 0x00, /* channel 0 */
91 SH_DMAC_BASE0 + 0x10,
92 SH_DMAC_BASE0 + 0x20,
93 SH_DMAC_BASE0 + 0x30,
94#endif
95#if (MAX_DMA_CHANNELS >= 6)
96 SH_DMAC_BASE0 + 0x50,
97 SH_DMAC_BASE0 + 0x60,
98#endif
99#if (MAX_DMA_CHANNELS >= 8)
100 SH_DMAC_BASE1 + 0x00,
101 SH_DMAC_BASE1 + 0x10,
102#endif
103#if (MAX_DMA_CHANNELS >= 12)
104 SH_DMAC_BASE1 + 0x20,
105 SH_DMAC_BASE1 + 0x30,
106 SH_DMAC_BASE1 + 0x50,
107 SH_DMAC_BASE1 + 0x60, /* channel 11 */
108#endif
109};
110
111/* DMA register */
112#define SAR 0x00
113#define DAR 0x04
114#define TCR 0x08
115#define CHCR 0x0C
116#define DMAOR 0x40
117
118#endif /* __DMA_SH_H */
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
index beca7128e2ab..6bd178473878 100644
--- a/arch/sh/include/asm/dma.h
+++ b/arch/sh/include/asm/dma.h
@@ -25,9 +25,9 @@
25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) 25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
26 26
27#ifdef CONFIG_NR_DMA_CHANNELS 27#ifdef CONFIG_NR_DMA_CHANNELS
28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) 28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
29#else 29#else
30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
31#endif 31#endif
32 32
33/* 33/*
diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
index 2dab0b8d9454..3a4752a65722 100644
--- a/arch/sh/include/asm/entry-macros.S
+++ b/arch/sh/include/asm/entry-macros.S
@@ -31,3 +31,8 @@
31#endif 31#endif
32 .endm 32 .endm
33 33
34#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
35# define PREF(x) pref @x
36#else
37# define PREF(x) nop
38#endif
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
index 90673658eb14..61f93da2c62e 100644
--- a/arch/sh/include/asm/gpio.h
+++ b/arch/sh/include/asm/gpio.h
@@ -19,8 +19,42 @@
19#include <cpu/gpio.h> 19#include <cpu/gpio.h>
20#endif 20#endif
21 21
22#define ARCH_NR_GPIOS 512
23#include <asm-generic/gpio.h>
24
25#ifdef CONFIG_GPIOLIB
26
27static inline int gpio_get_value(unsigned gpio)
28{
29 return __gpio_get_value(gpio);
30}
31
32static inline void gpio_set_value(unsigned gpio, int value)
33{
34 __gpio_set_value(gpio, value);
35}
36
37static inline int gpio_cansleep(unsigned gpio)
38{
39 return __gpio_cansleep(gpio);
40}
41
42static inline int gpio_to_irq(unsigned gpio)
43{
44 WARN_ON(1);
45 return -ENOSYS;
46}
47
48static inline int irq_to_gpio(unsigned int irq)
49{
50 WARN_ON(1);
51 return -EINVAL;
52}
53
54#endif /* CONFIG_GPIOLIB */
55
22typedef unsigned short pinmux_enum_t; 56typedef unsigned short pinmux_enum_t;
23typedef unsigned char pinmux_flag_t; 57typedef unsigned short pinmux_flag_t;
24 58
25#define PINMUX_TYPE_NONE 0 59#define PINMUX_TYPE_NONE 0
26#define PINMUX_TYPE_FUNCTION 1 60#define PINMUX_TYPE_FUNCTION 1
@@ -34,6 +68,11 @@ typedef unsigned char pinmux_flag_t;
34#define PINMUX_FLAG_WANT_PULLUP (1 << 3) 68#define PINMUX_FLAG_WANT_PULLUP (1 << 3)
35#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4) 69#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4)
36 70
71#define PINMUX_FLAG_DBIT_SHIFT 5
72#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
73#define PINMUX_FLAG_DREG_SHIFT 10
74#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
75
37struct pinmux_gpio { 76struct pinmux_gpio {
38 pinmux_enum_t enum_id; 77 pinmux_enum_t enum_id;
39 pinmux_flag_t flags; 78 pinmux_flag_t flags;
@@ -54,7 +93,7 @@ struct pinmux_cfg_reg {
54 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \ 93 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \
55 94
56struct pinmux_data_reg { 95struct pinmux_data_reg {
57 unsigned long reg, reg_width; 96 unsigned long reg, reg_width, reg_shadow;
58 pinmux_enum_t *enum_ids; 97 pinmux_enum_t *enum_ids;
59}; 98};
60 99
@@ -89,34 +128,9 @@ struct pinmux_info {
89 unsigned int gpio_data_size; 128 unsigned int gpio_data_size;
90 129
91 unsigned long *gpio_in_use; 130 unsigned long *gpio_in_use;
131 struct gpio_chip chip;
92}; 132};
93 133
94int register_pinmux(struct pinmux_info *pip); 134int register_pinmux(struct pinmux_info *pip);
95 135
96int __gpio_request(unsigned gpio);
97static inline int gpio_request(unsigned gpio, const char *label)
98{
99 return __gpio_request(gpio);
100}
101void gpio_free(unsigned gpio);
102int gpio_direction_input(unsigned gpio);
103int gpio_direction_output(unsigned gpio, int value);
104int gpio_get_value(unsigned gpio);
105void gpio_set_value(unsigned gpio, int value);
106
107/* IRQ modes are unspported */
108static inline int gpio_to_irq(unsigned gpio)
109{
110 WARN_ON(1);
111 return -EINVAL;
112}
113
114static inline int irq_to_gpio(unsigned irq)
115{
116 WARN_ON(1);
117 return -EINVAL;
118}
119
120#include <asm-generic/gpio.h>
121
122#endif /* __ASM_SH_GPIO_H */ 136#endif /* __ASM_SH_GPIO_H */
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 8c1353baf00f..52b4b6238277 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -242,7 +242,6 @@
242#include <asm/io_generic.h> 242#include <asm/io_generic.h>
243 243
244/* arch/sh/cchips/hd6446x/hd64461/setup.c */ 244/* arch/sh/cchips/hd6446x/hd64461/setup.c */
245int hd64461_irq_demux(int irq);
246void hd64461_register_irq_demux(int irq, 245void hd64461_register_irq_demux(int irq,
247 int (*demux) (int irq, void *dev), void *dev); 246 int (*demux) (int irq, void *dev), void *dev);
248void hd64461_unregister_irq_demux(int irq); 247void hd64461_unregister_irq_demux(int irq);
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 61f6dae40534..0454f8d68059 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -238,7 +238,7 @@ extern void onchip_unmap(unsigned long vaddr);
238static inline void __iomem * 238static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) 239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{ 240{
241#ifdef CONFIG_SUPERH32 241#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
242 unsigned long last_addr = offset + size - 1; 242 unsigned long last_addr = offset + size - 1;
243#endif 243#endif
244 void __iomem *ret; 244 void __iomem *ret;
@@ -247,7 +247,7 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
247 if (ret) 247 if (ret)
248 return ret; 248 return ret;
249 249
250#ifdef CONFIG_SUPERH32 250#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
251 /* 251 /*
252 * For P1 and P2 space this is trivial, as everything is already 252 * For P1 and P2 space this is trivial, as everything is already
253 * mapped. Uncached access for P1 addresses are done through P2. 253 * mapped. Uncached access for P1 addresses are done through P2.
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 6078d8e551d4..613644a758e8 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -16,7 +16,7 @@ typedef u16 kprobe_opcode_t;
16 ? (MAX_STACK_SIZE) \ 16 ? (MAX_STACK_SIZE) \
17 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) 17 : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
18 18
19#define regs_return_value(regs) ((regs)->regs[0]) 19#define regs_return_value(_regs) ((_regs)->regs[0])
20#define flush_insn_slot(p) do { } while (0) 20#define flush_insn_slot(p) do { } while (0)
21#define kretprobe_blacklist_size 0 21#define kretprobe_blacklist_size 0
22 22
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
index 5d9157bd474d..2a9c55f1a83f 100644
--- a/arch/sh/include/asm/mmu_context.h
+++ b/arch/sh/include/asm/mmu_context.h
@@ -19,13 +19,18 @@
19 * (a) TLB cache version (or round, cycle whatever expression you like) 19 * (a) TLB cache version (or round, cycle whatever expression you like)
20 * (b) ASID (Address Space IDentifier) 20 * (b) ASID (Address Space IDentifier)
21 */ 21 */
22#ifdef CONFIG_CPU_HAS_PTEAEX
23#define MMU_CONTEXT_ASID_MASK 0x0000ffff
24#else
22#define MMU_CONTEXT_ASID_MASK 0x000000ff 25#define MMU_CONTEXT_ASID_MASK 0x000000ff
23#define MMU_CONTEXT_VERSION_MASK 0xffffff00 26#endif
24#define MMU_CONTEXT_FIRST_VERSION 0x00000100
25#define NO_CONTEXT 0UL
26 27
27/* ASID is 8-bit value, so it can't be 0x100 */ 28#define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK)
28#define MMU_NO_ASID 0x100 29#define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1)
30
31/* Impossible ASID value, to differentiate from NO_CONTEXT. */
32#define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION
33#define NO_CONTEXT 0UL
29 34
30#define asid_cache(cpu) (cpu_data[cpu].asid_cache) 35#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
31 36
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h
index f4f9aebd68b7..8ef800c549ab 100644
--- a/arch/sh/include/asm/mmu_context_32.h
+++ b/arch/sh/include/asm/mmu_context_32.h
@@ -10,6 +10,17 @@ static inline void destroy_context(struct mm_struct *mm)
10 /* Do nothing */ 10 /* Do nothing */
11} 11}
12 12
13#ifdef CONFIG_CPU_HAS_PTEAEX
14static inline void set_asid(unsigned long asid)
15{
16 __raw_writel(asid, MMU_PTEAEX);
17}
18
19static inline unsigned long get_asid(void)
20{
21 return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK;
22}
23#else
13static inline void set_asid(unsigned long asid) 24static inline void set_asid(unsigned long asid)
14{ 25{
15 unsigned long __dummy; 26 unsigned long __dummy;
@@ -33,6 +44,7 @@ static inline unsigned long get_asid(void)
33 asid &= MMU_CONTEXT_ASID_MASK; 44 asid &= MMU_CONTEXT_ASID_MASK;
34 return asid; 45 return asid;
35} 46}
47#endif /* CONFIG_CPU_HAS_PTEAEX */
36 48
37/* MMU_TTB is used for optimizing the fault handling. */ 49/* MMU_TTB is used for optimizing the fault handling. */
38static inline void set_TTB(pgd_t *pgd) 50static inline void set_TTB(pgd_t *pgd)
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index 5871d78e47e5..9c6d21ec0240 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -129,7 +129,12 @@ typedef struct page *pgtable_t;
129 * is not visible (it is part of the PMB mapping) and so needs to be 129 * is not visible (it is part of the PMB mapping) and so needs to be
130 * added or subtracted as required. 130 * added or subtracted as required.
131 */ 131 */
132#ifdef CONFIG_32BIT 132#if defined(CONFIG_PMB_FIXED)
133/* phys = virt - PAGE_OFFSET - (__MEMORY_START & 0xe0000000) */
134#define PMB_OFFSET (PAGE_OFFSET - PXSEG(__MEMORY_START))
135#define __pa(x) ((unsigned long)(x) - PMB_OFFSET)
136#define __va(x) ((void *)((unsigned long)(x) + PMB_OFFSET))
137#elif defined(CONFIG_32BIT)
133#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START) 138#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
134#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START)) 139#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
135#else 140#else
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1ef4b24d7619..1fd58b421438 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -31,7 +31,7 @@ enum cpu_type {
31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501, 31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SHX3, 35 CPU_SH7723, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index d79063c5eb9c..efdd78a53b11 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -108,12 +108,12 @@ extern int ubc_usercnt;
108/* 108/*
109 * Do necessary setup to start up a newly executed thread. 109 * Do necessary setup to start up a newly executed thread.
110 */ 110 */
111#define start_thread(regs, new_pc, new_sp) \ 111#define start_thread(_regs, new_pc, new_sp) \
112 set_fs(USER_DS); \ 112 set_fs(USER_DS); \
113 regs->pr = 0; \ 113 _regs->pr = 0; \
114 regs->sr = SR_FD; /* User mode. */ \ 114 _regs->sr = SR_FD; /* User mode. */ \
115 regs->pc = new_pc; \ 115 _regs->pc = new_pc; \
116 regs->regs[15] = new_sp 116 _regs->regs[15] = new_sp
117 117
118/* Forward declaration, a strange C thing */ 118/* Forward declaration, a strange C thing */
119struct task_struct; 119struct task_struct;
@@ -189,10 +189,9 @@ extern unsigned long get_wchan(struct task_struct *p);
189#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) 189#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
190#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) 190#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
191 191
192#define user_stack_pointer(regs) ((regs)->regs[15]) 192#define user_stack_pointer(_regs) ((_regs)->regs[15])
193 193
194#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \ 194#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
195 defined(CONFIG_CPU_SH4)
196#define PREFETCH_STRIDE L1_CACHE_BYTES 195#define PREFETCH_STRIDE L1_CACHE_BYTES
197#define ARCH_HAS_PREFETCH 196#define ARCH_HAS_PREFETCH
198#define ARCH_HAS_PREFETCHW 197#define ARCH_HAS_PREFETCHW
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index 803177fcf086..5727d31b0ccf 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -145,13 +145,13 @@ struct thread_struct {
145 */ 145 */
146#define SR_USER (SR_MMU | SR_FD) 146#define SR_USER (SR_MMU | SR_FD)
147 147
148#define start_thread(regs, new_pc, new_sp) \ 148#define start_thread(_regs, new_pc, new_sp) \
149 set_fs(USER_DS); \ 149 set_fs(USER_DS); \
150 regs->sr = SR_USER; /* User mode. */ \ 150 _regs->sr = SR_USER; /* User mode. */ \
151 regs->pc = new_pc - 4; /* Compensate syscall exit */ \ 151 _regs->pc = new_pc - 4; /* Compensate syscall exit */ \
152 regs->pc |= 1; /* Set SHmedia ! */ \ 152 _regs->pc |= 1; /* Set SHmedia ! */ \
153 regs->regs[18] = 0; \ 153 _regs->regs[18] = 0; \
154 regs->regs[15] = new_sp 154 _regs->regs[15] = new_sp
155 155
156/* Forward declaration, a strange C thing */ 156/* Forward declaration, a strange C thing */
157struct task_struct; 157struct task_struct;
@@ -226,7 +226,7 @@ extern unsigned long get_wchan(struct task_struct *p);
226#define KSTK_EIP(tsk) ((tsk)->thread.pc) 226#define KSTK_EIP(tsk) ((tsk)->thread.pc)
227#define KSTK_ESP(tsk) ((tsk)->thread.sp) 227#define KSTK_ESP(tsk) ((tsk)->thread.sp)
228 228
229#define user_stack_pointer(regs) ((regs)->regs[15]) 229#define user_stack_pointer(_regs) ((_regs)->regs[15])
230 230
231#endif /* __ASSEMBLY__ */ 231#endif /* __ASSEMBLY__ */
232#endif /* __ASM_SH_PROCESSOR_64_H */ 232#endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 12912ab80c15..81c6568fdb3e 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -122,14 +122,12 @@ extern void user_disable_single_step(struct task_struct *);
122#ifdef CONFIG_SH_DSP 122#ifdef CONFIG_SH_DSP
123#define task_pt_regs(task) \ 123#define task_pt_regs(task) \
124 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ 124 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
125 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) 125 - sizeof(struct pt_dspregs)) - 1)
126#define task_pt_dspregs(task) \ 126#define task_pt_dspregs(task) \
127 ((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE \ 127 ((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE) - 1)
128 - sizeof(unsigned long)) - 1)
129#else 128#else
130#define task_pt_regs(task) \ 129#define task_pt_regs(task) \
131 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ 130 ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE) - 1)
132 - sizeof(unsigned long)) - 1)
133#endif 131#endif
134 132
135static inline unsigned long profile_pc(struct pt_regs *regs) 133static inline unsigned long profile_pc(struct pt_regs *regs)
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index 8f8f4ad400df..01a4076a3719 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -3,6 +3,7 @@
3 3
4#include <asm-generic/sections.h> 4#include <asm-generic/sections.h>
5 5
6extern void __nosave_begin, __nosave_end;
6extern long __machvec_start, __machvec_end; 7extern long __machvec_start, __machvec_end;
7extern char __uncached_start, __uncached_end; 8extern char __uncached_start, __uncached_end;
8extern char _ebss[]; 9extern char _ebss[];
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
new file mode 100644
index 000000000000..b1b995370e79
--- /dev/null
+++ b/arch/sh/include/asm/suspend.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_SH_SUSPEND_H
2#define _ASM_SH_SUSPEND_H
3
4#ifndef __ASSEMBLY__
5static inline int arch_prepare_suspend(void) { return 0; }
6
7#include <asm/ptrace.h>
8
9struct swsusp_arch_regs {
10 struct pt_regs user_regs;
11 unsigned long bank1_regs[8];
12};
13#endif
14
15/* flags passed to assembly suspend code */
16#define SUSP_SH_SLEEP (1 << 0) /* Regular sleep mode */
17#define SUSP_SH_STANDBY (1 << 1) /* SH-Mobile Software standby mode */
18#define SUSP_SH_RSTANDBY (1 << 2) /* SH-Mobile R-standby mode */
19#define SUSP_SH_USTANDBY (1 << 3) /* SH-Mobile U-standby mode */
20#define SUSP_SH_SF (1 << 4) /* Enable self-refresh */
21
22#endif /* _ASM_SH_SUSPEND_H */
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
index a7ca3a195bb5..4c3b66e30af2 100644
--- a/arch/sh/include/asm/timer.h
+++ b/arch/sh/include/asm/timer.h
@@ -9,7 +9,6 @@ struct sys_timer_ops {
9 int (*init)(void); 9 int (*init)(void);
10 int (*start)(void); 10 int (*start)(void);
11 int (*stop)(void); 11 int (*stop)(void);
12 cycle_t (*read)(void);
13#ifndef CONFIG_GENERIC_TIME 12#ifndef CONFIG_GENERIC_TIME
14 unsigned long (*get_offset)(void); 13 unsigned long (*get_offset)(void);
15#endif 14#endif
@@ -39,6 +38,7 @@ struct sys_timer *get_sys_timer(void);
39 38
40/* arch/sh/kernel/time.c */ 39/* arch/sh/kernel/time.c */
41void handle_timer_tick(void); 40void handle_timer_tick(void);
42extern unsigned long sh_hpt_frequency; 41
42extern struct clocksource clocksource_sh;
43 43
44#endif /* __ASM_SH_TIMER_H */ 44#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
index 88ff1ae8a6b8..9c16f737074a 100644
--- a/arch/sh/include/asm/tlb.h
+++ b/arch/sh/include/asm/tlb.h
@@ -6,22 +6,106 @@
6#endif 6#endif
7 7
8#ifndef __ASSEMBLY__ 8#ifndef __ASSEMBLY__
9#include <linux/pagemap.h>
10
11#ifdef CONFIG_MMU
12#include <asm/pgalloc.h>
13#include <asm/tlbflush.h>
14
15/*
16 * TLB handling. This allows us to remove pages from the page
17 * tables, and efficiently handle the TLB issues.
18 */
19struct mmu_gather {
20 struct mm_struct *mm;
21 unsigned int fullmm;
22 unsigned long start, end;
23};
9 24
10#define tlb_start_vma(tlb, vma) \ 25DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
11 flush_cache_range(vma, vma->vm_start, vma->vm_end)
12 26
13#define tlb_end_vma(tlb, vma) \ 27static inline void init_tlb_gather(struct mmu_gather *tlb)
14 flush_tlb_range(vma, vma->vm_start, vma->vm_end) 28{
29 tlb->start = TASK_SIZE;
30 tlb->end = 0;
15 31
16#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0) 32 if (tlb->fullmm) {
33 tlb->start = 0;
34 tlb->end = TASK_SIZE;
35 }
36}
37
38static inline struct mmu_gather *
39tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
40{
41 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
42
43 tlb->mm = mm;
44 tlb->fullmm = full_mm_flush;
45
46 init_tlb_gather(tlb);
47
48 return tlb;
49}
50
51static inline void
52tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
53{
54 if (tlb->fullmm)
55 flush_tlb_mm(tlb->mm);
56
57 /* keep the page table cache within bounds */
58 check_pgt_cache();
59
60 put_cpu_var(mmu_gathers);
61}
62
63static inline void
64tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
65{
66 if (tlb->start > address)
67 tlb->start = address;
68 if (tlb->end < address + PAGE_SIZE)
69 tlb->end = address + PAGE_SIZE;
70}
17 71
18/* 72/*
19 * Flush whole TLBs for MM 73 * In the case of tlb vma handling, we can optimise these away in the
74 * case where we're doing a full MM flush. When we're doing a munmap,
75 * the vmas are adjusted to only cover the region to be torn down.
20 */ 76 */
21#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 77static inline void
78tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
79{
80 if (!tlb->fullmm)
81 flush_cache_range(vma, vma->vm_start, vma->vm_end);
82}
83
84static inline void
85tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
86{
87 if (!tlb->fullmm && tlb->end) {
88 flush_tlb_range(vma, tlb->start, tlb->end);
89 init_tlb_gather(tlb);
90 }
91}
92
93#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
94#define pte_free_tlb(tlb, ptep) pte_free((tlb)->mm, ptep)
95#define pmd_free_tlb(tlb, pmdp) pmd_free((tlb)->mm, pmdp)
96#define pud_free_tlb(tlb, pudp) pud_free((tlb)->mm, pudp)
97
98#define tlb_migrate_finish(mm) do { } while (0)
99
100#else /* CONFIG_MMU */
101
102#define tlb_start_vma(tlb, vma) do { } while (0)
103#define tlb_end_vma(tlb, vma) do { } while (0)
104#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
105#define tlb_flush(tlb) do { } while (0)
22 106
23#include <linux/pagemap.h>
24#include <asm-generic/tlb.h> 107#include <asm-generic/tlb.h>
25 108
109#endif /* CONFIG_MMU */
26#endif /* __ASSEMBLY__ */ 110#endif /* __ASSEMBLY__ */
27#endif /* __ASM_SH_TLB_H */ 111#endif /* __ASM_SH_TLB_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 6813c3220a1d..0ea15f3f2363 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -1,22 +1,17 @@
1#ifndef __ASM_CPU_SH3_DMA_H 1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 4#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721) 5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
7#define SH_DMAC_BASE 0xa4010020 6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
8#else 7 defined(CONFIG_CPU_SUBTYPE_SH7712)
9#define SH_DMAC_BASE 0xa4000020 8#define SH_DMAC_BASE0 0xa4010020
9#else /* SH7705/06/07/09 */
10#define SH_DMAC_BASE0 0xa4000020
10#endif 11#endif
11 12
12#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
13#define DMTE0_IRQ 48 13#define DMTE0_IRQ 48
14#define DMTE1_IRQ 49
15#define DMTE2_IRQ 50
16#define DMTE3_IRQ 51
17#define DMTE4_IRQ 76 14#define DMTE4_IRQ 76
18#define DMTE5_IRQ 77
19#endif
20 15
21/* Definitions for the SuperH DMAC */ 16/* Definitions for the SuperH DMAC */
22#define TM_BURST 0x00000020 17#define TM_BURST 0x00000020
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
new file mode 100644
index 000000000000..0ed5178fed69
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -0,0 +1,94 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7730)
7#define DMTE0_IRQ 48
8#define DMTE4_IRQ 76
9#define DMAE0_IRQ 78 /* DMA Error IRQ*/
10#define SH_DMAC_BASE0 0xFE008020
11#define SH_DMARS_BASE 0xFE009000
12#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7764)
14#define DMTE0_IRQ 34
15#define DMTE4_IRQ 44
16#define DMAE0_IRQ 38
17#define SH_DMAC_BASE0 0xFF608020
18#define SH_DMARS_BASE 0xFF609000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
20#define DMTE0_IRQ 48 /* DMAC0A*/
21#define DMTE4_IRQ 40 /* DMAC0B */
22#define DMTE6_IRQ 42
23#define DMTE8_IRQ 76 /* DMAC1A */
24#define DMTE9_IRQ 77
25#define DMTE10_IRQ 72 /* DMAC1B */
26#define DMTE11_IRQ 73
27#define DMAE0_IRQ 78 /* DMA Error IRQ*/
28#define DMAE1_IRQ 74 /* DMA Error IRQ*/
29#define SH_DMAC_BASE0 0xFE008020
30#define SH_DMAC_BASE1 0xFDC08020
31#define SH_DMARS_BASE 0xFDC09000
32#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
33#define DMTE0_IRQ 34
34#define DMTE4_IRQ 44
35#define DMTE6_IRQ 46
36#define DMTE8_IRQ 92
37#define DMTE9_IRQ 93
38#define DMTE10_IRQ 94
39#define DMTE11_IRQ 95
40#define DMAE0_IRQ 38 /* DMA Error IRQ */
41#define SH_DMAC_BASE0 0xFC808020
42#define SH_DMAC_BASE1 0xFC818020
43#define SH_DMARS_BASE 0xFC809000
44#else /* SH7785 */
45#define DMTE0_IRQ 33
46#define DMTE4_IRQ 37
47#define DMTE6_IRQ 52
48#define DMTE8_IRQ 54
49#define DMTE9_IRQ 55
50#define DMTE10_IRQ 56
51#define DMTE11_IRQ 57
52#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
53#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
54#define SH_DMAC_BASE0 0xFC808020
55#define SH_DMAC_BASE1 0xFCC08020
56#define SH_DMARS_BASE 0xFC809000
57#endif
58
59#define REQ_HE 0x000000C0
60#define REQ_H 0x00000080
61#define REQ_LE 0x00000040
62#define TM_BURST 0x0000020
63#define TS_8 0x00000000
64#define TS_16 0x00000008
65#define TS_32 0x00000010
66#define TS_16BLK 0x00000018
67#define TS_32BLK 0x00100000
68
69/*
70 * The SuperH DMAC supports a number of transmit sizes, we list them here,
71 * with their respective values as they appear in the CHCR registers.
72 *
73 * Defaults to a 64-bit transfer size.
74 */
75enum {
76 XMIT_SZ_8BIT,
77 XMIT_SZ_16BIT,
78 XMIT_SZ_32BIT,
79 XMIT_SZ_128BIT,
80 XMIT_SZ_256BIT,
81};
82
83/*
84 * The DMA count is defined as the number of bytes to transfer.
85 */
86static unsigned int ts_shift[] __maybe_unused = {
87 [XMIT_SZ_8BIT] = 0,
88 [XMIT_SZ_16BIT] = 1,
89 [XMIT_SZ_32BIT] = 2,
90 [XMIT_SZ_128BIT] = 4,
91 [XMIT_SZ_256BIT] = 5,
92};
93
94#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
deleted file mode 100644
index 71b426a6e482..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int ts_shift[] __maybe_unused = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index 235b7cd1fc9a..bcb30246e85c 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -1,31 +1,29 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
6/* SH7751/7760/7780 DMA IRQ sources */ 4/* SH7751/7760/7780 DMA IRQ sources */
7#define DMTE0_IRQ 34
8#define DMTE1_IRQ 35
9#define DMTE2_IRQ 36
10#define DMTE3_IRQ 37
11#define DMTE4_IRQ 44
12#define DMTE5_IRQ 45
13#define DMTE6_IRQ 46
14#define DMTE7_IRQ 47
15#define DMAE_IRQ 38
16 5
17#ifdef CONFIG_CPU_SH4A 6#ifdef CONFIG_CPU_SH4A
18#define SH_DMAC_BASE 0xfc808020
19 7
8#define DMAOR_INIT (DMAOR_DME)
20#define CHCR_TS_MASK 0x18 9#define CHCR_TS_MASK 0x18
21#define CHCR_TS_SHIFT 3 10#define CHCR_TS_SHIFT 3
22 11
23#include <cpu/dma-sh7780.h> 12#include <cpu/dma-sh4a.h>
24#else 13#else /* CONFIG_CPU_SH4A */
25#define SH_DMAC_BASE 0xffa00000 14/*
15 * SH7750/SH7751/SH7760
16 */
17#define DMTE0_IRQ 34
18#define DMTE4_IRQ 44
19#define DMTE6_IRQ 46
20#define DMAE0_IRQ 38
26 21
22#define DMAOR_INIT (0x8000|DMAOR_DME)
23#define SH_DMAC_BASE0 0xffa00000
24#define SH_DMAC_BASE1 0xffa00070
27/* Definitions for the SuperH DMAC */ 25/* Definitions for the SuperH DMAC */
28#define TM_BURST 0x0000080 26#define TM_BURST 0x00000080
29#define TS_8 0x00000010 27#define TS_8 0x00000010
30#define TS_16 0x00000020 28#define TS_16 0x00000020
31#define TS_32 0x00000030 29#define TS_32 0x00000030
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index c23af81c2e70..749d1c434337 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -29,6 +29,10 @@
29#define FRQCR0 0xffc80000 29#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004 30#define FRQCR1 0xffc80004
31#define FRQMR1 0xffc80014 31#define FRQMR1 0xffc80014
32#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
33#define FRQCR0 0xffc40000
34#define FRQCR1 0xffc40004
35#define FRQMR1 0xffc40014
32#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 36#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
33#define FRQCR 0xffc00014 37#define FRQCR 0xffc00014
34#else 38#else
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 9ea8eb27b18e..3ce7ef6c2978 100644
--- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -14,28 +14,35 @@
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */ 15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */ 16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */ 17#define MMU_PTEA 0xFF000034 /* PTE assistance register */
18#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
18 19
19#define MMUCR 0xFF000010 /* MMU Control Register */ 20#define MMUCR 0xFF000010 /* MMU Control Register */
20 21
21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
23#define MMU_PAGE_ASSOC_BIT 0x80 24#define MMU_PAGE_ASSOC_BIT 0x80
24 25
25#define MMUCR_TI (1<<2) 26#define MMUCR_TI (1<<2)
26 27
27#ifdef CONFIG_X2TLB
28#define MMUCR_ME (1 << 7)
29#else
30#define MMUCR_ME (0)
31#endif
32
33#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 28#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
34#define MMUCR_SE (1 << 4) 29#define MMUCR_SE (1 << 4)
35#else 30#else
36#define MMUCR_SE (0) 31#define MMUCR_SE (0)
37#endif 32#endif
38 33
34#ifdef CONFIG_CPU_HAS_PTEAEX
35#define MMUCR_AEX (1 << 6)
36#else
37#define MMUCR_AEX (0)
38#endif
39
40#ifdef CONFIG_X2TLB
41#define MMUCR_ME (1 << 7)
42#else
43#define MMUCR_ME (0)
44#endif
45
39#ifdef CONFIG_SH_STORE_QUEUES 46#ifdef CONFIG_SH_STORE_QUEUES
40#define MMUCR_SQMD (1 << 9) 47#define MMUCR_SQMD (1 << 9)
41#else 48#else
@@ -43,17 +50,7 @@
43#endif 50#endif
44 51
45#define MMU_NTLB_ENTRIES 64 52#define MMU_NTLB_ENTRIES 64
46#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE) 53#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX)
47
48#define MMU_ITLB_DATA_ARRAY 0xF3000000
49#define MMU_UTLB_DATA_ARRAY 0xF7000000
50
51#define MMU_UTLB_ENTRIES 64
52#define MMU_U_ENTRY_SHIFT 8
53#define MMU_UTLB_VALID 0x100
54#define MMU_ITLB_ENTRIES 4
55#define MMU_I_ENTRY_SHIFT 8
56#define MMU_ITLB_VALID 0x100
57 54
58#define TRA 0xff000020 55#define TRA 0xff000020
59#define EXPEVT 0xff000024 56#define EXPEVT 0xff000024
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7786.h b/arch/sh/include/cpu-sh4/cpu/sh7786.h
new file mode 100644
index 000000000000..48688adc0c84
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7786.h
@@ -0,0 +1,192 @@
1/*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on sh7785.h
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#ifndef __CPU_SH7786_H__
15#define __CPU_SH7786_H__
16
17enum {
18 /* PA */
19 GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
20 GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
21
22 /* PB */
23 GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
24 GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
25
26 /* PC */
27 GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
28 GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
29
30 /* PD */
31 GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
32 GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
33
34 /* PE */
35 GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
36 GPIO_PE1, GPIO_PE0,
37
38 /* PF */
39 GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
40 GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
41
42 /* PG */
43 GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
44 GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
45
46 /* PH */
47 GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
48 GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
49
50 /* PJ */
51 GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
52 GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
53
54 GPIO_FN_CDE,
55 GPIO_FN_ETH_MAGIC,
56 GPIO_FN_DISP,
57 GPIO_FN_ETH_LINK,
58 GPIO_FN_DR5,
59 GPIO_FN_ETH_TX_ER,
60 GPIO_FN_DR4,
61 GPIO_FN_ETH_TX_EN,
62 GPIO_FN_DR3,
63 GPIO_FN_ETH_TXD3,
64 GPIO_FN_DR2,
65 GPIO_FN_ETH_TXD2,
66 GPIO_FN_DR1,
67 GPIO_FN_ETH_TXD1,
68 GPIO_FN_DR0,
69 GPIO_FN_ETH_TXD0,
70 GPIO_FN_VSYNC,
71 GPIO_FN_HSPI_CLK,
72 GPIO_FN_ODDF,
73 GPIO_FN_HSPI_CS,
74 GPIO_FN_DG5,
75 GPIO_FN_ETH_MDIO,
76 GPIO_FN_DG4,
77 GPIO_FN_ETH_RX_CLK,
78 GPIO_FN_DG3,
79 GPIO_FN_ETH_MDC,
80 GPIO_FN_DG2,
81 GPIO_FN_ETH_COL,
82 GPIO_FN_DG1,
83 GPIO_FN_ETH_TX_CLK,
84 GPIO_FN_DG0,
85 GPIO_FN_ETH_CRS,
86 GPIO_FN_DCLKIN,
87 GPIO_FN_HSPI_RX,
88 GPIO_FN_HSYNC,
89 GPIO_FN_HSPI_TX,
90 GPIO_FN_DB5,
91 GPIO_FN_ETH_RXD3,
92 GPIO_FN_DB4,
93 GPIO_FN_ETH_RXD2,
94 GPIO_FN_DB3,
95 GPIO_FN_ETH_RXD1,
96 GPIO_FN_DB2,
97 GPIO_FN_ETH_RXD0,
98 GPIO_FN_DB1,
99 GPIO_FN_ETH_RX_DV,
100 GPIO_FN_DB0,
101 GPIO_FN_ETH_RX_ER,
102 GPIO_FN_DCLKOUT,
103 GPIO_FN_SCIF1_SLK,
104 GPIO_FN_SCIF1_RXD,
105 GPIO_FN_SCIF1_TXD,
106 GPIO_FN_DACK1,
107 GPIO_FN_BACK,
108 GPIO_FN_FALE,
109 GPIO_FN_DACK0,
110 GPIO_FN_FCLE,
111 GPIO_FN_DREQ1,
112 GPIO_FN_BREQ,
113 GPIO_FN_USB_OVC1,
114 GPIO_FN_DREQ0,
115 GPIO_FN_USB_OVC0,
116 GPIO_FN_USB_PENC1,
117 GPIO_FN_USB_PENC0,
118 GPIO_FN_HAC1_SDOUT,
119 GPIO_FN_SSI1_SDATA,
120 GPIO_FN_SDIF1CMD,
121 GPIO_FN_HAC1_SDIN,
122 GPIO_FN_SSI1_SCK,
123 GPIO_FN_SDIF1CD,
124 GPIO_FN_HAC1_SYNC,
125 GPIO_FN_SSI1_WS,
126 GPIO_FN_SDIF1WP,
127 GPIO_FN_HAC1_BITCLK,
128 GPIO_FN_SSI1_CLK,
129 GPIO_FN_SDIF1CLK,
130 GPIO_FN_HAC0_SDOUT,
131 GPIO_FN_SSI0_SDATA,
132 GPIO_FN_SDIF1D3,
133 GPIO_FN_HAC0_SDIN,
134 GPIO_FN_SSI0_SCK,
135 GPIO_FN_SDIF1D2,
136 GPIO_FN_HAC0_SYNC,
137 GPIO_FN_SSI0_WS,
138 GPIO_FN_SDIF1D1,
139 GPIO_FN_HAC0_BITCLK,
140 GPIO_FN_SSI0_CLK,
141 GPIO_FN_SDIF1D0,
142 GPIO_FN_SCIF3_SCK,
143 GPIO_FN_SSI2_SDATA,
144 GPIO_FN_SCIF3_RXD,
145 GPIO_FN_TCLK,
146 GPIO_FN_SSI2_SCK,
147 GPIO_FN_SCIF3_TXD,
148 GPIO_FN_HAC_RES,
149 GPIO_FN_SSI2_WS,
150 GPIO_FN_DACK3,
151 GPIO_FN_SDIF0CMD,
152 GPIO_FN_DACK2,
153 GPIO_FN_SDIF0CD,
154 GPIO_FN_DREQ3,
155 GPIO_FN_SDIF0WP,
156 GPIO_FN_SCIF0_CTS,
157 GPIO_FN_DREQ2,
158 GPIO_FN_SDIF0CLK,
159 GPIO_FN_SCIF0_RTS,
160 GPIO_FN_IRL7,
161 GPIO_FN_SDIF0D3,
162 GPIO_FN_SCIF0_SCK,
163 GPIO_FN_IRL6,
164 GPIO_FN_SDIF0D2,
165 GPIO_FN_SCIF0_RXD,
166 GPIO_FN_IRL5,
167 GPIO_FN_SDIF0D1,
168 GPIO_FN_SCIF0_TXD,
169 GPIO_FN_IRL4,
170 GPIO_FN_SDIF0D0,
171 GPIO_FN_SCIF5_SCK,
172 GPIO_FN_FRB,
173 GPIO_FN_SCIF5_RXD,
174 GPIO_FN_IOIS16,
175 GPIO_FN_SCIF5_TXD,
176 GPIO_FN_CE2B,
177 GPIO_FN_DRAK3,
178 GPIO_FN_CE2A,
179 GPIO_FN_SCIF4_SCK,
180 GPIO_FN_DRAK2,
181 GPIO_FN_SSI3_WS,
182 GPIO_FN_SCIF4_RXD,
183 GPIO_FN_DRAK1,
184 GPIO_FN_SSI3_SDATA,
185 GPIO_FN_FSTATUS,
186 GPIO_FN_SCIF4_TXD,
187 GPIO_FN_DRAK0,
188 GPIO_FN_SSI3_SCK,
189 GPIO_FN_FSE,
190};
191
192#endif /* __CPU_SH7786_H__ */
diff --git a/arch/sh/include/mach-common/mach/urquell.h b/arch/sh/include/mach-common/mach/urquell.h
new file mode 100644
index 000000000000..14b3e1d01777
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/urquell.h
@@ -0,0 +1,68 @@
1#ifndef __MACH_URQUELL_H
2#define __MACH_URQUELL_H
3
4/*
5 * ------ 0x00000000 ------------------------------------
6 * CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH
7 * -----+ 0x04000000 ------------------------------------
8 * CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH
9 * -----+ 0x08000000 ------------------------------------
10 * CS2 | DDR3
11 * CS3 |
12 * -----+ 0x10000000 ------------------------------------
13 * CS4 | PCIe
14 * -----+ 0x14000000 ------------------------------------
15 * CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA
16 * -----+ 0x18000000 ------------------------------------
17 * CS6 | ATA, NAND FLASH
18 * -----+ 0x1c000000 ------------------------------------
19 * CS7 | SH7786 register
20 * -----+------------------------------------------------
21 */
22
23#define NOR_FLASH_ADDR 0x00000000
24#define NOR_FLASH_SIZE 0x04000000
25
26#define CS1_BASE 0x05000000
27#define CS5_BASE 0x15000000
28#define FPGA_BASE CS1_BASE
29
30#define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS)
31#define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS)
32
33#define SRSTR_OFS 0x0000 /* System reset register */
34#define BDMR_OFS 0x0010 /* Board operating mode resister */
35#define IRL0SR_OFS 0x0020 /* IRL0 Status register */
36#define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */
37#define IRL1SR_OFS 0x0040 /* IRL1 Status register */
38#define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */
39#define IRL2SR_OFS 0x0060 /* IRL2 Status register */
40#define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */
41#define IRL3SR_OFS 0x0080 /* IRL3 Status register */
42#define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */
43#define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */
44#define SLEDR_OFS 0x0130 /* LED control resister */
45#define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */
46#define FPVERR_OFS 0x0150 /* FPGA Version register */
47#define FPDATER_OFS 0x0160 /* FPGA Date register */
48#define FPYEARR_OFS 0x0170 /* FPGA Year register */
49#define TCLKCR_OFS 0x0180 /* TCLK Control register */
50#define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */
51#define FPODR_OFS 0x1010 /* Output port data register */
52#define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */
53#define FPINDR_OFS 0x1030 /* Input port data register */
54#define MDSWMR_OFS 0x1040 /* MODE SW monitor register */
55#define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
56#define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */
57#define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */
58#define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */
59#define LATCHCR_OFS 0x3000 /* Latch control register */
60#define LATCUAR_OFS 0x3010 /* Latch upper address register */
61#define LATCLAR_OFS 0x3012 /* Latch lower address register */
62#define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
63#define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
64
65#define CHARLED_OFS 0x2000 /* Character LED */
66
67#endif /* __MACH_URQUELL_H */
68
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 04:59:58 -0500