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-rw-r--r--arch/sh/include/asm/addrspace.h8
-rw-r--r--arch/sh/include/asm/pgtable.h12
-rw-r--r--arch/sh/include/asm/system.h4
-rw-r--r--arch/sh/include/asm/system_32.h36
-rw-r--r--arch/sh/include/asm/system_64.h3
-rw-r--r--arch/sh/include/asm/uncached.h40
-rw-r--r--arch/sh/include/mach-common/mach/edosk7705.h7
-rw-r--r--arch/sh/include/mach-common/mach/microdev.h9
-rw-r--r--arch/sh/include/mach-common/mach/secureedge5410.h (renamed from arch/sh/include/mach-common/mach/snapgear.h)22
-rw-r--r--arch/sh/include/mach-common/mach/systemh7751.h71
10 files changed, 45 insertions, 167 deletions
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
index 446b3831c214..3d1ae2bfaa6f 100644
--- a/arch/sh/include/asm/addrspace.h
+++ b/arch/sh/include/asm/addrspace.h
@@ -44,10 +44,10 @@
44/* 44/*
45 * These will never work in 32-bit, don't even bother. 45 * These will never work in 32-bit, don't even bother.
46 */ 46 */
47#define P1SEGADDR(a) __futile_remapping_attempt 47#define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; })
48#define P2SEGADDR(a) __futile_remapping_attempt 48#define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; })
49#define P3SEGADDR(a) __futile_remapping_attempt 49#define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; })
50#define P4SEGADDR(a) __futile_remapping_attempt 50#define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; })
51#endif 51#endif
52#endif /* P1SEG */ 52#endif /* P1SEG */
53 53
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index a15f1058bbf4..083ea068e819 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -66,7 +66,6 @@ static inline unsigned long long neff_sign_extend(unsigned long val)
66#define PHYS_ADDR_MASK29 0x1fffffff 66#define PHYS_ADDR_MASK29 0x1fffffff
67#define PHYS_ADDR_MASK32 0xffffffff 67#define PHYS_ADDR_MASK32 0xffffffff
68 68
69#ifdef CONFIG_PMB
70static inline unsigned long phys_addr_mask(void) 69static inline unsigned long phys_addr_mask(void)
71{ 70{
72 /* Is the MMU in 29bit mode? */ 71 /* Is the MMU in 29bit mode? */
@@ -75,17 +74,6 @@ static inline unsigned long phys_addr_mask(void)
75 74
76 return PHYS_ADDR_MASK32; 75 return PHYS_ADDR_MASK32;
77} 76}
78#elif defined(CONFIG_32BIT)
79static inline unsigned long phys_addr_mask(void)
80{
81 return PHYS_ADDR_MASK32;
82}
83#else
84static inline unsigned long phys_addr_mask(void)
85{
86 return PHYS_ADDR_MASK29;
87}
88#endif
89 77
90#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK) 78#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
91#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT) 79#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index 1f1af5afff03..10c8b1823a18 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -10,6 +10,7 @@
10#include <linux/compiler.h> 10#include <linux/compiler.h>
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <asm/types.h> 12#include <asm/types.h>
13#include <asm/uncached.h>
13 14
14#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ 15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
15 16
@@ -137,9 +138,6 @@ extern unsigned int instruction_size(unsigned int insn);
137#define instruction_size(insn) (4) 138#define instruction_size(insn) (4)
138#endif 139#endif
139 140
140extern unsigned long cached_to_uncached;
141extern unsigned long uncached_size;
142
143void per_cpu_trap_init(void); 141void per_cpu_trap_init(void);
144void default_idle(void); 142void default_idle(void);
145void cpu_idle_wait(void); 143void cpu_idle_wait(void);
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index c941b2739405..a4ad1cd9bc4d 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -145,42 +145,6 @@ do { \
145 __restore_dsp(prev); \ 145 __restore_dsp(prev); \
146} while (0) 146} while (0)
147 147
148/*
149 * Jump to uncached area.
150 * When handling TLB or caches, we need to do it from an uncached area.
151 */
152#define jump_to_uncached() \
153do { \
154 unsigned long __dummy; \
155 \
156 __asm__ __volatile__( \
157 "mova 1f, %0\n\t" \
158 "add %1, %0\n\t" \
159 "jmp @%0\n\t" \
160 " nop\n\t" \
161 ".balign 4\n" \
162 "1:" \
163 : "=&z" (__dummy) \
164 : "r" (cached_to_uncached)); \
165} while (0)
166
167/*
168 * Back to cached area.
169 */
170#define back_to_cached() \
171do { \
172 unsigned long __dummy; \
173 ctrl_barrier(); \
174 __asm__ __volatile__( \
175 "mov.l 1f, %0\n\t" \
176 "jmp @%0\n\t" \
177 " nop\n\t" \
178 ".balign 4\n" \
179 "1: .long 2f\n" \
180 "2:" \
181 : "=&r" (__dummy)); \
182} while (0)
183
184#ifdef CONFIG_CPU_HAS_SR_RB 148#ifdef CONFIG_CPU_HAS_SR_RB
185#define lookup_exception_vector() \ 149#define lookup_exception_vector() \
186({ \ 150({ \
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
index 36338646dfc8..8593bc8d1a4e 100644
--- a/arch/sh/include/asm/system_64.h
+++ b/arch/sh/include/asm/system_64.h
@@ -34,9 +34,6 @@ do { \
34 &next->thread); \ 34 &next->thread); \
35} while (0) 35} while (0)
36 36
37#define jump_to_uncached() do { } while (0)
38#define back_to_cached() do { } while (0)
39
40#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr)) 37#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
41#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr)) 38#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
42#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr)) 39#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
diff --git a/arch/sh/include/asm/uncached.h b/arch/sh/include/asm/uncached.h
index e3419f96626a..6f8816b79cf1 100644
--- a/arch/sh/include/asm/uncached.h
+++ b/arch/sh/include/asm/uncached.h
@@ -4,15 +4,55 @@
4#include <linux/bug.h> 4#include <linux/bug.h>
5 5
6#ifdef CONFIG_UNCACHED_MAPPING 6#ifdef CONFIG_UNCACHED_MAPPING
7extern unsigned long cached_to_uncached;
8extern unsigned long uncached_size;
7extern unsigned long uncached_start, uncached_end; 9extern unsigned long uncached_start, uncached_end;
8 10
9extern int virt_addr_uncached(unsigned long kaddr); 11extern int virt_addr_uncached(unsigned long kaddr);
10extern void uncached_init(void); 12extern void uncached_init(void);
11extern void uncached_resize(unsigned long size); 13extern void uncached_resize(unsigned long size);
14
15/*
16 * Jump to uncached area.
17 * When handling TLB or caches, we need to do it from an uncached area.
18 */
19#define jump_to_uncached() \
20do { \
21 unsigned long __dummy; \
22 \
23 __asm__ __volatile__( \
24 "mova 1f, %0\n\t" \
25 "add %1, %0\n\t" \
26 "jmp @%0\n\t" \
27 " nop\n\t" \
28 ".balign 4\n" \
29 "1:" \
30 : "=&z" (__dummy) \
31 : "r" (cached_to_uncached)); \
32} while (0)
33
34/*
35 * Back to cached area.
36 */
37#define back_to_cached() \
38do { \
39 unsigned long __dummy; \
40 ctrl_barrier(); \
41 __asm__ __volatile__( \
42 "mov.l 1f, %0\n\t" \
43 "jmp @%0\n\t" \
44 " nop\n\t" \
45 ".balign 4\n" \
46 "1: .long 2f\n" \
47 "2:" \
48 : "=&r" (__dummy)); \
49} while (0)
12#else 50#else
13#define virt_addr_uncached(kaddr) (0) 51#define virt_addr_uncached(kaddr) (0)
14#define uncached_init() do { } while (0) 52#define uncached_init() do { } while (0)
15#define uncached_resize(size) BUG() 53#define uncached_resize(size) BUG()
54#define jump_to_uncached() do { } while (0)
55#define back_to_cached() do { } while (0)
16#endif 56#endif
17 57
18#endif /* __ASM_SH_UNCACHED_H */ 58#endif /* __ASM_SH_UNCACHED_H */
diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h
deleted file mode 100644
index efc43b323466..000000000000
--- a/arch/sh/include/mach-common/mach/edosk7705.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_SH_EDOSK7705_H
2#define __ASM_SH_EDOSK7705_H
3
4#define __IO_PREFIX sh_edosk7705
5#include <asm/io_generic.h>
6
7#endif /* __ASM_SH_EDOSK7705_H */
diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h
index 1aed15856e11..dcb05fa8c164 100644
--- a/arch/sh/include/mach-common/mach/microdev.h
+++ b/arch/sh/include/mach-common/mach/microdev.h
@@ -68,13 +68,4 @@ extern void microdev_print_fpga_intc_status(void);
68#define __IO_PREFIX microdev 68#define __IO_PREFIX microdev
69#include <asm/io_generic.h> 69#include <asm/io_generic.h>
70 70
71#if defined(CONFIG_PCI)
72unsigned char microdev_pci_inb(unsigned long port);
73unsigned short microdev_pci_inw(unsigned long port);
74unsigned long microdev_pci_inl(unsigned long port);
75void microdev_pci_outb(unsigned char data, unsigned long port);
76void microdev_pci_outw(unsigned short data, unsigned long port);
77void microdev_pci_outl(unsigned long data, unsigned long port);
78#endif
79
80#endif /* __ASM_SH_MICRODEV_H */ 71#endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/secureedge5410.h
index 042d95f51c4d..3653b9a4bacc 100644
--- a/arch/sh/include/mach-common/mach/snapgear.h
+++ b/arch/sh/include/mach-common/mach/secureedge5410.h
@@ -12,30 +12,9 @@
12#ifndef _ASM_SH_IO_SNAPGEAR_H 12#ifndef _ASM_SH_IO_SNAPGEAR_H
13#define _ASM_SH_IO_SNAPGEAR_H 13#define _ASM_SH_IO_SNAPGEAR_H
14 14
15#if defined(CONFIG_CPU_SH4)
16/*
17 * The external interrupt lines, these take up ints 0 - 15 inclusive
18 * depending on the priority for the interrupt. In fact the priority
19 * is the interrupt :-)
20 */
21
22#define IRL0_IRQ 2
23#define IRL0_PRIORITY 13
24
25#define IRL1_IRQ 5
26#define IRL1_PRIORITY 10
27
28#define IRL2_IRQ 8
29#define IRL2_PRIORITY 7
30
31#define IRL3_IRQ 11
32#define IRL3_PRIORITY 4
33#endif
34
35#define __IO_PREFIX snapgear 15#define __IO_PREFIX snapgear
36#include <asm/io_generic.h> 16#include <asm/io_generic.h>
37 17
38#ifdef CONFIG_SH_SECUREEDGE5410
39/* 18/*
40 * We need to remember what was written to the ioport as some bits 19 * We need to remember what was written to the ioport as some bits
41 * are shared with other functions and you cannot read back what was 20 * are shared with other functions and you cannot read back what was
@@ -66,6 +45,5 @@ extern unsigned short secureedge5410_ioport;
66 ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) 45 ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
67#define SECUREEDGE_READ_IOPORT() \ 46#define SECUREEDGE_READ_IOPORT() \
68 ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) 47 ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
69#endif
70 48
71#endif /* _ASM_SH_IO_SNAPGEAR_H */ 49#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/mach-common/mach/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h
deleted file mode 100644
index 4161122c84ef..000000000000
--- a/arch/sh/include/mach-common/mach/systemh7751.h
+++ /dev/null
@@ -1,71 +0,0 @@
1#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
2#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
3
4/*
5 * linux/include/asm-sh/systemh/7751systemh.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SystemH support
10
11 * Modified for 7751 SystemH by
12 * Jonathan Short, 2002.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68#define __IO_PREFIX sh7751systemh
69#include <asm/io_generic.h>
70
71#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-06 16:46:24 -0500