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Diffstat (limited to 'arch/sh/include/mach-common/mach/sh2007.h')
-rw-r--r--arch/sh/include/mach-common/mach/sh2007.h117
1 files changed, 117 insertions, 0 deletions
diff --git a/arch/sh/include/mach-common/mach/sh2007.h b/arch/sh/include/mach-common/mach/sh2007.h
new file mode 100644
index 000000000000..48180b9aa03d
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh2007.h
@@ -0,0 +1,117 @@
1#ifndef __MACH_SH2007_H
2#define __MACH_SH2007_H
3
4#define CS5BCR 0xff802050
5#define CS5WCR 0xff802058
6#define CS5PCR 0xff802070
7
8#define BUS_SZ8 1
9#define BUS_SZ16 2
10#define BUS_SZ32 3
11
12#define PCMCIA_IODYN 1
13#define PCMCIA_ATA 0
14#define PCMCIA_IO8 2
15#define PCMCIA_IO16 3
16#define PCMCIA_COMM8 4
17#define PCMCIA_COMM16 5
18#define PCMCIA_ATTR8 6
19#define PCMCIA_ATTR16 7
20
21#define TYPE_SRAM 0
22#define TYPE_PCMCIA 4
23
24/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
25#define IWW5 0
26#define IWW6 3
27/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
28#define IWRWD5 2
29#define IWRWD6 2
30/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31#define IWRWS5 2
32#define IWRWS6 2
33/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
34#define IWRRD5 2
35#define IWRRD6 2
36/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37#define IWRRS5 0
38#define IWRRS6 2
39/* burst count (0-3:4,8,16,32) */
40#define BST5 0
41#define BST6 0
42/* bus size */
43#define SZ5 BUS_SZ16
44#define SZ6 BUS_SZ16
45/* RD hold for SRAM (0-1:0,1) */
46#define RDSPL5 0
47#define RDSPL6 0
48/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
49#define BW5 0
50#define BW6 0
51/* Multiplex (0-1:0,1) */
52#define MPX5 0
53#define MPX6 0
54/* device type */
55#define TYPE5 TYPE_PCMCIA
56#define TYPE6 TYPE_PCMCIA
57/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
58#define ADS5 0
59#define ADS6 0
60/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
61#define ADH5 0
62#define ADH6 0
63/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
64#define RDS5 0
65#define RDS6 0
66/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
67#define RDH5 0
68#define RDH6 0
69/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
70#define WTS5 0
71#define WTS6 0
72/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
73#define WTH5 0
74#define WTH6 0
75/* BS hold (0-1:1,2) */
76#define BSH5 0
77#define BSH6 0
78/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
79#define IW5 6 /* 60ns PIO mode 4 */
80#define IW6 15 /* 250ns */
81
82#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */
83#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */
84#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */
85#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */
86/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
87#define PCIW5 12
88/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
89#define TEDA5 2
90/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
91#define TEDB5 4
92/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
93#define TEHA5 2
94/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
95#define TEHB5 3
96
97#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \
98 (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \
99 (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
100#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \
101 (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5)
102#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \
103 (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \
104 (TEDB5<<8)|(TEHA5<<4)|TEHB5)
105
106#define SMC0_BASE 0xb0800000 /* eth0 */
107#define SMC1_BASE 0xb0900000 /* eth1 */
108#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */
109#define IDE_BASE 0xb4000000 /* IDE */
110#define PC104_IO_BASE 0xb8000000
111#define PC104_MEM_BASE 0xba000000
112#define SMC_IO_SIZE 0x100
113
114#define CF_OFFSET 0x1f0
115#define IDE_OFFSET 0x170
116
117#endif /* __MACH_SH2007_H */