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Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/dma-sh4a.h')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h94
1 files changed, 94 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
new file mode 100644
index 000000000000..0ed5178fed69
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -0,0 +1,94 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7730)
7#define DMTE0_IRQ 48
8#define DMTE4_IRQ 76
9#define DMAE0_IRQ 78 /* DMA Error IRQ*/
10#define SH_DMAC_BASE0 0xFE008020
11#define SH_DMARS_BASE 0xFE009000
12#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7764)
14#define DMTE0_IRQ 34
15#define DMTE4_IRQ 44
16#define DMAE0_IRQ 38
17#define SH_DMAC_BASE0 0xFF608020
18#define SH_DMARS_BASE 0xFF609000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
20#define DMTE0_IRQ 48 /* DMAC0A*/
21#define DMTE4_IRQ 40 /* DMAC0B */
22#define DMTE6_IRQ 42
23#define DMTE8_IRQ 76 /* DMAC1A */
24#define DMTE9_IRQ 77
25#define DMTE10_IRQ 72 /* DMAC1B */
26#define DMTE11_IRQ 73
27#define DMAE0_IRQ 78 /* DMA Error IRQ*/
28#define DMAE1_IRQ 74 /* DMA Error IRQ*/
29#define SH_DMAC_BASE0 0xFE008020
30#define SH_DMAC_BASE1 0xFDC08020
31#define SH_DMARS_BASE 0xFDC09000
32#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
33#define DMTE0_IRQ 34
34#define DMTE4_IRQ 44
35#define DMTE6_IRQ 46
36#define DMTE8_IRQ 92
37#define DMTE9_IRQ 93
38#define DMTE10_IRQ 94
39#define DMTE11_IRQ 95
40#define DMAE0_IRQ 38 /* DMA Error IRQ */
41#define SH_DMAC_BASE0 0xFC808020
42#define SH_DMAC_BASE1 0xFC818020
43#define SH_DMARS_BASE 0xFC809000
44#else /* SH7785 */
45#define DMTE0_IRQ 33
46#define DMTE4_IRQ 37
47#define DMTE6_IRQ 52
48#define DMTE8_IRQ 54
49#define DMTE9_IRQ 55
50#define DMTE10_IRQ 56
51#define DMTE11_IRQ 57
52#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
53#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
54#define SH_DMAC_BASE0 0xFC808020
55#define SH_DMAC_BASE1 0xFCC08020
56#define SH_DMARS_BASE 0xFC809000
57#endif
58
59#define REQ_HE 0x000000C0
60#define REQ_H 0x00000080
61#define REQ_LE 0x00000040
62#define TM_BURST 0x0000020
63#define TS_8 0x00000000
64#define TS_16 0x00000008
65#define TS_32 0x00000010
66#define TS_16BLK 0x00000018
67#define TS_32BLK 0x00100000
68
69/*
70 * The SuperH DMAC supports a number of transmit sizes, we list them here,
71 * with their respective values as they appear in the CHCR registers.
72 *
73 * Defaults to a 64-bit transfer size.
74 */
75enum {
76 XMIT_SZ_8BIT,
77 XMIT_SZ_16BIT,
78 XMIT_SZ_32BIT,
79 XMIT_SZ_128BIT,
80 XMIT_SZ_256BIT,
81};
82
83/*
84 * The DMA count is defined as the number of bytes to transfer.
85 */
86static unsigned int ts_shift[] __maybe_unused = {
87 [XMIT_SZ_8BIT] = 0,
88 [XMIT_SZ_16BIT] = 1,
89 [XMIT_SZ_32BIT] = 2,
90 [XMIT_SZ_128BIT] = 4,
91 [XMIT_SZ_256BIT] = 5,
92};
93
94#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */