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-rw-r--r--arch/sh/include/asm/atomic-llsc.h27
-rw-r--r--arch/sh/include/asm/atomic.h4
-rw-r--r--arch/sh/include/asm/cacheflush.h2
-rw-r--r--arch/sh/include/asm/clock.h113
-rw-r--r--arch/sh/include/asm/cmpxchg-llsc.h2
-rw-r--r--arch/sh/include/asm/device.h2
-rw-r--r--arch/sh/include/asm/hd64461.h148
-rw-r--r--arch/sh/include/asm/io.h22
-rw-r--r--arch/sh/include/asm/irq.h3
-rw-r--r--arch/sh/include/asm/kprobes.h2
-rw-r--r--arch/sh/include/asm/machvec.h3
-rw-r--r--arch/sh/include/asm/pci.h118
-rw-r--r--arch/sh/include/asm/pgtable.h4
-rw-r--r--arch/sh/include/asm/processor.h23
-rw-r--r--arch/sh/include/asm/ptrace.h5
-rw-r--r--arch/sh/include/asm/rtc.h11
-rw-r--r--arch/sh/include/asm/spinlock.h2
-rw-r--r--arch/sh/include/asm/swab.h12
-rw-r--r--arch/sh/include/asm/system_32.h2
-rw-r--r--arch/sh/include/asm/timer.h44
-rw-r--r--arch/sh/include/asm/types.h4
-rw-r--r--arch/sh/include/asm/ubc.h11
-rw-r--r--arch/sh/include/asm/unaligned-sh4a.h10
-rw-r--r--arch/sh/include/asm/unistd_32.h3
-rw-r--r--arch/sh/include/asm/unistd_64.h3
25 files changed, 352 insertions, 228 deletions
diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h
index 4b00b78e3f4f..b040e1e08610 100644
--- a/arch/sh/include/asm/atomic-llsc.h
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -104,4 +104,31 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
104 : "t"); 104 : "t");
105} 105}
106 106
107#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
108
109/**
110 * atomic_add_unless - add unless the number is a given value
111 * @v: pointer of type atomic_t
112 * @a: the amount to add to v...
113 * @u: ...unless v is equal to u.
114 *
115 * Atomically adds @a to @v, so long as it was not @u.
116 * Returns non-zero if @v was not @u, and zero otherwise.
117 */
118static inline int atomic_add_unless(atomic_t *v, int a, int u)
119{
120 int c, old;
121 c = atomic_read(v);
122 for (;;) {
123 if (unlikely(c == (u)))
124 break;
125 old = atomic_cmpxchg((v), c, c + (a));
126 if (likely(old == c))
127 break;
128 c = old;
129 }
130
131 return c != (u);
132}
133
107#endif /* __ASM_SH_ATOMIC_LLSC_H */ 134#endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index a5647d0cd179..157c320272cb 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -45,7 +45,7 @@
45#define atomic_inc(v) atomic_add(1,(v)) 45#define atomic_inc(v) atomic_add(1,(v))
46#define atomic_dec(v) atomic_sub(1,(v)) 46#define atomic_dec(v) atomic_sub(1,(v))
47 47
48#ifndef CONFIG_GUSA_RB 48#if !defined(CONFIG_GUSA_RB) && !defined(CONFIG_CPU_SH4A)
49static inline int atomic_cmpxchg(atomic_t *v, int old, int new) 49static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
50{ 50{
51 int ret; 51 int ret;
@@ -73,7 +73,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
73 73
74 return ret != u; 74 return ret != u;
75} 75}
76#endif 76#endif /* !CONFIG_GUSA_RB && !CONFIG_CPU_SH4A */
77 77
78#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 78#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
79#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 79#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 09acbc32d6c7..4c5462daa74c 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -75,7 +75,5 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
75#define flush_cache_vmap(start, end) flush_cache_all() 75#define flush_cache_vmap(start, end) flush_cache_all()
76#define flush_cache_vunmap(start, end) flush_cache_all() 76#define flush_cache_vunmap(start, end) flush_cache_all()
77 77
78#define HAVE_ARCH_UNMAPPED_AREA
79
80#endif /* __KERNEL__ */ 78#endif /* __KERNEL__ */
81#endif /* __ASM_SH_CACHEFLUSH_H */ 79#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 2f6c9627bc1f..9fe7d7f8af40 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,9 +1,9 @@
1#ifndef __ASM_SH_CLOCK_H 1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H 2#define __ASM_SH_CLOCK_H
3 3
4#include <linux/kref.h>
5#include <linux/list.h> 4#include <linux/list.h>
6#include <linux/seq_file.h> 5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/clk.h> 7#include <linux/clk.h>
8#include <linux/err.h> 8#include <linux/err.h>
9 9
@@ -11,9 +11,9 @@ struct clk;
11 11
12struct clk_ops { 12struct clk_ops {
13 void (*init)(struct clk *clk); 13 void (*init)(struct clk *clk);
14 void (*enable)(struct clk *clk); 14 int (*enable)(struct clk *clk);
15 void (*disable)(struct clk *clk); 15 void (*disable)(struct clk *clk);
16 void (*recalc)(struct clk *clk); 16 unsigned long (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent); 18 int (*set_parent)(struct clk *clk, struct clk *parent);
19 long (*round_rate)(struct clk *clk, unsigned long rate); 19 long (*round_rate)(struct clk *clk, unsigned long rate);
@@ -28,43 +28,47 @@ struct clk {
28 struct clk *parent; 28 struct clk *parent;
29 struct clk_ops *ops; 29 struct clk_ops *ops;
30 30
31 struct kref kref; 31 struct list_head children;
32 struct list_head sibling; /* node for children */
33
34 int usecount;
32 35
33 unsigned long rate; 36 unsigned long rate;
34 unsigned long flags; 37 unsigned long flags;
38
39 void __iomem *enable_reg;
40 unsigned int enable_bit;
41
35 unsigned long arch_flags; 42 unsigned long arch_flags;
43 void *priv;
44 struct dentry *dentry;
45 struct cpufreq_frequency_table *freq_table;
46};
47
48struct clk_lookup {
49 struct list_head node;
50 const char *dev_id;
51 const char *con_id;
52 struct clk *clk;
36}; 53};
37 54
38#define CLK_ALWAYS_ENABLED (1 << 0) 55#define CLK_ENABLE_ON_INIT (1 << 0)
39#define CLK_RATE_PROPAGATES (1 << 1)
40 56
41/* Should be defined by processor-specific code */ 57/* Should be defined by processor-specific code */
42void arch_init_clk_ops(struct clk_ops **, int type); 58void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
43int __init arch_clk_init(void); 59int __init arch_clk_init(void);
44 60
45/* arch/sh/kernel/cpu/clock.c */ 61/* arch/sh/kernel/cpu/clock.c */
46int clk_init(void); 62int clk_init(void);
47 63unsigned long followparent_recalc(struct clk *);
48void clk_recalc_rate(struct clk *); 64void recalculate_root_clocks(void);
49 65void propagate_rate(struct clk *);
66int clk_reparent(struct clk *child, struct clk *parent);
50int clk_register(struct clk *); 67int clk_register(struct clk *);
51void clk_unregister(struct clk *); 68void clk_unregister(struct clk *);
52 69
53static inline int clk_always_enable(const char *id) 70/* arch/sh/kernel/cpu/clock-cpg.c */
54{ 71int __init __deprecated cpg_clk_init(void);
55 struct clk *clk;
56 int ret;
57
58 clk = clk_get(NULL, id);
59 if (IS_ERR(clk))
60 return PTR_ERR(clk);
61
62 ret = clk_enable(clk);
63 if (ret)
64 clk_put(clk);
65
66 return ret;
67}
68 72
69/* the exported API, in addition to clk_set_rate */ 73/* the exported API, in addition to clk_set_rate */
70/** 74/**
@@ -96,4 +100,63 @@ enum clk_sh_algo_id {
96 100
97 IP_N1, 101 IP_N1,
98}; 102};
103
104struct clk_div_mult_table {
105 unsigned int *divisors;
106 unsigned int nr_divisors;
107 unsigned int *multipliers;
108 unsigned int nr_multipliers;
109};
110
111struct cpufreq_frequency_table;
112void clk_rate_table_build(struct clk *clk,
113 struct cpufreq_frequency_table *freq_table,
114 int nr_freqs,
115 struct clk_div_mult_table *src_table,
116 unsigned long *bitmap);
117
118long clk_rate_table_round(struct clk *clk,
119 struct cpufreq_frequency_table *freq_table,
120 unsigned long rate);
121
122int clk_rate_table_find(struct clk *clk,
123 struct cpufreq_frequency_table *freq_table,
124 unsigned long rate);
125
126#define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \
127 _enable_bit, _flags) \
128{ \
129 .name = _name, \
130 .id = _id, \
131 .parent = _parent, \
132 .enable_reg = (void __iomem *)_enable_reg, \
133 .enable_bit = _enable_bit, \
134 .flags = _flags, \
135}
136
137int sh_clk_mstp32_register(struct clk *clks, int nr);
138
139#define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \
140{ \
141 .name = _name, \
142 .parent = _parent, \
143 .enable_reg = (void __iomem *)_reg, \
144 .enable_bit = _shift, \
145 .arch_flags = _div_bitmap, \
146 .flags = _flags, \
147}
148
149int sh_clk_div4_register(struct clk *clks, int nr,
150 struct clk_div_mult_table *table);
151
152#define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
153{ \
154 .name = _name, \
155 .parent = _parent, \
156 .enable_reg = (void __iomem *)_reg, \
157 .flags = _flags, \
158}
159
160int sh_clk_div6_register(struct clk *clks, int nr);
161
99#endif /* __ASM_SH_CLOCK_H */ 162#endif /* __ASM_SH_CLOCK_H */
diff --git a/arch/sh/include/asm/cmpxchg-llsc.h b/arch/sh/include/asm/cmpxchg-llsc.h
index 0fac3da536ca..47136661a203 100644
--- a/arch/sh/include/asm/cmpxchg-llsc.h
+++ b/arch/sh/include/asm/cmpxchg-llsc.h
@@ -55,7 +55,7 @@ __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
55 "mov %0, %1 \n\t" 55 "mov %0, %1 \n\t"
56 "cmp/eq %1, %3 \n\t" 56 "cmp/eq %1, %3 \n\t"
57 "bf 2f \n\t" 57 "bf 2f \n\t"
58 "mov %3, %0 \n\t" 58 "mov %4, %0 \n\t"
59 "2: \n\t" 59 "2: \n\t"
60 "movco.l %0, @%2 \n\t" 60 "movco.l %0, @%2 \n\t"
61 "bf 1b \n\t" 61 "bf 1b \n\t"
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
10int platform_resource_setup_memory(struct platform_device *pdev, 10int platform_resource_setup_memory(struct platform_device *pdev,
11 char *name, unsigned long memsize); 11 char *name, unsigned long memsize);
12 12
13void plat_early_device_setup(void);
14
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 52b4b6238277..977355f0a483 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -13,18 +13,20 @@
13#define HD64461_PCC_WINDOW 0x01000000 13#define HD64461_PCC_WINDOW 0x01000000
14 14
15/* Area 6 - Slot 0 - memory and/or IO card */ 15/* Area 6 - Slot 0 - memory and/or IO card */
16#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 16#define HD64461_IOBASE 0xb0000000
17#define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
18#define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
17#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 19#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
18#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 20#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
19#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 21#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
20 22
21/* Area 5 - Slot 1 - memory card only */ 23/* Area 5 - Slot 1 - memory card only */
22#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 24#define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
23#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 25#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
24#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 26#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
25 27
26/* Standby Control Register for HD64461 */ 28/* Standby Control Register for HD64461 */
27#define HD64461_STBCR CONFIG_HD64461_IOBASE 29#define HD64461_STBCR HD64461_IO_OFFSET(0x00000000)
28#define HD64461_STBCR_CKIO_STBY 0x2000 30#define HD64461_STBCR_CKIO_STBY 0x2000
29#define HD64461_STBCR_SAFECKE_IST 0x1000 31#define HD64461_STBCR_SAFECKE_IST 0x1000
30#define HD64461_STBCR_SLCKE_IST 0x0800 32#define HD64461_STBCR_SLCKE_IST 0x0800
@@ -41,19 +43,19 @@
41#define HD64461_STBCR_SURTST 0x0001 43#define HD64461_STBCR_SURTST 0x0001
42 44
43/* System Configuration Register */ 45/* System Configuration Register */
44#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 46#define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
45 47
46/* CPU Data Bus Control Register */ 48/* CPU Data Bus Control Register */
47#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 49#define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
48 50
49/* Base Address Register */ 51/* Base Address Register */
50#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 52#define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
51 53
52/* Line increment address */ 54/* Line increment address */
53#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 55#define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
54 56
55/* Controls LCD controller */ 57/* Controls LCD controller */
56#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 58#define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
57 59
58/* LCCDR control bits */ 60/* LCCDR control bits */
59#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 61#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
@@ -64,30 +66,30 @@
64#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 66#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
65 67
66/* Controls LCD (1) */ 68/* Controls LCD (1) */
67#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 69#define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
68#define HD64461_LDR1_DON 0x01 /* Display On */ 70#define HD64461_LDR1_DON 0x01 /* Display On */
69#define HD64461_LDR1_DINV 0x80 /* Display Invert */ 71#define HD64461_LDR1_DINV 0x80 /* Display Invert */
70 72
71/* Controls LCD (2) */ 73/* Controls LCD (2) */
72#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 74#define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
73#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 75#define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
74#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 76#define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
75#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 77#define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
76#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 78#define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
77#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 79#define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
78 80
79/* Controls LCD (3) */ 81/* Controls LCD (3) */
80#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 82#define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
81 83
82/* Palette Registers */ 84/* Palette Registers */
83#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ 85#define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
84#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 86#define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
85#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ 87#define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
86#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 88#define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
87 89
88#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 90#define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
89#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 91#define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
90#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 92#define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
91 93
92#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 94#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
93#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 95#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
@@ -97,41 +99,41 @@
97#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 99#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98 100
99/* Line Drawing Registers */ 101/* Line Drawing Registers */
100#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ 102#define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
101#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ 103#define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
102#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 104#define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
103#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 105#define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
104#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 106#define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
105#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 107#define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
106#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 108#define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
107 109
108/* BitBLT Registers */ 110/* BitBLT Registers */
109#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ 111#define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
110#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ 112#define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
111#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ 113#define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
112#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ 114#define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
113#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 115#define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
114#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 116#define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
115#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ 117#define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
116#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ 118#define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
117#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ 119#define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
118#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ 120#define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
119#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 121#define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
120#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 122#define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
121 123
122/* PC Card Controller Registers */ 124/* PC Card Controller Registers */
123/* Maps to Physical Area 6 */ 125/* Maps to Physical Area 6 */
124#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 126#define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
125#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 127#define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
126#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 128#define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
127#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 129#define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
128#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 130#define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
129/* Maps to Physical Area 5 */ 131/* Maps to Physical Area 5 */
130#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 132#define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
131#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 133#define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
132#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 134#define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
133#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 135#define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
134#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 136#define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
135 137
136/* PCC Interface Status Register */ 138/* PCC Interface Status Register */
137#define HD64461_PCCISR_READY 0x80 /* card ready */ 139#define HD64461_PCCISR_READY 0x80 /* card ready */
@@ -189,41 +191,41 @@
189#define HD64461_PCCSCR_SWP 0x01 /* write protect */ 191#define HD64461_PCCSCR_SWP 0x01 /* write protect */
190 192
191/* PCC0 Output Pins Control Register */ 193/* PCC0 Output Pins Control Register */
192#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 194#define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
193 195
194/* PCC1 Output Pins Control Register */ 196/* PCC1 Output Pins Control Register */
195#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 197#define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
196 198
197/* PC Card General Control Register */ 199/* PC Card General Control Register */
198#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 200#define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
199 201
200/* Port Control Registers */ 202/* Port Control Registers */
201#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 203#define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
202#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 204#define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
203#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 205#define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
204#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 206#define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
205 207
206/* Port Control Data Registers */ 208/* Port Control Data Registers */
207#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 209#define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
208#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 210#define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
209#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 211#define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
210#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 212#define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
211 213
212/* Interrupt Control Registers */ 214/* Interrupt Control Registers */
213#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 215#define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
214#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 216#define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
215#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 217#define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
216#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 218#define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
217 219
218/* Interrupt Status Registers */ 220/* Interrupt Status Registers */
219#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 221#define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
220#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 222#define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
221#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 223#define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
222#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 224#define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
223 225
224/* Interrupt Request Register & Interrupt Mask Register */ 226/* Interrupt Request Register & Interrupt Mask Register */
225#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 227#define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
226#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 228#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
227 229
228#define HD64461_IRQBASE OFFCHIP_IRQ_BASE 230#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229#define OFFCHIP_IRQ_BASE 64 231#define OFFCHIP_IRQ_BASE 64
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0454f8d68059..25348141674b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -123,10 +123,15 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
123 123
124__BUILD_MEMORY_STRING(b, u8) 124__BUILD_MEMORY_STRING(b, u8)
125__BUILD_MEMORY_STRING(w, u16) 125__BUILD_MEMORY_STRING(w, u16)
126__BUILD_MEMORY_STRING(q, u64)
127 126
127#ifdef CONFIG_SUPERH32
128void __raw_writesl(void __iomem *addr, const void *data, int longlen); 128void __raw_writesl(void __iomem *addr, const void *data, int longlen);
129void __raw_readsl(const void __iomem *addr, void *data, int longlen); 129void __raw_readsl(const void __iomem *addr, void *data, int longlen);
130#else
131__BUILD_MEMORY_STRING(l, u32)
132#endif
133
134__BUILD_MEMORY_STRING(q, u64)
130 135
131#define writesb __raw_writesb 136#define writesb __raw_writesb
132#define writesw __raw_writesw 137#define writesw __raw_writesw
@@ -224,17 +229,6 @@ void __iomem *__ioremap(unsigned long offset, unsigned long size,
224 unsigned long flags); 229 unsigned long flags);
225void __iounmap(void __iomem *addr); 230void __iounmap(void __iomem *addr);
226 231
227/* arch/sh/mm/ioremap_64.c */
228unsigned long onchip_remap(unsigned long addr, unsigned long size,
229 const char *name);
230extern void onchip_unmap(unsigned long vaddr);
231#else
232#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
233#define __iounmap(addr) do { } while (0)
234#define onchip_remap(addr, size, name) (addr)
235#define onchip_unmap(addr) do { } while (0)
236#endif /* CONFIG_MMU */
237
238static inline void __iomem * 232static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) 233__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{ 234{
@@ -268,6 +262,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
268 262
269 return __ioremap(offset, size, flags); 263 return __ioremap(offset, size, flags);
270} 264}
265#else
266#define __ioremap_mode(offset, size, flags) ((void __iomem *)(offset))
267#define __iounmap(addr) do { } while (0)
268#endif /* CONFIG_MMU */
271 269
272#define ioremap(offset, size) \ 270#define ioremap(offset, size) \
273 __ioremap_mode((offset), (size), 0) 271 __ioremap_mode((offset), (size), 0)
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index d319baaf4fbd..a2b8c99cc06f 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -8,7 +8,8 @@
8 * advised to cap this at the hard limit that they're interested in 8 * advised to cap this at the hard limit that they're interested in
9 * through the machvec. 9 * through the machvec.
10 */ 10 */
11#define NR_IRQS 256 11#define NR_IRQS 256
12#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */
12 13
13/* 14/*
14 * Convert back and forth between INTEVT and IRQ values. 15 * Convert back and forth between INTEVT and IRQ values.
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 613644a758e8..036c3311233c 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -6,7 +6,7 @@
6#include <linux/types.h> 6#include <linux/types.h>
7#include <linux/ptrace.h> 7#include <linux/ptrace.h>
8 8
9typedef u16 kprobe_opcode_t; 9typedef insn_size_t kprobe_opcode_t;
10#define BREAKPOINT_INSTRUCTION 0xc33a 10#define BREAKPOINT_INSTRUCTION 0xc33a
11 11
12#define MAX_INSN_SIZE 16 12#define MAX_INSN_SIZE 16
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 64b1c16a0f03..84dd37761f56 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -46,6 +46,9 @@ struct sh_machine_vector {
46 46
47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); 47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
48 void (*mv_ioport_unmap)(void __iomem *); 48 void (*mv_ioport_unmap)(void __iomem *);
49
50 int (*mv_clk_init)(void);
51 int (*mv_mode_pins)(void);
49}; 52};
50 53
51extern struct sh_machine_vector sh_mv; 54extern struct sh_machine_vector sh_mv;
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index df1d383e18a5..ae0da6f48b6d 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -17,54 +17,29 @@
17 * external) PCI controllers. 17 * external) PCI controllers.
18 */ 18 */
19struct pci_channel { 19struct pci_channel {
20 struct pci_ops *pci_ops; 20 struct pci_channel *next;
21 struct resource *io_resource;
22 struct resource *mem_resource;
23 int first_devfn;
24 int last_devfn;
25};
26 21
27/* 22 struct pci_ops *pci_ops;
28 * Each board initializes this array and terminates it with a NULL entry. 23 struct resource *io_resource;
29 */ 24 struct resource *mem_resource;
30extern struct pci_channel board_pci_channels[];
31 25
32#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start 26 unsigned long io_offset;
33#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start 27 unsigned long mem_offset;
34 28
35/* 29 unsigned long reg_base;
36 * I/O routine helpers
37 */
38#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
39#define PCI_IO_AREA 0xFE400000
40#define PCI_IO_SIZE 0x00400000
41#elif defined(CONFIG_CPU_SH5)
42extern unsigned long PCI_IO_AREA;
43#define PCI_IO_SIZE 0x00010000
44#else
45#define PCI_IO_AREA 0xFE240000
46#define PCI_IO_SIZE 0x00040000
47#endif
48 30
49#define PCI_MEM_SIZE 0x01000000 31 unsigned long io_map_base;
32};
50 33
51#define SH4_PCIIOBR_MASK 0xFFFC0000 34extern void register_pci_controller(struct pci_channel *hose);
52#define pci_ioaddr(addr) (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
53 35
54#if defined(CONFIG_PCI) 36extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
55#define is_pci_ioaddr(port) \
56 (((port) >= PCIBIOS_MIN_IO) && \
57 ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
58#define is_pci_memaddr(port) \
59 (((port) >= PCIBIOS_MIN_MEM) && \
60 ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
61#else
62#define is_pci_ioaddr(port) (0)
63#define is_pci_memaddr(port) (0)
64#endif
65 37
66struct pci_dev; 38struct pci_dev;
67 39
40#define HAVE_PCI_MMAP
41extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
42 enum pci_mmap_state mmap_state, int write_combine);
68extern void pcibios_set_master(struct pci_dev *dev); 43extern void pcibios_set_master(struct pci_dev *dev);
69 44
70static inline void pcibios_penalize_isa_irq(int irq, int active) 45static inline void pcibios_penalize_isa_irq(int irq, int active)
@@ -114,31 +89,76 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
114#endif 89#endif
115 90
116#ifdef CONFIG_PCI 91#ifdef CONFIG_PCI
92/*
93 * None of the SH PCI controllers support MWI, it is always treated as a
94 * direct memory write.
95 */
96#define PCI_DISABLE_MWI
97
117static inline void pci_dma_burst_advice(struct pci_dev *pdev, 98static inline void pci_dma_burst_advice(struct pci_dev *pdev,
118 enum pci_dma_burst_strategy *strat, 99 enum pci_dma_burst_strategy *strat,
119 unsigned long *strategy_parameter) 100 unsigned long *strategy_parameter)
120{ 101{
121 *strat = PCI_DMA_BURST_INFINITY; 102 unsigned long cacheline_size;
122 *strategy_parameter = ~0UL; 103 u8 byte;
104
105 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
106
107 if (byte == 0)
108 cacheline_size = L1_CACHE_BYTES;
109 else
110 cacheline_size = byte << 2;
111
112 *strat = PCI_DMA_BURST_MULTIPLE;
113 *strategy_parameter = cacheline_size;
123} 114}
124#endif 115#endif
125 116
117#ifdef CONFIG_SUPERH32
118/*
119 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
120 * at the end of the address space in a special non-translatable area.
121 */
122#define PCI_MEM_FIXED_START 0xfd000000
123#define PCI_MEM_FIXED_END (PCI_MEM_FIXED_START + 0x01000000)
124
125#define is_pci_memory_fixed_range(s, e) \
126 ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
127#else
128#define is_pci_memory_fixed_range(s, e) (0)
129#endif
130
126/* Board-specific fixup routines. */ 131/* Board-specific fixup routines. */
127void pcibios_fixup(void);
128int pcibios_init_platform(void);
129int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); 132int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
130 133
131#ifdef CONFIG_PCI_AUTO 134extern void pcibios_resource_to_bus(struct pci_dev *dev,
132int pciauto_assign_resources(int busno, struct pci_channel *hose); 135 struct pci_bus_region *region, struct resource *res);
133#endif
134 136
135#endif /* __KERNEL__ */ 137extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
138 struct pci_bus_region *region);
136 139
137/* generic pci stuff */ 140static inline struct resource *
138#include <asm-generic/pci.h> 141pcibios_select_root(struct pci_dev *pdev, struct resource *res)
142{
143 struct resource *root = NULL;
144
145 if (res->flags & IORESOURCE_IO)
146 root = &ioport_resource;
147 if (res->flags & IORESOURCE_MEM)
148 root = &iomem_resource;
149
150 return root;
151}
152
153/* Chances are this interrupt is wired PC-style ... */
154static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
155{
156 return channel ? 15 : 14;
157}
139 158
140/* generic DMA-mapping stuff */ 159/* generic DMA-mapping stuff */
141#include <asm-generic/pci-dma-compat.h> 160#include <asm-generic/pci-dma-compat.h>
142 161
162#endif /* __KERNEL__ */
143#endif /* __ASM_SH_PCI_H */ 163#endif /* __ASM_SH_PCI_H */
144 164
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index b517ae08b9c0..2a011b18090b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -154,6 +154,10 @@ extern void kmap_coherent_init(void);
154#define kmap_coherent_init() do { } while (0) 154#define kmap_coherent_init() do { } while (0)
155#endif 155#endif
156 156
157/* arch/sh/mm/mmap.c */
158#define HAVE_ARCH_UNMAPPED_AREA
159#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
160
157#include <asm-generic/pgtable.h> 161#include <asm-generic/pgtable.h>
158 162
159#endif /* __ASM_SH_PGTABLE_H */ 163#endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..ff7daaf9a620 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
@@ -94,6 +94,27 @@ extern struct pt_regs fake_swapper_regs;
94const char *get_cpu_subtype(struct sh_cpuinfo *c); 94const char *get_cpu_subtype(struct sh_cpuinfo *c);
95extern const struct seq_operations cpuinfo_op; 95extern const struct seq_operations cpuinfo_op;
96 96
97/* processor boot mode configuration */
98#define MODE_PIN0 (1 << 0)
99#define MODE_PIN1 (1 << 1)
100#define MODE_PIN2 (1 << 2)
101#define MODE_PIN3 (1 << 3)
102#define MODE_PIN4 (1 << 4)
103#define MODE_PIN5 (1 << 5)
104#define MODE_PIN6 (1 << 6)
105#define MODE_PIN7 (1 << 7)
106#define MODE_PIN8 (1 << 8)
107#define MODE_PIN9 (1 << 9)
108#define MODE_PIN10 (1 << 10)
109#define MODE_PIN11 (1 << 11)
110#define MODE_PIN12 (1 << 12)
111#define MODE_PIN13 (1 << 13)
112#define MODE_PIN14 (1 << 14)
113#define MODE_PIN15 (1 << 15)
114
115int generic_mode_pins(void);
116int test_mode_pin(int pin);
117
97#ifdef CONFIG_VSYSCALL 118#ifdef CONFIG_VSYSCALL
98int vsyscall_init(void); 119int vsyscall_init(void);
99#else 120#else
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 68e20ff9aa9b..1dc12cb44a2d 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -102,6 +102,11 @@ struct pt_dspregs {
102#define PTRACE_GETDSPREGS 55 /* DSP registers */ 102#define PTRACE_GETDSPREGS 55 /* DSP registers */
103#define PTRACE_SETDSPREGS 56 103#define PTRACE_SETDSPREGS 56
104 104
105#define PT_TEXT_END_ADDR 240
106#define PT_TEXT_ADDR 244 /* &(struct user)->start_code */
107#define PT_DATA_ADDR 248 /* &(struct user)->start_data */
108#define PT_TEXT_LEN 252
109
105#ifdef __KERNEL__ 110#ifdef __KERNEL__
106#include <asm/addrspace.h> 111#include <asm/addrspace.h>
107 112
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
index f7b010d48af7..52b0c2dba979 100644
--- a/arch/sh/include/asm/rtc.h
+++ b/arch/sh/include/asm/rtc.h
@@ -6,6 +6,17 @@ extern void (*board_time_init)(void);
6extern void (*rtc_sh_get_time)(struct timespec *); 6extern void (*rtc_sh_get_time)(struct timespec *);
7extern int (*rtc_sh_set_time)(const time_t); 7extern int (*rtc_sh_set_time)(const time_t);
8 8
9/* some dummy definitions */
10#define RTC_BATT_BAD 0x100 /* battery bad */
11#define RTC_SQWE 0x08 /* enable square-wave output */
12#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
13#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
14#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
15
16struct rtc_time;
17unsigned int get_rtc_time(struct rtc_time *);
18int set_rtc_time(struct rtc_time *);
19
9#define RTC_CAP_4_DIGIT_YEAR (1 << 0) 20#define RTC_CAP_4_DIGIT_YEAR (1 << 0)
10 21
11struct sh_rtc_platform_info { 22struct sh_rtc_platform_info {
diff --git a/arch/sh/include/asm/spinlock.h b/arch/sh/include/asm/spinlock.h
index 60283565f89b..a28c9f0053fd 100644
--- a/arch/sh/include/asm/spinlock.h
+++ b/arch/sh/include/asm/spinlock.h
@@ -26,7 +26,7 @@
26#define __raw_spin_is_locked(x) ((x)->lock <= 0) 26#define __raw_spin_is_locked(x) ((x)->lock <= 0)
27#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 27#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
28#define __raw_spin_unlock_wait(x) \ 28#define __raw_spin_unlock_wait(x) \
29 do { cpu_relax(); } while ((x)->lock) 29 do { while (__raw_spin_is_locked(x)) cpu_relax(); } while (0)
30 30
31/* 31/*
32 * Simple spin lock operations. There are two variants, one clears IRQ's 32 * Simple spin lock operations. There are two variants, one clears IRQ's
diff --git a/arch/sh/include/asm/swab.h b/arch/sh/include/asm/swab.h
index e69315935107..0e08fe54ad71 100644
--- a/arch/sh/include/asm/swab.h
+++ b/arch/sh/include/asm/swab.h
@@ -14,15 +14,15 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
14{ 14{
15 __asm__( 15 __asm__(
16#ifdef __SH5__ 16#ifdef __SH5__
17 "byterev %0, %0\n\t" 17 "byterev %1, %0\n\t"
18 "shari %0, 32, %0" 18 "shari %0, 32, %0"
19#else 19#else
20 "swap.b %0, %0\n\t" 20 "swap.b %1, %0\n\t"
21 "swap.w %0, %0\n\t" 21 "swap.w %0, %0\n\t"
22 "swap.b %0, %0" 22 "swap.b %0, %0"
23#endif 23#endif
24 : "=r" (x) 24 : "=r" (x)
25 : "0" (x)); 25 : "r" (x));
26 26
27 return x; 27 return x;
28} 28}
@@ -32,13 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
32{ 32{
33 __asm__( 33 __asm__(
34#ifdef __SH5__ 34#ifdef __SH5__
35 "byterev %0, %0\n\t" 35 "byterev %1, %0\n\t"
36 "shari %0, 32, %0" 36 "shari %0, 32, %0"
37#else 37#else
38 "swap.b %0, %0" 38 "swap.b %1, %0"
39#endif 39#endif
40 : "=r" (x) 40 : "=r" (x)
41 : "0" (x)); 41 : "r" (x));
42 42
43 return x; 43 return x;
44} 44}
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 240b31e1142c..6c68a51f1cc5 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -198,7 +198,7 @@ do { \
198}) 198})
199#endif 199#endif
200 200
201int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, 201int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
202 struct mem_access *ma); 202 struct mem_access *ma);
203 203
204asmlinkage void do_address_error(struct pt_regs *regs, 204asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
deleted file mode 100644
index 4c3b66e30af2..000000000000
--- a/arch/sh/include/asm/timer.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef __ASM_SH_TIMER_H
2#define __ASM_SH_TIMER_H
3
4#include <linux/sysdev.h>
5#include <linux/clocksource.h>
6#include <cpu/timer.h>
7
8struct sys_timer_ops {
9 int (*init)(void);
10 int (*start)(void);
11 int (*stop)(void);
12#ifndef CONFIG_GENERIC_TIME
13 unsigned long (*get_offset)(void);
14#endif
15};
16
17struct sys_timer {
18 const char *name;
19
20 struct sys_device dev;
21 struct sys_timer_ops *ops;
22};
23
24#define TICK_SIZE (tick_nsec / 1000)
25
26extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
27extern struct sys_timer *sys_timer;
28
29#ifndef CONFIG_GENERIC_TIME
30static inline unsigned long get_timer_offset(void)
31{
32 return sys_timer->ops->get_offset();
33}
34#endif
35
36/* arch/sh/kernel/timers/timer.c */
37struct sys_timer *get_sys_timer(void);
38
39/* arch/sh/kernel/time.c */
40void handle_timer_tick(void);
41
42extern struct clocksource clocksource_sh;
43
44#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index beea4e6f8dfd..b13caca62a76 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -23,9 +23,9 @@ typedef unsigned short umode_t;
23typedef u32 dma_addr_t; 23typedef u32 dma_addr_t;
24 24
25#ifdef CONFIG_SUPERH32 25#ifdef CONFIG_SUPERH32
26typedef u16 opcode_t; 26typedef u16 insn_size_t;
27#else 27#else
28typedef u32 opcode_t; 28typedef u32 insn_size_t;
29#endif 29#endif
30 30
31#endif /* __ASSEMBLY__ */ 31#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
index a7b9028bbfbb..4ca4b7717371 100644
--- a/arch/sh/include/asm/ubc.h
+++ b/arch/sh/include/asm/ubc.h
@@ -42,12 +42,23 @@
42 42
43#define BRCR_CMFA (1 << 15) 43#define BRCR_CMFA (1 << 15)
44#define BRCR_CMFB (1 << 14) 44#define BRCR_CMFB (1 << 14)
45
46#if defined CONFIG_CPU_SH2A
47#define BRCR_CMFCA (1 << 15)
48#define BRCR_CMFCB (1 << 14)
49#define BRCR_CMFDA (1 << 13)
50#define BRCR_CMFDB (1 << 12)
51#define BRCR_PCBB (1 << 6) /* 1: after execution */
52#define BRCR_PCBA (1 << 5) /* 1: after execution */
53#define BRCR_PCTE 0
54#else
45#define BRCR_PCTE (1 << 11) 55#define BRCR_PCTE (1 << 11)
46#define BRCR_PCBA (1 << 10) /* 1: after execution */ 56#define BRCR_PCBA (1 << 10) /* 1: after execution */
47#define BRCR_DBEB (1 << 7) 57#define BRCR_DBEB (1 << 7)
48#define BRCR_PCBB (1 << 6) 58#define BRCR_PCBB (1 << 6)
49#define BRCR_SEQ (1 << 3) 59#define BRCR_SEQ (1 << 3)
50#define BRCR_UBDE (1 << 0) 60#define BRCR_UBDE (1 << 0)
61#endif
51 62
52#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
53/* arch/sh/kernel/cpu/ubc.S */ 64/* arch/sh/kernel/cpu/ubc.S */
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index d8f89770275b..9f4dd252c981 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -3,9 +3,9 @@
3 3
4/* 4/*
5 * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. 5 * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
6 * Support for 16 and 64-bit accesses are done through shifting and 6 * Support for 64-bit accesses are done through shifting and masking
7 * masking relative to the endianness. Unaligned stores are not supported 7 * relative to the endianness. Unaligned stores are not supported by the
8 * by the instruction encoding, so these continue to use the packed 8 * instruction encoding, so these continue to use the packed
9 * struct. 9 * struct.
10 * 10 *
11 * The same note as with the movli.l/movco.l pair applies here, as long 11 * The same note as with the movli.l/movco.l pair applies here, as long
@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); };
41static inline u16 __get_unaligned_cpu16(const u8 *p) 41static inline u16 __get_unaligned_cpu16(const u8 *p)
42{ 42{
43#ifdef __LITTLE_ENDIAN 43#ifdef __LITTLE_ENDIAN
44 return __get_unaligned_cpu32(p) & 0xffff; 44 return p[0] | p[1] << 8;
45#else 45#else
46 return __get_unaligned_cpu32(p) >> 16; 46 return p[0] << 8 | p[1];
47#endif 47#endif
48} 48}
49 49
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 2efb819e2db3..65197086a1c5 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -343,8 +343,9 @@
343#define __NR_inotify_init1 332 343#define __NR_inotify_init1 332
344#define __NR_preadv 333 344#define __NR_preadv 333
345#define __NR_pwritev 334 345#define __NR_pwritev 334
346#define __NR_rt_tgsigqueueinfo 335
346 347
347#define NR_syscalls 335 348#define NR_syscalls 336
348 349
349#ifdef __KERNEL__ 350#ifdef __KERNEL__
350 351
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 6eb9d2934c0f..8014aea88ec3 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -383,10 +383,11 @@
383#define __NR_inotify_init1 360 383#define __NR_inotify_init1 360
384#define __NR_preadv 361 384#define __NR_preadv 361
385#define __NR_pwritev 362 385#define __NR_pwritev 362
386#define __NR_rt_tgsigqueueinfo 363
386 387
387#ifdef __KERNEL__ 388#ifdef __KERNEL__
388 389
389#define NR_syscalls 363 390#define NR_syscalls 364
390 391
391#define __ARCH_WANT_IPC_PARSE_VERSION 392#define __ARCH_WANT_IPC_PARSE_VERSION
392#define __ARCH_WANT_OLD_READDIR 393#define __ARCH_WANT_OLD_READDIR
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 18:42:07 -0500