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-rw-r--r--arch/sh/include/asm/watchdog.h107
1 files changed, 107 insertions, 0 deletions
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
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1/*
2 * include/asm-sh/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef __ASM_SH_WATCHDOG_H
12#define __ASM_SH_WATCHDOG_H
13#ifdef __KERNEL__
14
15#include <linux/types.h>
16#include <cpu/watchdog.h>
17#include <asm/io.h>
18
19/*
20 * See cpu-sh2/watchdog.h for explanation of this stupidity..
21 */
22#ifndef WTCNT_R
23# define WTCNT_R WTCNT
24#endif
25
26#ifndef WTCSR_R
27# define WTCSR_R WTCSR
28#endif
29
30#define WTCNT_HIGH 0x5a
31#define WTCSR_HIGH 0xa5
32
33#define WTCSR_CKS2 0x04
34#define WTCSR_CKS1 0x02
35#define WTCSR_CKS0 0x01
36
37/*
38 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
39 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
40 * something a little more reasonable, and really can't deal with anything
41 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
42 *
43 * Clock Division Ratio Overflow Period
44 * --------------------------------------------
45 * 1/32 (initial value) 41 usecs
46 * 1/64 82 usecs
47 * 1/128 164 usecs
48 * 1/256 328 usecs
49 * 1/512 656 usecs
50 * 1/1024 1.31 msecs
51 * 1/2048 2.62 msecs
52 * 1/4096 5.25 msecs
53 */
54#define WTCSR_CKS_32 0x00
55#define WTCSR_CKS_64 0x01
56#define WTCSR_CKS_128 0x02
57#define WTCSR_CKS_256 0x03
58#define WTCSR_CKS_512 0x04
59#define WTCSR_CKS_1024 0x05
60#define WTCSR_CKS_2048 0x06
61#define WTCSR_CKS_4096 0x07
62
63/**
64 * sh_wdt_read_cnt - Read from Counter
65 * Reads back the WTCNT value.
66 */
67static inline __u8 sh_wdt_read_cnt(void)
68{
69 return ctrl_inb(WTCNT_R);
70}
71
72/**
73 * sh_wdt_write_cnt - Write to Counter
74 * @val: Value to write
75 *
76 * Writes the given value @val to the lower byte of the timer counter.
77 * The upper byte is set manually on each write.
78 */
79static inline void sh_wdt_write_cnt(__u8 val)
80{
81 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
82}
83
84/**
85 * sh_wdt_read_csr - Read from Control/Status Register
86 *
87 * Reads back the WTCSR value.
88 */
89static inline __u8 sh_wdt_read_csr(void)
90{
91 return ctrl_inb(WTCSR_R);
92}
93
94/**
95 * sh_wdt_write_csr - Write to Control/Status Register
96 * @val: Value to write
97 *
98 * Writes the given value @val to the lower byte of the control/status
99 * register. The upper byte is set manually on each write.
100 */
101static inline void sh_wdt_write_csr(__u8 val)
102{
103 ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
104}
105
106#endif /* __KERNEL__ */
107#endif /* __ASM_SH_WATCHDOG_H */