1 files changed, 250 insertions, 0 deletions
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
new file mode 100644
index 000000000000..8c1353baf00f
--- /dev/null
+++ b/arch/sh/include/asm/hd64461.h
@@ -0,0 +1,250 @@
+#ifndef __ASM_SH_HD64461
+#define __ASM_SH_HD64461
+/*
+ *      Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *      Copyright (C) 2004 Paul Mundt
+ *      Copyright (C) 2000 YAEGASHI Takeshi
+ *
+ *              Hitachi HD64461 companion chip support
+ *      (please note manual reference 0x10000000 = 0xb0000000)
+ */
+/* Constants for PCMCIA mappings */
+#define HD64461_PCC_WINDOW      0x01000000
+/* Area 6 - Slot 0 - memory and/or IO card */
+#define HD64461_PCC0_BASE       (CONFIG_HD64461_IOBASE + 0x8000000)
+#define HD64461_PCC0_ATTR       (HD64461_PCC0_BASE)                             /* 0xb80000000 */
+#define HD64461_PCC0_COMM       (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)          /* 0xb90000000 */
+#define HD64461_PCC0_IO         (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)        /* 0xba0000000 */
+/* Area 5 - Slot 1 - memory card only */
+#define HD64461_PCC1_BASE       (CONFIG_HD64461_IOBASE + 0x4000000)
+#define HD64461_PCC1_ATTR       (HD64461_PCC1_BASE)                             /* 0xb4000000 */
+#define HD64461_PCC1_COMM       (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)          /* 0xb5000000 */
+/* Standby Control Register for HD64461 */
+#define HD64461_STBCR                   CONFIG_HD64461_IOBASE
+#define HD64461_STBCR_CKIO_STBY         0x2000
+#define HD64461_STBCR_SAFECKE_IST       0x1000
+#define HD64461_STBCR_SLCKE_IST         0x0800
+#define HD64461_STBCR_SAFECKE_OST       0x0400
+#define HD64461_STBCR_SLCKE_OST         0x0200
+#define HD64461_STBCR_SMIAST            0x0100
+#define HD64461_STBCR_SLCDST            0x0080
+#define HD64461_STBCR_SPC0ST            0x0040
+#define HD64461_STBCR_SPC1ST            0x0020
+#define HD64461_STBCR_SAFEST            0x0010
+#define HD64461_STBCR_STM0ST            0x0008
+#define HD64461_STBCR_STM1ST            0x0004
+#define HD64461_STBCR_SIRST             0x0002
+#define HD64461_STBCR_SURTST            0x0001
+/* System Configuration Register */
+#define HD64461_SYSCR           (CONFIG_HD64461_IOBASE + 0x02)
+/* CPU Data Bus Control Register */
+#define HD64461_SCPUCR          (CONFIG_HD64461_IOBASE + 0x04)
+/* Base Address Register */
+#define HD64461_LCDCBAR         (CONFIG_HD64461_IOBASE + 0x1000)
+/* Line increment address */
+#define HD64461_LCDCLOR         (CONFIG_HD64461_IOBASE + 0x1002)
+/* Controls LCD controller */
+#define HD64461_LCDCCR          (CONFIG_HD64461_IOBASE + 0x1004)
+/* LCCDR control bits */
+#define HD64461_LCDCCR_STBACK   0x0400  /* Standby Back */
+#define HD64461_LCDCCR_STREQ    0x0100  /* Standby Request */
+#define HD64461_LCDCCR_MOFF     0x0080  /* Memory Off */
+#define HD64461_LCDCCR_REFSEL   0x0040  /* Refresh Select */
+#define HD64461_LCDCCR_EPON     0x0020  /* End Power On */
+#define HD64461_LCDCCR_SPON     0x0010  /* Start Power On */
+/* Controls LCD (1) */
+#define HD64461_LDR1            (CONFIG_HD64461_IOBASE + 0x1010)
+#define HD64461_LDR1_DON        0x01    /* Display On */
+#define HD64461_LDR1_DINV       0x80    /* Display Invert */
+/* Controls LCD (2) */
+#define HD64461_LDR2            (CONFIG_HD64461_IOBASE + 0x1012)
+#define HD64461_LDHNCR          (CONFIG_HD64461_IOBASE + 0x1014)        /* Number of horizontal characters */
+#define HD64461_LDHNSR          (CONFIG_HD64461_IOBASE + 0x1016)        /* Specify output start position + width of CL1 */
+#define HD64461_LDVNTR          (CONFIG_HD64461_IOBASE + 0x1018)        /* Specify total vertical lines */
+#define HD64461_LDVNDR          (CONFIG_HD64461_IOBASE + 0x101a)        /* specify number of display vertical lines */
+#define HD64461_LDVSPR          (CONFIG_HD64461_IOBASE + 0x101c)        /* specify vertical synchronization pos and AC nr */
+/* Controls LCD (3) */
+#define HD64461_LDR3            (CONFIG_HD64461_IOBASE + 0x101e)
+/* Palette Registers */
+#define HD64461_CPTWAR          (CONFIG_HD64461_IOBASE + 0x1030)        /* Color Palette Write Address Register */
+#define HD64461_CPTWDR          (CONFIG_HD64461_IOBASE + 0x1032)        /* Color Palette Write Data Register */
+#define HD64461_CPTRAR          (CONFIG_HD64461_IOBASE + 0x1034)        /* Color Palette Read Address Register */
+#define HD64461_CPTRDR          (CONFIG_HD64461_IOBASE + 0x1036)        /* Color Palette Read Data Register */
+#define HD64461_GRDOR           (CONFIG_HD64461_IOBASE + 0x1040)        /* Display Resolution Offset Register */
+#define HD64461_GRSCR           (CONFIG_HD64461_IOBASE + 0x1042)        /* Solid Color Register */
+#define HD64461_GRCFGR          (CONFIG_HD64461_IOBASE + 0x1044)        /* Accelerator Configuration Register */
+#define HD64461_GRCFGR_ACCSTATUS        0x10    /* Accelerator Status */
+#define HD64461_GRCFGR_ACCRESET         0x08    /* Accelerator Reset */
+#define HD64461_GRCFGR_ACCSTART_BITBLT  0x06    /* Accelerator Start BITBLT */
+#define HD64461_GRCFGR_ACCSTART_LINE    0x04    /* Accelerator Start Line Drawing */
+#define HD64461_GRCFGR_COLORDEPTH16     0x01    /* Sets Colordepth 16 for Accelerator */
+#define HD64461_GRCFGR_COLORDEPTH8      0x01    /* Sets Colordepth 8 for Accelerator */
+/* Line Drawing Registers */
+#define HD64461_LNSARH          (CONFIG_HD64461_IOBASE + 0x1046)        /* Line Start Address Register (H) */
+#define HD64461_LNSARL          (CONFIG_HD64461_IOBASE + 0x1048)        /* Line Start Address Register (L) */
+#define HD64461_LNAXLR          (CONFIG_HD64461_IOBASE + 0x104a)        /* Axis Pixel Length Register */
+#define HD64461_LNDGR           (CONFIG_HD64461_IOBASE + 0x104c)        /* Diagonal Register */
+#define HD64461_LNAXR           (CONFIG_HD64461_IOBASE + 0x104e)        /* Axial Register */
+#define HD64461_LNERTR          (CONFIG_HD64461_IOBASE + 0x1050)        /* Start Error Term Register */
+#define HD64461_LNMDR           (CONFIG_HD64461_IOBASE + 0x1052)        /* Line Mode Register */
+/* BitBLT Registers */
+#define HD64461_BBTSSARH        (CONFIG_HD64461_IOBASE + 0x1054)        /* Source Start Address Register (H) */
+#define HD64461_BBTSSARL        (CONFIG_HD64461_IOBASE + 0x1056)        /* Source Start Address Register (L) */
+#define HD64461_BBTDSARH        (CONFIG_HD64461_IOBASE + 0x1058)        /* Destination Start Address Register (H) */
+#define HD64461_BBTDSARL        (CONFIG_HD64461_IOBASE + 0x105a)        /* Destination Start Address Register (L) */
+#define HD64461_BBTDWR          (CONFIG_HD64461_IOBASE + 0x105c)        /* Destination Block Width Register */
+#define HD64461_BBTDHR          (CONFIG_HD64461_IOBASE + 0x105e)        /* Destination Block Height Register */
+#define HD64461_BBTPARH         (CONFIG_HD64461_IOBASE + 0x1060)        /* Pattern Start Address Register (H) */
+#define HD64461_BBTPARL         (CONFIG_HD64461_IOBASE + 0x1062)        /* Pattern Start Address Register (L) */
+#define HD64461_BBTMARH         (CONFIG_HD64461_IOBASE + 0x1064)        /* Mask Start Address Register (H) */
+#define HD64461_BBTMARL         (CONFIG_HD64461_IOBASE + 0x1066)        /* Mask Start Address Register (L) */
+#define HD64461_BBTROPR         (CONFIG_HD64461_IOBASE + 0x1068)        /* ROP Register */
+#define HD64461_BBTMDR          (CONFIG_HD64461_IOBASE + 0x106a)        /* BitBLT Mode Register */
+/* PC Card Controller Registers */
+/* Maps to Physical Area 6 */
+#define HD64461_PCC0ISR         (CONFIG_HD64461_IOBASE + 0x2000)        /* socket 0 interface status */
+#define HD64461_PCC0GCR         (CONFIG_HD64461_IOBASE + 0x2002)        /* socket 0 general control */
+#define HD64461_PCC0CSCR        (CONFIG_HD64461_IOBASE + 0x2004)        /* socket 0 card status change */
+#define HD64461_PCC0CSCIER      (CONFIG_HD64461_IOBASE + 0x2006)        /* socket 0 card status change interrupt enable */
+#define HD64461_PCC0SCR         (CONFIG_HD64461_IOBASE + 0x2008)        /* socket 0 software control */
+/* Maps to Physical Area 5 */
+#define HD64461_PCC1ISR         (CONFIG_HD64461_IOBASE + 0x2010)        /* socket 1 interface status */
+#define HD64461_PCC1GCR         (CONFIG_HD64461_IOBASE + 0x2012)        /* socket 1 general control */
+#define HD64461_PCC1CSCR        (CONFIG_HD64461_IOBASE + 0x2014)        /* socket 1 card status change */
+#define HD64461_PCC1CSCIER      (CONFIG_HD64461_IOBASE + 0x2016)        /* socket 1 card status change interrupt enable */
+#define HD64461_PCC1SCR         (CONFIG_HD64461_IOBASE + 0x2018)        /* socket 1 software control */
+/* PCC Interface Status Register */
+#define HD64461_PCCISR_READY            0x80    /* card ready */
+#define HD64461_PCCISR_MWP              0x40    /* card write-protected */
+#define HD64461_PCCISR_VS2              0x20    /* voltage select pin 2 */
+#define HD64461_PCCISR_VS1              0x10    /* voltage select pin 1 */
+#define HD64461_PCCISR_CD2              0x08    /* card detect 2 */
+#define HD64461_PCCISR_CD1              0x04    /* card detect 1 */
+#define HD64461_PCCISR_BVD2             0x02    /* battery 1 */
+#define HD64461_PCCISR_BVD1             0x01    /* battery 1 */
+#define HD64461_PCCISR_PCD_MASK         0x0c    /* card detect */
+#define HD64461_PCCISR_BVD_MASK         0x03    /* battery voltage */
+#define HD64461_PCCISR_BVD_BATGOOD      0x03    /* battery good */
+#define HD64461_PCCISR_BVD_BATWARN      0x01    /* battery low warning */
+#define HD64461_PCCISR_BVD_BATDEAD1     0x02    /* battery dead */
+#define HD64461_PCCISR_BVD_BATDEAD2     0x00    /* battery dead */
+/* PCC General Control Register */
+#define HD64461_PCCGCR_DRVE             0x80    /* output drive */
+#define HD64461_PCCGCR_PCCR             0x40    /* PC card reset */
+#define HD64461_PCCGCR_PCCT             0x20    /* PC card type, 1=IO&mem, 0=mem */
+#define HD64461_PCCGCR_VCC0             0x10    /* voltage control pin VCC0SEL0 */
+#define HD64461_PCCGCR_PMMOD            0x08    /* memory mode */
+#define HD64461_PCCGCR_PA25             0x04    /* pin A25 */
+#define HD64461_PCCGCR_PA24             0x02    /* pin A24 */
+#define HD64461_PCCGCR_REG              0x01    /* pin PCC0REG# */
+/* PCC Card Status Change Register */
+#define HD64461_PCCCSCR_SCDI            0x80    /* sw card detect intr */
+#define HD64461_PCCCSCR_SRV1            0x40    /* reserved */
+#define HD64461_PCCCSCR_IREQ            0x20    /* IREQ intr req */
+#define HD64461_PCCCSCR_SC              0x10    /* STSCHG (status change) pin */
+#define HD64461_PCCCSCR_CDC             0x08    /* CD (card detect) change */
+#define HD64461_PCCCSCR_RC              0x04    /* READY change */
+#define HD64461_PCCCSCR_BW              0x02    /* battery warning change */
+#define HD64461_PCCCSCR_BD              0x01    /* battery dead change */
+/* PCC Card Status Change Interrupt Enable Register */
+#define HD64461_PCCCSCIER_CRE           0x80    /* change reset enable */
+#define HD64461_PCCCSCIER_IREQE_MASK    0x60    /* IREQ enable */
+#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00   /* IREQ disabled */
+#define HD64461_PCCCSCIER_IREQE_LEVEL   0x20    /* IREQ level-triggered */
+#define HD64461_PCCCSCIER_IREQE_FALLING 0x40    /* IREQ falling-edge-trig */
+#define HD64461_PCCCSCIER_IREQE_RISING  0x60    /* IREQ rising-edge-trig */
+#define HD64461_PCCCSCIER_SCE           0x10    /* status change enable */
+#define HD64461_PCCCSCIER_CDE           0x08    /* card detect change enable */
+#define HD64461_PCCCSCIER_RE            0x04    /* ready change enable */
+#define HD64461_PCCCSCIER_BWE           0x02    /* battery warn change enable */
+#define HD64461_PCCCSCIER_BDE           0x01    /* battery dead change enable*/
+/* PCC Software Control Register */
+#define HD64461_PCCSCR_VCC1             0x02    /* voltage control pin 1 */
+#define HD64461_PCCSCR_SWP              0x01    /* write protect */
+/* PCC0 Output Pins Control Register */
+#define HD64461_P0OCR           (CONFIG_HD64461_IOBASE + 0x202a)
+/* PCC1 Output Pins Control Register */
+#define HD64461_P1OCR           (CONFIG_HD64461_IOBASE + 0x202c)
+/* PC Card General Control Register */
+#define HD64461_PGCR            (CONFIG_HD64461_IOBASE + 0x202e)
+/* Port Control Registers */
+#define HD64461_GPACR           (CONFIG_HD64461_IOBASE + 0x4000)        /* Port A - Handles IRDA/TIMER */
+#define HD64461_GPBCR           (CONFIG_HD64461_IOBASE + 0x4002)        /* Port B - Handles UART */
+#define HD64461_GPCCR           (CONFIG_HD64461_IOBASE + 0x4004)        /* Port C - Handles PCMCIA 1 */
+#define HD64461_GPDCR           (CONFIG_HD64461_IOBASE + 0x4006)        /* Port D - Handles PCMCIA 1 */
+/* Port Control Data Registers */
+#define HD64461_GPADR           (CONFIG_HD64461_IOBASE + 0x4010)        /* A */
+#define HD64461_GPBDR           (CONFIG_HD64461_IOBASE + 0x4012)        /* B */
+#define HD64461_GPCDR           (CONFIG_HD64461_IOBASE + 0x4014)        /* C */
+#define HD64461_GPDDR           (CONFIG_HD64461_IOBASE + 0x4016)        /* D */
+/* Interrupt Control Registers */
+#define HD64461_GPAICR          (CONFIG_HD64461_IOBASE + 0x4020)        /* A */
+#define HD64461_GPBICR          (CONFIG_HD64461_IOBASE + 0x4022)        /* B */
+#define HD64461_GPCICR          (CONFIG_HD64461_IOBASE + 0x4024)        /* C */
+#define HD64461_GPDICR          (CONFIG_HD64461_IOBASE + 0x4026)        /* D */
+/* Interrupt Status Registers */
+#define HD64461_GPAISR          (CONFIG_HD64461_IOBASE + 0x4040)        /* A */
+#define HD64461_GPBISR          (CONFIG_HD64461_IOBASE + 0x4042)        /* B */
+#define HD64461_GPCISR          (CONFIG_HD64461_IOBASE + 0x4044)        /* C */
+#define HD64461_GPDISR          (CONFIG_HD64461_IOBASE + 0x4046)        /* D */
+/* Interrupt Request Register & Interrupt Mask Register */
+#define HD64461_NIRR            (CONFIG_HD64461_IOBASE + 0x5000)
+#define HD64461_NIMR            (CONFIG_HD64461_IOBASE + 0x5002)
+#define HD64461_IRQBASE         OFFCHIP_IRQ_BASE
+#define OFFCHIP_IRQ_BASE        64
+#define HD64461_IRQ_NUM         16
+#define HD64461_IRQ_UART        (HD64461_IRQBASE+5)
+#define HD64461_IRQ_IRDA        (HD64461_IRQBASE+6)
+#define HD64461_IRQ_TMU1        (HD64461_IRQBASE+9)
+#define HD64461_IRQ_TMU0        (HD64461_IRQBASE+10)
+#define HD64461_IRQ_GPIO        (HD64461_IRQBASE+11)
+#define HD64461_IRQ_AFE         (HD64461_IRQBASE+12)
+#define HD64461_IRQ_PCC1        (HD64461_IRQBASE+13)
+#define HD64461_IRQ_PCC0        (HD64461_IRQBASE+14)
+#define __IO_PREFIX     hd64461
+#include <asm/io_generic.h>
+/* arch/sh/cchips/hd6446x/hd64461/setup.c */
+int hd64461_irq_demux(int irq);
+void hd64461_register_irq_demux(int irq,
+                                int (*demux) (int irq, void *dev), void *dev);
+void hd64461_unregister_irq_demux(int irq);
+#endif

diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h new file mode 100644 index 000000000000..8c1353baf00f --- /dev/null +++ b/arch/sh/include/asm/hd64461.h
@@ -0,0 +1,250 @@
	1	#ifndef __ASM_SH_HD64461
	2	#define __ASM_SH_HD64461
	3	/*
	4	* Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
	5	* Copyright (C) 2004 Paul Mundt
	6	* Copyright (C) 2000 YAEGASHI Takeshi
	7	*
	8	* Hitachi HD64461 companion chip support
	9	* (please note manual reference 0x10000000 = 0xb0000000)
	10	*/
	11
	12	/* Constants for PCMCIA mappings */
	13	#define HD64461_PCC_WINDOW 0x01000000
	14
	15	/* Area 6 - Slot 0 - memory and/or IO card */
	16	#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000)
	17	#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
	18	#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
	19	#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2HD64461_PCC_WINDOW) / 0xba0000000 */
	20
	21	/* Area 5 - Slot 1 - memory card only */
	22	#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000)
	23	#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
	24	#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
	25
	26	/* Standby Control Register for HD64461 */
	27	#define HD64461_STBCR CONFIG_HD64461_IOBASE
	28	#define HD64461_STBCR_CKIO_STBY 0x2000
	29	#define HD64461_STBCR_SAFECKE_IST 0x1000
	30	#define HD64461_STBCR_SLCKE_IST 0x0800
	31	#define HD64461_STBCR_SAFECKE_OST 0x0400
	32	#define HD64461_STBCR_SLCKE_OST 0x0200
	33	#define HD64461_STBCR_SMIAST 0x0100
	34	#define HD64461_STBCR_SLCDST 0x0080
	35	#define HD64461_STBCR_SPC0ST 0x0040
	36	#define HD64461_STBCR_SPC1ST 0x0020
	37	#define HD64461_STBCR_SAFEST 0x0010
	38	#define HD64461_STBCR_STM0ST 0x0008
	39	#define HD64461_STBCR_STM1ST 0x0004
	40	#define HD64461_STBCR_SIRST 0x0002
	41	#define HD64461_STBCR_SURTST 0x0001
	42
	43	/* System Configuration Register */
	44	#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02)
	45
	46	/* CPU Data Bus Control Register */
	47	#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
	48
	49	/* Base Address Register */
	50	#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
	51
	52	/* Line increment address */
	53	#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
	54
	55	/* Controls LCD controller */
	56	#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004)
	57
	58	/* LCCDR control bits */
	59	#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
	60	#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
	61	#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
	62	#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
	63	#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
	64	#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
	65
	66	/* Controls LCD (1) */
	67	#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010)
	68	#define HD64461_LDR1_DON 0x01 /* Display On */
	69	#define HD64461_LDR1_DINV 0x80 /* Display Invert */
	70
	71	/* Controls LCD (2) */
	72	#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012)
	73	#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */
	74	#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */
	75	#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */
	76	#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */
	77	#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */
	78
	79	/* Controls LCD (3) */
	80	#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
	81
	82	/* Palette Registers */
	83	#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */
	84	#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
	85	#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */
	86	#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
	87
	88	#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
	89	#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */
	90	#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */
	91
	92	#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
	93	#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
	94	#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
	95	#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
	96	#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
	97	#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
	98
	99	/* Line Drawing Registers */
	100	#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */
	101	#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */
	102	#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
	103	#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
	104	#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
	105	#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */
	106	#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
	107
	108	/* BitBLT Registers */
	109	#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */
	110	#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */
	111	#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */
	112	#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */
	113	#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
	114	#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
	115	#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */
	116	#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */
	117	#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */
	118	#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */
	119	#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
	120	#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
	121
	122	/* PC Card Controller Registers */
	123	/* Maps to Physical Area 6 */
	124	#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */
	125	#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */
	126	#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */
	127	#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */
	128	#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */
	129	/* Maps to Physical Area 5 */
	130	#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */
	131	#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */
	132	#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */
	133	#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */
	134	#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */
	135
	136	/* PCC Interface Status Register */
	137	#define HD64461_PCCISR_READY 0x80 /* card ready */
	138	#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
	139	#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
	140	#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
	141	#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
	142	#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
	143	#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
	144	#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
	145
	146	#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
	147	#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
	148	#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
	149	#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
	150	#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
	151	#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
	152
	153	/* PCC General Control Register */
	154	#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
	155	#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
	156	#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
	157	#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
	158	#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
	159	#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
	160	#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
	161	#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
	162
	163	/* PCC Card Status Change Register */
	164	#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
	165	#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
	166	#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
	167	#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
	168	#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
	169	#define HD64461_PCCCSCR_RC 0x04 /* READY change */
	170	#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
	171	#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
	172
	173	/* PCC Card Status Change Interrupt Enable Register */
	174	#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
	175	#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
	176	#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
	177	#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
	178	#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
	179	#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
	180
	181	#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
	182	#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
	183	#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
	184	#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
	185	#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
	186
	187	/* PCC Software Control Register */
	188	#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
	189	#define HD64461_PCCSCR_SWP 0x01 /* write protect */
	190
	191	/* PCC0 Output Pins Control Register */
	192	#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a)
	193
	194	/* PCC1 Output Pins Control Register */
	195	#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c)
	196
	197	/* PC Card General Control Register */
	198	#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e)
	199
	200	/* Port Control Registers */
	201	#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */
	202	#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */
	203	#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */
	204	#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */
	205
	206	/* Port Control Data Registers */
	207	#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */
	208	#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */
	209	#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */
	210	#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */
	211
	212	/* Interrupt Control Registers */
	213	#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */
	214	#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */
	215	#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */
	216	#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */
	217
	218	/* Interrupt Status Registers */
	219	#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */
	220	#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */
	221	#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */
	222	#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */
	223
	224	/* Interrupt Request Register & Interrupt Mask Register */
	225	#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000)
	226	#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002)
	227
	228	#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
	229	#define OFFCHIP_IRQ_BASE 64
	230	#define HD64461_IRQ_NUM 16
	231
	232	#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
	233	#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
	234	#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
	235	#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
	236	#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
	237	#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
	238	#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
	239	#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
	240
	241	#define __IO_PREFIX hd64461
	242	#include <asm/io_generic.h>
	243
	244	/* arch/sh/cchips/hd6446x/hd64461/setup.c */
	245	int hd64461_irq_demux(int irq);
	246	void hd64461_register_irq_demux(int irq,
	247	int (demux) (int irq, void dev), void *dev);
	248	void hd64461_unregister_irq_demux(int irq);
	249
	250	#endif