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-rw-r--r--arch/sh/drivers/dma/Makefile1
-rw-r--r--arch/sh/drivers/dma/dma-isa.c106
-rw-r--r--arch/sh/drivers/dma/dma-sh.c3
-rw-r--r--arch/sh/drivers/dma/dma-sh.h1
-rw-r--r--arch/sh/drivers/pci/ops-sh03.c3
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c12
6 files changed, 10 insertions, 116 deletions
diff --git a/arch/sh/drivers/dma/Makefile b/arch/sh/drivers/dma/Makefile
index 1ac812d24488..ab956adacb47 100644
--- a/arch/sh/drivers/dma/Makefile
+++ b/arch/sh/drivers/dma/Makefile
@@ -3,7 +3,6 @@
3# 3#
4 4
5obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o 5obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o
6obj-$(CONFIG_ISA_DMA_API) += dma-isa.o
7obj-$(CONFIG_SH_DMA) += dma-sh.o 6obj-$(CONFIG_SH_DMA) += dma-sh.o
8obj-$(CONFIG_SH_DREAMCAST) += dma-pvr2.o dma-g2.o 7obj-$(CONFIG_SH_DREAMCAST) += dma-pvr2.o dma-g2.o
9obj-$(CONFIG_SH_DMABRG) += dmabrg.o 8obj-$(CONFIG_SH_DMABRG) += dmabrg.o
diff --git a/arch/sh/drivers/dma/dma-isa.c b/arch/sh/drivers/dma/dma-isa.c
deleted file mode 100644
index 5fb044b791c3..000000000000
--- a/arch/sh/drivers/dma/dma-isa.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/sh/drivers/dma/dma-isa.c
3 *
4 * Generic ISA DMA wrapper for SH DMA API
5 *
6 * Copyright (C) 2003, 2004 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <asm/dma.h>
15
16/*
17 * This implements a small wrapper set to make code using the old ISA DMA API
18 * work with the SH DMA API. Since most of the work in the new API happens
19 * at ops->xfer() time, we simply use the various set_dma_xxx() routines to
20 * fill in per-channel info, and then hand hand this off to ops->xfer() at
21 * enable_dma() time.
22 *
23 * For channels that are doing on-demand data transfer via cascading, the
24 * channel itself will still need to be configured through the new API. As
25 * such, this code is meant for only the simplest of tasks (and shouldn't be
26 * used in any new drivers at all).
27 *
28 * NOTE: ops->xfer() is the preferred way of doing things. However, there
29 * are some users of the ISA DMA API that exist in common code that we
30 * don't necessarily want to go out of our way to break, so we still
31 * allow for some compatibility at that level. Any new code is strongly
32 * advised to run far away from the ISA DMA API and use the SH DMA API
33 * directly.
34 */
35unsigned long claim_dma_lock(void)
36{
37 unsigned long flags;
38
39 spin_lock_irqsave(&dma_spin_lock, flags);
40
41 return flags;
42}
43EXPORT_SYMBOL(claim_dma_lock);
44
45void release_dma_lock(unsigned long flags)
46{
47 spin_unlock_irqrestore(&dma_spin_lock, flags);
48}
49EXPORT_SYMBOL(release_dma_lock);
50
51void disable_dma(unsigned int chan)
52{
53 /* Nothing */
54}
55EXPORT_SYMBOL(disable_dma);
56
57void enable_dma(unsigned int chan)
58{
59 struct dma_info *info = get_dma_info(chan);
60 struct dma_channel *channel = &info->channels[chan];
61
62 info->ops->xfer(channel);
63}
64EXPORT_SYMBOL(enable_dma);
65
66void clear_dma_ff(unsigned int chan)
67{
68 /* Nothing */
69}
70EXPORT_SYMBOL(clear_dma_ff);
71
72void set_dma_mode(unsigned int chan, char mode)
73{
74 struct dma_info *info = get_dma_info(chan);
75 struct dma_channel *channel = &info->channels[chan];
76
77 channel->mode = mode;
78}
79EXPORT_SYMBOL(set_dma_mode);
80
81void set_dma_addr(unsigned int chan, unsigned int addr)
82{
83 struct dma_info *info = get_dma_info(chan);
84 struct dma_channel *channel = &info->channels[chan];
85
86 /*
87 * Single address mode is the only thing supported through
88 * this interface.
89 */
90 if ((channel->mode & DMA_MODE_MASK) == DMA_MODE_READ) {
91 channel->sar = addr;
92 } else {
93 channel->dar = addr;
94 }
95}
96EXPORT_SYMBOL(set_dma_addr);
97
98void set_dma_count(unsigned int chan, unsigned int count)
99{
100 struct dma_info *info = get_dma_info(chan);
101 struct dma_channel *channel = &info->channels[chan];
102
103 channel->count = count;
104}
105EXPORT_SYMBOL(set_dma_count);
106
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index b2ffe649c7c0..50887a592dd0 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -205,7 +205,8 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
205 205
206#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 206#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
207 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 207 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
208 defined(CONFIG_CPU_SUBTYPE_SH7780) 208 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
209 defined(CONFIG_CPU_SUBTYPE_SH7709)
209#define dmaor_read_reg() ctrl_inw(DMAOR) 210#define dmaor_read_reg() ctrl_inw(DMAOR)
210#define dmaor_write_reg(data) ctrl_outw(data, DMAOR) 211#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
211#else 212#else
diff --git a/arch/sh/drivers/dma/dma-sh.h b/arch/sh/drivers/dma/dma-sh.h
index b05af34fc15d..05fecd5428e4 100644
--- a/arch/sh/drivers/dma/dma-sh.h
+++ b/arch/sh/drivers/dma/dma-sh.h
@@ -29,6 +29,7 @@
29#define RS_IN 0x00000200 29#define RS_IN 0x00000200
30#define RS_OUT 0x00000300 30#define RS_OUT 0x00000300
31#define TS_BLK 0x00000040 31#define TS_BLK 0x00000040
32#define TM_BUR 0x00000020
32#define CHCR_DE 0x00000001 33#define CHCR_DE 0x00000001
33#define CHCR_TE 0x00000002 34#define CHCR_TE 0x00000002
34#define CHCR_IE 0x00000004 35#define CHCR_IE 0x00000004
diff --git a/arch/sh/drivers/pci/ops-sh03.c b/arch/sh/drivers/pci/ops-sh03.c
index ebb58e605d9d..e1703ff5a4d2 100644
--- a/arch/sh/drivers/pci/ops-sh03.c
+++ b/arch/sh/drivers/pci/ops-sh03.c
@@ -18,7 +18,8 @@
18 */ 18 */
19int __init pcibios_init_platform(void) 19int __init pcibios_init_platform(void)
20{ 20{
21 return 1; 21 __set_io_port_base(SH7751_PCI_IO_BASE);
22 return 1;
22} 23}
23 24
24static struct resource sh7751_io_resource = { 25static struct resource sh7751_io_resource = {
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index b2a2bfa3c1bd..078dc44d6b08 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -123,16 +123,14 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
123 * Window0 = map->window0.size @ non-cached area base = SDRAM 123 * Window0 = map->window0.size @ non-cached area base = SDRAM
124 * Window1 = map->window1.size @ cached area base = SDRAM 124 * Window1 = map->window1.size @ cached area base = SDRAM
125 */ 125 */
126 word = ((map->window0.size - 1) & 0x1ff00001) | 0x01; 126 word = (CONFIG_MEMORY_SIZE - 0x00100000) | 0x00000001;
127 pci_write_reg(0x07f00001, SH4_PCILSR0); 127 pci_write_reg(word, SH4_PCILSR0);
128 word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
129 pci_write_reg(0x00000001, SH4_PCILSR1); 128 pci_write_reg(0x00000001, SH4_PCILSR1);
130 /* Set the values on window 0 PCI config registers */ 129 /* Set the values on window 0 PCI config registers */
131 word = P2SEGADDR(map->window0.base); 130 word = (CONFIG_MEMORY_SIZE > 0x08000000) ? 0x10000000 : 0x08000000;
132 pci_write_reg(0xa8000000, SH4_PCILAR0); 131 pci_write_reg(word | 0xa0000000, SH4_PCILAR0);
133 pci_write_reg(0x08000000, SH7780_PCIMBAR0); 132 pci_write_reg(word, SH7780_PCIMBAR0);
134 /* Set the values on window 1 PCI config registers */ 133 /* Set the values on window 1 PCI config registers */
135 word = P2SEGADDR(map->window1.base);
136 pci_write_reg(0x00000000, SH4_PCILAR1); 134 pci_write_reg(0x00000000, SH4_PCILAR1);
137 pci_write_reg(0x00000000, SH7780_PCIMBAR1); 135 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
138 136