aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/drivers/pci
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/drivers/pci')
-rw-r--r--arch/sh/drivers/pci/Makefile5
-rw-r--r--arch/sh/drivers/pci/common.c162
-rw-r--r--arch/sh/drivers/pci/fixups-dreamcast.c2
-rw-r--r--arch/sh/drivers/pci/fixups-r7780rp.c12
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c4
-rw-r--r--arch/sh/drivers/pci/fixups-sdk7780.c19
-rw-r--r--arch/sh/drivers/pci/fixups-se7751.c6
-rw-r--r--arch/sh/drivers/pci/ops-sh4.c30
-rw-r--r--arch/sh/drivers/pci/pci-dreamcast.c32
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h18
-rw-r--r--arch/sh/drivers/pci/pci-sh5.c19
-rw-r--r--arch/sh/drivers/pci/pci-sh5.h12
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c52
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c408
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h64
-rw-r--r--arch/sh/drivers/pci/pci.c167
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c205
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.h74
18 files changed, 857 insertions, 434 deletions
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 08af1f459756..4a59e6890876 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -1,14 +1,14 @@
1# 1#
2# Makefile for the PCI specific kernel interface routines under Linux. 2# Makefile for the PCI specific kernel interface routines under Linux.
3# 3#
4obj-y += pci.o 4obj-y += common.o pci.o
5 5
6obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o 6obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += ops-sh7786.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o
12obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o 12obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
13 13
14obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ 14obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
@@ -25,4 +25,3 @@ obj-$(CONFIG_SH_TITAN) += fixups-titan.o
25obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o 25obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o
26obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o 26obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o
27obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o 27obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o
28obj-$(CONFIG_SH_URQUELL) += pcie-sh7786.o
diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c
new file mode 100644
index 000000000000..dbf138199871
--- /dev/null
+++ b/arch/sh/drivers/pci/common.c
@@ -0,0 +1,162 @@
1#include <linux/pci.h>
2#include <linux/interrupt.h>
3#include <linux/timer.h>
4#include <linux/kernel.h>
5
6/*
7 * These functions are used early on before PCI scanning is done
8 * and all of the pci_dev and pci_bus structures have been created.
9 */
10static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
11 int top_bus, int busnr, int devfn)
12{
13 static struct pci_dev dev;
14 static struct pci_bus bus;
15
16 dev.bus = &bus;
17 dev.sysdata = hose;
18 dev.devfn = devfn;
19 bus.number = busnr;
20 bus.sysdata = hose;
21 bus.ops = hose->pci_ops;
22
23 if(busnr != top_bus)
24 /* Fake a parent bus structure. */
25 bus.parent = &bus;
26 else
27 bus.parent = NULL;
28
29 return &dev;
30}
31
32#define EARLY_PCI_OP(rw, size, type) \
33int __init early_##rw##_config_##size(struct pci_channel *hose, \
34 int top_bus, int bus, int devfn, int offset, type value) \
35{ \
36 return pci_##rw##_config_##size( \
37 fake_pci_dev(hose, top_bus, bus, devfn), \
38 offset, value); \
39}
40
41EARLY_PCI_OP(read, byte, u8 *)
42EARLY_PCI_OP(read, word, u16 *)
43EARLY_PCI_OP(read, dword, u32 *)
44EARLY_PCI_OP(write, byte, u8)
45EARLY_PCI_OP(write, word, u16)
46EARLY_PCI_OP(write, dword, u32)
47
48int __init pci_is_66mhz_capable(struct pci_channel *hose,
49 int top_bus, int current_bus)
50{
51 u32 pci_devfn;
52 unsigned short vid;
53 int cap66 = -1;
54 u16 stat;
55
56 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
57
58 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
59 if (PCI_FUNC(pci_devfn))
60 continue;
61 if (early_read_config_word(hose, top_bus, current_bus,
62 pci_devfn, PCI_VENDOR_ID, &vid) !=
63 PCIBIOS_SUCCESSFUL)
64 continue;
65 if (vid == 0xffff)
66 continue;
67
68 /* check 66MHz capability */
69 if (cap66 < 0)
70 cap66 = 1;
71 if (cap66) {
72 early_read_config_word(hose, top_bus, current_bus,
73 pci_devfn, PCI_STATUS, &stat);
74 if (!(stat & PCI_STATUS_66MHZ)) {
75 printk(KERN_DEBUG
76 "PCI: %02x:%02x not 66MHz capable.\n",
77 current_bus, pci_devfn);
78 cap66 = 0;
79 break;
80 }
81 }
82 }
83
84 return cap66 > 0;
85}
86
87static void pcibios_enable_err(unsigned long __data)
88{
89 struct pci_channel *hose = (struct pci_channel *)__data;
90
91 del_timer(&hose->err_timer);
92 printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
93 enable_irq(hose->err_irq);
94}
95
96static void pcibios_enable_serr(unsigned long __data)
97{
98 struct pci_channel *hose = (struct pci_channel *)__data;
99
100 del_timer(&hose->serr_timer);
101 printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
102 enable_irq(hose->serr_irq);
103}
104
105void pcibios_enable_timers(struct pci_channel *hose)
106{
107 if (hose->err_irq) {
108 init_timer(&hose->err_timer);
109 hose->err_timer.data = (unsigned long)hose;
110 hose->err_timer.function = pcibios_enable_err;
111 }
112
113 if (hose->serr_irq) {
114 init_timer(&hose->serr_timer);
115 hose->serr_timer.data = (unsigned long)hose;
116 hose->serr_timer.function = pcibios_enable_serr;
117 }
118}
119
120/*
121 * A simple handler for the regular PCI status errors, called from IRQ
122 * context.
123 */
124unsigned int pcibios_handle_status_errors(unsigned long addr,
125 unsigned int status,
126 struct pci_channel *hose)
127{
128 unsigned int cmd = 0;
129
130 if (status & PCI_STATUS_REC_MASTER_ABORT) {
131 printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
132 cmd |= PCI_STATUS_REC_MASTER_ABORT;
133 }
134
135 if (status & PCI_STATUS_REC_TARGET_ABORT) {
136 printk(KERN_DEBUG "PCI: target abort: ");
137 pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
138 PCI_STATUS_SIG_TARGET_ABORT |
139 PCI_STATUS_REC_MASTER_ABORT, 1);
140 printk("\n");
141
142 cmd |= PCI_STATUS_REC_TARGET_ABORT;
143 }
144
145 if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
146 printk(KERN_DEBUG "PCI: parity error detected: ");
147 pcibios_report_status(PCI_STATUS_PARITY |
148 PCI_STATUS_DETECTED_PARITY, 1);
149 printk("\n");
150
151 cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
152
153 /* Now back off of the IRQ for awhile */
154 if (hose->err_irq) {
155 disable_irq_nosync(hose->err_irq);
156 hose->err_timer.expires = jiffies + HZ;
157 add_timer(&hose->err_timer);
158 }
159 }
160
161 return cmd;
162}
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index ed7f489936f1..942ef4f155f5 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -39,7 +39,7 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
39 /* 39 /*
40 * We also assume that dev->devfn == 0 40 * We also assume that dev->devfn == 0
41 */ 41 */
42 dev->resource[1].start = p->io_resource->start + 0x100; 42 dev->resource[1].start = p->resources[0].start + 0x100;
43 dev->resource[1].end = dev->resource[1].start + 0x200 - 1; 43 dev->resource[1].end = dev->resource[1].start + 0x200 - 1;
44 44
45 /* 45 /*
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
index 15ca65cb667e..08b2d8658a00 100644
--- a/arch/sh/drivers/pci/fixups-r7780rp.c
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -22,15 +22,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
22{ 22{
23 return irq_tab[slot]; 23 return irq_tab[slot];
24} 24}
25
26int pci_fixup_pcic(struct pci_channel *chan)
27{
28 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
29 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
30 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
31 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
32 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
33 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
34
35 return 0;
36}
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 7898f14d6641..e248516118a9 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -43,7 +43,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
43{ 43{
44 unsigned long bcr1, mcr; 44 unsigned long bcr1, mcr;
45 45
46 bcr1 = ctrl_inl(SH7751_BCR1); 46 bcr1 = __raw_readl(SH7751_BCR1);
47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
48 pci_write_reg(chan, bcr1, SH4_PCIBCR1); 48 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
49 49
@@ -54,7 +54,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); 54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); 55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
56 56
57 mcr = ctrl_inl(SH7751_MCR); 57 mcr = __raw_readl(SH7751_MCR);
58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
59 pci_write_reg(chan, mcr, SH4_PCIMCR); 59 pci_write_reg(chan, mcr, SH4_PCIMCR);
60 60
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
index 250b0edd7365..0930f988ac29 100644
--- a/arch/sh/drivers/pci/fixups-sdk7780.c
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -31,22 +31,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
31{ 31{
32 return sdk7780_irq_tab[pin-1][slot]; 32 return sdk7780_irq_tab[pin-1][slot];
33} 33}
34int pci_fixup_pcic(struct pci_channel *chan)
35{
36 /* Enable all interrupts, so we know what to fix */
37 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
38
39 /* Set up standard PCI config registers */
40 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
41 pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
42 pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
43
44 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
45 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
46 pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
47
48 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
49 pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
50
51 return 0;
52}
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
index 475fa9f0fe2c..a4c7d3a4efca 100644
--- a/arch/sh/drivers/pci/fixups-se7751.c
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -97,12 +97,12 @@ int pci_fixup_pcic(struct pci_channel *chan)
97 * meaning all calls go straight through... use BUG_ON to 97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption. 98 * catch erroneous assumption.
99 */ 99 */
100 BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE); 100 BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
101 101
102 PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start); 102 PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
103 103
104 /* Set IOBR for window containing area specified in pci.h */ 104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK)); 105 PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
106 106
107 /* All done, may as well say so... */ 107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n"); 108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 78bebebdc99c..0b81999fb88b 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -16,7 +16,7 @@
16 * Direct access to PCI hardware... 16 * Direct access to PCI hardware...
17 */ 17 */
18#define CONFIG_CMD(bus, devfn, where) \ 18#define CONFIG_CMD(bus, devfn, where) \
19 (P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3)) 19 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
20 20
21static DEFINE_SPINLOCK(sh4_pci_lock); 21static DEFINE_SPINLOCK(sh4_pci_lock);
22 22
@@ -102,34 +102,6 @@ struct pci_ops sh4_pci_ops = {
102 .write = sh4_pci_write, 102 .write = sh4_pci_write,
103}; 103};
104 104
105/*
106 * Not really related to pci_ops, but it's common and not worth shoving
107 * somewhere else for now..
108 */
109int __init sh4_pci_check_direct(struct pci_channel *chan)
110{
111 /*
112 * Check if configuration works.
113 */
114 unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR);
115
116 pci_write_reg(chan, P1SEG, SH4_PCIPAR);
117
118 if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) {
119 pci_write_reg(chan, tmp, SH4_PCIPAR);
120 printk(KERN_INFO "PCI: Using configuration type 1\n");
121 request_region(chan->reg_base + SH4_PCIPAR, 8,
122 "PCI conf1");
123 return 0;
124 }
125
126 pci_write_reg(chan, tmp, SH4_PCIPAR);
127
128 printk(KERN_ERR "PCI: %s failed\n", __func__);
129
130 return -EINVAL;
131}
132
133int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan) 105int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
134{ 106{
135 /* Nothing to do. */ 107 /* Nothing to do. */
diff --git a/arch/sh/drivers/pci/pci-dreamcast.c b/arch/sh/drivers/pci/pci-dreamcast.c
index 210f9d4af141..633694193af8 100644
--- a/arch/sh/drivers/pci/pci-dreamcast.c
+++ b/arch/sh/drivers/pci/pci-dreamcast.c
@@ -25,25 +25,25 @@
25#include <asm/irq.h> 25#include <asm/irq.h>
26#include <mach/pci.h> 26#include <mach/pci.h>
27 27
28static struct resource gapspci_io_resource = { 28static struct resource gapspci_resources[] = {
29 .name = "GAPSPCI IO", 29 {
30 .start = GAPSPCI_BBA_CONFIG, 30 .name = "GAPSPCI IO",
31 .end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1, 31 .start = GAPSPCI_BBA_CONFIG,
32 .flags = IORESOURCE_IO, 32 .end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
33}; 33 .flags = IORESOURCE_IO,
34 34 }, {
35static struct resource gapspci_mem_resource = { 35 .name = "GAPSPCI mem",
36 .name = "GAPSPCI mem", 36 .start = GAPSPCI_DMA_BASE,
37 .start = GAPSPCI_DMA_BASE, 37 .end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
38 .end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1, 38 .flags = IORESOURCE_MEM,
39 .flags = IORESOURCE_MEM, 39 },
40}; 40};
41 41
42static struct pci_channel dreamcast_pci_controller = { 42static struct pci_channel dreamcast_pci_controller = {
43 .pci_ops = &gapspci_pci_ops, 43 .pci_ops = &gapspci_pci_ops,
44 .io_resource = &gapspci_io_resource, 44 .resources = gapspci_resources,
45 .nr_resources = ARRAY_SIZE(gapspci_resources),
45 .io_offset = 0x00000000, 46 .io_offset = 0x00000000,
46 .mem_resource = &gapspci_mem_resource,
47 .mem_offset = 0x00000000, 47 .mem_offset = 0x00000000,
48}; 48};
49 49
@@ -95,8 +95,6 @@ static int __init gapspci_init(void)
95 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10); 95 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
96 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14); 96 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
97 97
98 register_pci_controller(&dreamcast_pci_controller); 98 return register_pci_controller(&dreamcast_pci_controller);
99
100 return 0;
101} 99}
102arch_initcall(gapspci_init); 100arch_initcall(gapspci_init);
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 3d5296cde622..cbf763b3015e 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -49,6 +49,17 @@
49 #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */ 49 #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
50 #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */ 50 #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
51#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */ 51#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
52 #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
53 #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
54 #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
55 #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
56 #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
57 #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
58 #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
59 #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
60 #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
61 #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
62 #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
52#define SH4_PCIALR 0x11C /* Error Address Register */ 63#define SH4_PCIALR 0x11C /* Error Address Register */
53#define SH4_PCICLR 0x120 /* Error Command/Data */ 64#define SH4_PCICLR 0x120 /* Error Command/Data */
54 #define SH4_PCICLR_MPIO 0x80000000 65 #define SH4_PCICLR_MPIO 0x80000000
@@ -61,7 +72,7 @@
61#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */ 72#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
62 #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */ 73 #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
63 #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */ 74 #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
64 #define SH4_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */ 75 #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
65 #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */ 76 #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
66 #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */ 77 #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
67 #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */ 78 #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
@@ -151,7 +162,6 @@
151 162
152/* arch/sh/kernel/drivers/pci/ops-sh4.c */ 163/* arch/sh/kernel/drivers/pci/ops-sh4.c */
153extern struct pci_ops sh4_pci_ops; 164extern struct pci_ops sh4_pci_ops;
154int sh4_pci_check_direct(struct pci_channel *chan);
155int pci_fixup_pcic(struct pci_channel *chan); 165int pci_fixup_pcic(struct pci_channel *chan);
156 166
157struct sh4_pci_address_space { 167struct sh4_pci_address_space {
@@ -167,13 +177,13 @@ struct sh4_pci_address_map {
167static inline void pci_write_reg(struct pci_channel *chan, 177static inline void pci_write_reg(struct pci_channel *chan,
168 unsigned long val, unsigned long reg) 178 unsigned long val, unsigned long reg)
169{ 179{
170 ctrl_outl(val, chan->reg_base + reg); 180 __raw_writel(val, chan->reg_base + reg);
171} 181}
172 182
173static inline unsigned long pci_read_reg(struct pci_channel *chan, 183static inline unsigned long pci_read_reg(struct pci_channel *chan,
174 unsigned long reg) 184 unsigned long reg)
175{ 185{
176 return ctrl_inl(chan->reg_base + reg); 186 return __raw_readl(chan->reg_base + reg);
177} 187}
178 188
179#endif /* __PCI_SH4_H */ 189#endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index 873ed2b44055..0bf296c78795 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -89,14 +89,13 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
89 return IRQ_NONE; 89 return IRQ_NONE;
90} 90}
91 91
92static struct resource sh5_io_resource = { /* place holder */ }; 92static struct resource sh5_pci_resources[2];
93static struct resource sh5_mem_resource = { /* place holder */ };
94 93
95static struct pci_channel sh5pci_controller = { 94static struct pci_channel sh5pci_controller = {
96 .pci_ops = &sh5_pci_ops, 95 .pci_ops = &sh5_pci_ops,
97 .mem_resource = &sh5_mem_resource, 96 .resources = sh5_pci_resources,
97 .nr_resources = ARRAY_SIZE(sh5_pci_resources),
98 .mem_offset = 0x00000000, 98 .mem_offset = 0x00000000,
99 .io_resource = &sh5_io_resource,
100 .io_offset = 0x00000000, 99 .io_offset = 0x00000000,
101}; 100};
102 101
@@ -210,14 +209,12 @@ static int __init sh5pci_init(void)
210 SH5PCI_WRITE(AINTM, ~0); 209 SH5PCI_WRITE(AINTM, ~0);
211 SH5PCI_WRITE(PINTM, ~0); 210 SH5PCI_WRITE(PINTM, ~0);
212 211
213 sh5_io_resource.start = PCI_IO_AREA; 212 sh5_pci_resources[0].start = PCI_IO_AREA;
214 sh5_io_resource.end = PCI_IO_AREA + 0x10000; 213 sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000;
215 214
216 sh5_mem_resource.start = memStart; 215 sh5_pci_resources[1].start = memStart;
217 sh5_mem_resource.end = memStart + memSize; 216 sh5_pci_resources[1].end = memStart + memSize;
218 217
219 register_pci_controller(&sh5pci_controller); 218 return register_pci_controller(&sh5pci_controller);
220
221 return 0;
222} 219}
223arch_initcall(sh5pci_init); 220arch_initcall(sh5pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index f277628221f3..3f01decb4307 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -86,14 +86,14 @@ extern unsigned long pcicr_virt;
86/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */ 86/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
87 87
88/* Write I/O functions */ 88/* Write I/O functions */
89#define SH5PCI_WRITE(reg,val) ctrl_outl((u32)(val),PCISH5_ICR_REG(reg)) 89#define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
90#define SH5PCI_WRITE_SHORT(reg,val) ctrl_outw((u16)(val),PCISH5_ICR_REG(reg)) 90#define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
91#define SH5PCI_WRITE_BYTE(reg,val) ctrl_outb((u8)(val),PCISH5_ICR_REG(reg)) 91#define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
92 92
93/* Read I/O functions */ 93/* Read I/O functions */
94#define SH5PCI_READ(reg) ctrl_inl(PCISH5_ICR_REG(reg)) 94#define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg))
95#define SH5PCI_READ_SHORT(reg) ctrl_inw(PCISH5_ICR_REG(reg)) 95#define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg))
96#define SH5PCI_READ_BYTE(reg) ctrl_inb(PCISH5_ICR_REG(reg)) 96#define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg))
97 97
98/* Set PCI config bits */ 98/* Set PCI config bits */
99#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000) 99#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 70c1999a0ec4..17811e5d287b 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -44,25 +44,25 @@ static int __init __area_sdram_check(struct pci_channel *chan,
44 return 1; 44 return 1;
45} 45}
46 46
47static struct resource sh7751_io_resource = { 47static struct resource sh7751_pci_resources[] = {
48 .name = "SH7751_IO", 48 {
49 .start = SH7751_PCI_IO_BASE, 49 .name = "SH7751_IO",
50 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, 50 .start = SH7751_PCI_IO_BASE,
51 .flags = IORESOURCE_IO 51 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
52}; 52 .flags = IORESOURCE_IO
53 53 }, {
54static struct resource sh7751_mem_resource = { 54 .name = "SH7751_mem",
55 .name = "SH7751_mem", 55 .start = SH7751_PCI_MEMORY_BASE,
56 .start = SH7751_PCI_MEMORY_BASE, 56 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
57 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, 57 .flags = IORESOURCE_MEM
58 .flags = IORESOURCE_MEM 58 },
59}; 59};
60 60
61static struct pci_channel sh7751_pci_controller = { 61static struct pci_channel sh7751_pci_controller = {
62 .pci_ops = &sh4_pci_ops, 62 .pci_ops = &sh4_pci_ops,
63 .mem_resource = &sh7751_mem_resource, 63 .resources = sh7751_pci_resources,
64 .nr_resources = ARRAY_SIZE(sh7751_pci_resources),
64 .mem_offset = 0x00000000, 65 .mem_offset = 0x00000000,
65 .io_resource = &sh7751_io_resource,
66 .io_offset = 0x00000000, 66 .io_offset = 0x00000000,
67 .io_map_base = SH7751_PCI_IO_BASE, 67 .io_map_base = SH7751_PCI_IO_BASE,
68}; 68};
@@ -79,7 +79,6 @@ static int __init sh7751_pci_init(void)
79 struct pci_channel *chan = &sh7751_pci_controller; 79 struct pci_channel *chan = &sh7751_pci_controller;
80 unsigned int id; 80 unsigned int id;
81 u32 word, reg; 81 u32 word, reg;
82 int ret;
83 82
84 printk(KERN_NOTICE "PCI: Starting intialization.\n"); 83 printk(KERN_NOTICE "PCI: Starting intialization.\n");
85 84
@@ -93,13 +92,10 @@ static int __init sh7751_pci_init(void)
93 return -ENODEV; 92 return -ENODEV;
94 } 93 }
95 94
96 if ((ret = sh4_pci_check_direct(chan)) != 0)
97 return ret;
98
99 /* Set the BCR's to enable PCI access */ 95 /* Set the BCR's to enable PCI access */
100 reg = ctrl_inl(SH7751_BCR1); 96 reg = __raw_readl(SH7751_BCR1);
101 reg |= 0x80000; 97 reg |= 0x80000;
102 ctrl_outl(reg, SH7751_BCR1); 98 __raw_writel(reg, SH7751_BCR1);
103 99
104 /* Turn the clocks back on (not done in reset)*/ 100 /* Turn the clocks back on (not done in reset)*/
105 pci_write_reg(chan, 0, SH4_PCICLKR); 101 pci_write_reg(chan, 0, SH4_PCICLKR);
@@ -132,13 +128,13 @@ static int __init sh7751_pci_init(void)
132 /* Set the local 16MB PCI memory space window to 128 /* Set the local 16MB PCI memory space window to
133 * the lowest PCI mapped address 129 * the lowest PCI mapped address
134 */ 130 */
135 word = chan->mem_resource->start & SH4_PCIMBR_MASK; 131 word = chan->resources[1].start & SH4_PCIMBR_MASK;
136 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 132 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
137 pci_write_reg(chan, word , SH4_PCIMBR); 133 pci_write_reg(chan, word , SH4_PCIMBR);
138 134
139 /* Make sure the MSB's of IO window are set to access PCI space 135 /* Make sure the MSB's of IO window are set to access PCI space
140 * correctly */ 136 * correctly */
141 word = chan->io_resource->start & SH4_PCIIOBR_MASK; 137 word = chan->resources[0].start & SH4_PCIIOBR_MASK;
142 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 138 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
143 pci_write_reg(chan, word, SH4_PCIIOBR); 139 pci_write_reg(chan, word, SH4_PCIIOBR);
144 140
@@ -159,13 +155,13 @@ static int __init sh7751_pci_init(void)
159 return -1; 155 return -1;
160 156
161 /* configure the wait control registers */ 157 /* configure the wait control registers */
162 word = ctrl_inl(SH7751_WCR1); 158 word = __raw_readl(SH7751_WCR1);
163 pci_write_reg(chan, word, SH4_PCIWCR1); 159 pci_write_reg(chan, word, SH4_PCIWCR1);
164 word = ctrl_inl(SH7751_WCR2); 160 word = __raw_readl(SH7751_WCR2);
165 pci_write_reg(chan, word, SH4_PCIWCR2); 161 pci_write_reg(chan, word, SH4_PCIWCR2);
166 word = ctrl_inl(SH7751_WCR3); 162 word = __raw_readl(SH7751_WCR3);
167 pci_write_reg(chan, word, SH4_PCIWCR3); 163 pci_write_reg(chan, word, SH4_PCIWCR3);
168 word = ctrl_inl(SH7751_MCR); 164 word = __raw_readl(SH7751_MCR);
169 pci_write_reg(chan, word, SH4_PCIMCR); 165 pci_write_reg(chan, word, SH4_PCIMCR);
170 166
171 /* NOTE: I'm ignoring the PCI error IRQs for now.. 167 /* NOTE: I'm ignoring the PCI error IRQs for now..
@@ -180,8 +176,6 @@ static int __init sh7751_pci_init(void)
180 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 176 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
181 pci_write_reg(chan, word, SH4_PCICR); 177 pci_write_reg(chan, word, SH4_PCICR);
182 178
183 register_pci_controller(chan); 179 return register_pci_controller(chan);
184
185 return 0;
186} 180}
187arch_initcall(sh7751_pci_init); 181arch_initcall(sh7751_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 323b92d565fe..ffdcbf10b95e 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Low-Level PCI Support for the SH7780 2 * Low-Level PCI Support for the SH7780
3 * 3 *
4 * Copyright (C) 2005 - 2009 Paul Mundt 4 * Copyright (C) 2005 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -11,52 +11,240 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/pci.h> 13#include <linux/pci.h>
14#include <linux/interrupt.h>
15#include <linux/timer.h>
16#include <linux/irq.h>
14#include <linux/errno.h> 17#include <linux/errno.h>
15#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/log2.h>
16#include "pci-sh4.h" 20#include "pci-sh4.h"
21#include <asm/mmu.h>
22#include <asm/sizes.h>
17 23
18static struct resource sh7785_io_resource = { 24static struct resource sh7785_pci_resources[] = {
19 .name = "SH7785_IO", 25 {
20 .start = SH7780_PCI_IO_BASE, 26 .name = "PCI IO",
21 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1, 27 .start = 0x1000,
22 .flags = IORESOURCE_IO 28 .end = SZ_4M - 1,
23}; 29 .flags = IORESOURCE_IO,
24 30 }, {
25static struct resource sh7785_mem_resource = { 31 .name = "PCI MEM 0",
26 .name = "SH7785_mem", 32 .start = 0xfd000000,
27 .start = SH7780_PCI_MEMORY_BASE, 33 .end = 0xfd000000 + SZ_16M - 1,
28 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1, 34 .flags = IORESOURCE_MEM,
29 .flags = IORESOURCE_MEM 35 }, {
36 .name = "PCI MEM 1",
37 .start = 0x10000000,
38 .end = 0x10000000 + SZ_64M - 1,
39 .flags = IORESOURCE_MEM,
40 }, {
41 /*
42 * 32-bit only resources must be last.
43 */
44 .name = "PCI MEM 2",
45 .start = 0xc0000000,
46 .end = 0xc0000000 + SZ_512M - 1,
47 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
48 },
30}; 49};
31 50
32static struct pci_channel sh7780_pci_controller = { 51static struct pci_channel sh7780_pci_controller = {
33 .pci_ops = &sh4_pci_ops, 52 .pci_ops = &sh4_pci_ops,
34 .mem_resource = &sh7785_mem_resource, 53 .resources = sh7785_pci_resources,
35 .mem_offset = 0x00000000, 54 .nr_resources = ARRAY_SIZE(sh7785_pci_resources),
36 .io_resource = &sh7785_io_resource, 55 .io_offset = 0,
37 .io_offset = 0x00000000, 56 .mem_offset = 0,
38 .io_map_base = SH7780_PCI_IO_BASE, 57 .io_map_base = 0xfe200000,
58 .serr_irq = evt2irq(0xa00),
59 .err_irq = evt2irq(0xaa0),
39}; 60};
40 61
41static struct sh4_pci_address_map sh7780_pci_map = { 62struct pci_errors {
42 .window0 = { 63 unsigned int mask;
43#if defined(CONFIG_32BIT) 64 const char *str;
44 .base = SH7780_32BIT_DDR_BASE_ADDR, 65} pci_arbiter_errors[] = {
45 .size = 0x40000000, 66 { SH4_PCIAINT_MBKN, "master broken" },
46#else 67 { SH4_PCIAINT_TBTO, "target bus time out" },
47 .base = SH7780_CS0_BASE_ADDR, 68 { SH4_PCIAINT_MBTO, "master bus time out" },
48 .size = 0x20000000, 69 { SH4_PCIAINT_TABT, "target abort" },
49#endif 70 { SH4_PCIAINT_MABT, "master abort" },
50 }, 71 { SH4_PCIAINT_RDPE, "read data parity error" },
72 { SH4_PCIAINT_WDPE, "write data parity error" },
73}, pci_interrupt_errors[] = {
74 { SH4_PCIINT_MLCK, "master lock error" },
75 { SH4_PCIINT_TABT, "target-target abort" },
76 { SH4_PCIINT_TRET, "target retry time out" },
77 { SH4_PCIINT_MFDE, "master function disable erorr" },
78 { SH4_PCIINT_PRTY, "address parity error" },
79 { SH4_PCIINT_SERR, "SERR" },
80 { SH4_PCIINT_TWDP, "data parity error for target write" },
81 { SH4_PCIINT_TRDP, "PERR detected for target read" },
82 { SH4_PCIINT_MTABT, "target abort for master" },
83 { SH4_PCIINT_MMABT, "master abort for master" },
84 { SH4_PCIINT_MWPD, "master write data parity error" },
85 { SH4_PCIINT_MRPD, "master read data parity error" },
51}; 86};
52 87
88static irqreturn_t sh7780_pci_err_irq(int irq, void *dev_id)
89{
90 struct pci_channel *hose = dev_id;
91 unsigned long addr;
92 unsigned int status;
93 unsigned int cmd;
94 int i;
95
96 addr = __raw_readl(hose->reg_base + SH4_PCIALR);
97
98 /*
99 * Handle status errors.
100 */
101 status = __raw_readw(hose->reg_base + PCI_STATUS);
102 if (status & (PCI_STATUS_PARITY |
103 PCI_STATUS_DETECTED_PARITY |
104 PCI_STATUS_SIG_TARGET_ABORT |
105 PCI_STATUS_REC_TARGET_ABORT |
106 PCI_STATUS_REC_MASTER_ABORT)) {
107 cmd = pcibios_handle_status_errors(addr, status, hose);
108 if (likely(cmd))
109 __raw_writew(cmd, hose->reg_base + PCI_STATUS);
110 }
111
112 /*
113 * Handle arbiter errors.
114 */
115 status = __raw_readl(hose->reg_base + SH4_PCIAINT);
116 for (i = cmd = 0; i < ARRAY_SIZE(pci_arbiter_errors); i++) {
117 if (status & pci_arbiter_errors[i].mask) {
118 printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
119 pci_arbiter_errors[i].str, addr);
120 cmd |= pci_arbiter_errors[i].mask;
121 }
122 }
123 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
124
125 /*
126 * Handle the remaining PCI errors.
127 */
128 status = __raw_readl(hose->reg_base + SH4_PCIINT);
129 for (i = cmd = 0; i < ARRAY_SIZE(pci_interrupt_errors); i++) {
130 if (status & pci_interrupt_errors[i].mask) {
131 printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
132 pci_interrupt_errors[i].str, addr);
133 cmd |= pci_interrupt_errors[i].mask;
134 }
135 }
136 __raw_writel(cmd, hose->reg_base + SH4_PCIINT);
137
138 return IRQ_HANDLED;
139}
140
141static irqreturn_t sh7780_pci_serr_irq(int irq, void *dev_id)
142{
143 struct pci_channel *hose = dev_id;
144
145 printk(KERN_DEBUG "PCI: system error received: ");
146 pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
147 printk("\n");
148
149 /* Deassert SERR */
150 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
151
152 /* Back off the IRQ for awhile */
153 disable_irq_nosync(irq);
154 hose->serr_timer.expires = jiffies + HZ;
155 add_timer(&hose->serr_timer);
156
157 return IRQ_HANDLED;
158}
159
160static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
161{
162 int ret;
163
164 /* Clear out PCI arbiter IRQs */
165 __raw_writel(0, hose->reg_base + SH4_PCIAINT);
166
167 /* Clear all error conditions */
168 __raw_writew(PCI_STATUS_DETECTED_PARITY | \
169 PCI_STATUS_SIG_SYSTEM_ERROR | \
170 PCI_STATUS_REC_MASTER_ABORT | \
171 PCI_STATUS_REC_TARGET_ABORT | \
172 PCI_STATUS_SIG_TARGET_ABORT | \
173 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
174
175 ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, IRQF_DISABLED,
176 "PCI SERR interrupt", hose);
177 if (unlikely(ret)) {
178 printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n");
179 return ret;
180 }
181
182 /*
183 * The PCI ERR IRQ needs to be IRQF_SHARED since all of the power
184 * down IRQ vectors are routed through the ERR IRQ vector. We
185 * only request_irq() once as there is only a single masking
186 * source for multiple events.
187 */
188 ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
189 "PCI ERR interrupt", hose);
190 if (unlikely(ret)) {
191 free_irq(hose->serr_irq, hose);
192 return ret;
193 }
194
195 /* Unmask all of the arbiter IRQs. */
196 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
197 SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
198 SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
199
200 /* Unmask all of the PCI IRQs */
201 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
202 SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
203 SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
204 SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
205 SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
206 SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
207
208 return ret;
209}
210
211static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
212{
213 free_irq(hose->err_irq, hose);
214 free_irq(hose->serr_irq, hose);
215}
216
217static void __init sh7780_pci66_init(struct pci_channel *hose)
218{
219 unsigned int tmp;
220
221 if (!pci_is_66mhz_capable(hose, 0, 0))
222 return;
223
224 /* Enable register access */
225 tmp = __raw_readl(hose->reg_base + SH4_PCICR);
226 tmp |= SH4_PCICR_PREFIX;
227 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
228
229 /* Enable 66MHz operation */
230 tmp = __raw_readw(hose->reg_base + PCI_STATUS);
231 tmp |= PCI_STATUS_66MHZ;
232 __raw_writew(tmp, hose->reg_base + PCI_STATUS);
233
234 /* Done */
235 tmp = __raw_readl(hose->reg_base + SH4_PCICR);
236 tmp |= SH4_PCICR_PREFIX | SH4_PCICR_CFIN;
237 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
238}
239
53static int __init sh7780_pci_init(void) 240static int __init sh7780_pci_init(void)
54{ 241{
55 struct pci_channel *chan = &sh7780_pci_controller; 242 struct pci_channel *chan = &sh7780_pci_controller;
243 phys_addr_t memphys;
244 size_t memsize;
56 unsigned int id; 245 unsigned int id;
57 const char *type = NULL; 246 const char *type;
58 int ret; 247 int ret, i;
59 u32 word;
60 248
61 printk(KERN_NOTICE "PCI: Starting intialization.\n"); 249 printk(KERN_NOTICE "PCI: Starting intialization.\n");
62 250
@@ -65,17 +253,28 @@ static int __init sh7780_pci_init(void)
65 /* Enable CPU access to the PCIC registers. */ 253 /* Enable CPU access to the PCIC registers. */
66 __raw_writel(PCIECR_ENBL, PCIECR); 254 __raw_writel(PCIECR_ENBL, PCIECR);
67 255
68 id = __raw_readw(chan->reg_base + SH7780_PCIVID); 256 /* Reset */
69 if (id != SH7780_VENDOR_ID) { 257 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST,
258 chan->reg_base + SH4_PCICR);
259
260 /*
261 * Wait for it to come back up. The spec says to allow for up to
262 * 1 second after toggling the reset pin, but in practice 100ms
263 * is more than enough.
264 */
265 mdelay(100);
266
267 id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);
268 if (id != PCI_VENDOR_ID_RENESAS) {
70 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id); 269 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
71 return -ENODEV; 270 return -ENODEV;
72 } 271 }
73 272
74 id = __raw_readw(chan->reg_base + SH7780_PCIDID); 273 id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);
75 type = (id == SH7763_DEVICE_ID) ? "SH7763" : 274 type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" :
76 (id == SH7780_DEVICE_ID) ? "SH7780" : 275 (id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" :
77 (id == SH7781_DEVICE_ID) ? "SH7781" : 276 (id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" :
78 (id == SH7785_DEVICE_ID) ? "SH7785" : 277 (id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" :
79 NULL; 278 NULL;
80 if (unlikely(!type)) { 279 if (unlikely(!type)) {
81 printk(KERN_ERR "PCI: Found an unsupported Renesas host " 280 printk(KERN_ERR "PCI: Found an unsupported Renesas host "
@@ -85,62 +284,119 @@ static int __init sh7780_pci_init(void)
85 284
86 printk(KERN_NOTICE "PCI: Found a Renesas %s host " 285 printk(KERN_NOTICE "PCI: Found a Renesas %s host "
87 "controller, revision %d.\n", type, 286 "controller, revision %d.\n", type,
88 __raw_readb(chan->reg_base + SH7780_PCIRID)); 287 __raw_readb(chan->reg_base + PCI_REVISION_ID));
89 288
90 if ((ret = sh4_pci_check_direct(chan)) != 0) 289 /*
290 * Now throw it in to register initialization mode and
291 * start the real work.
292 */
293 __raw_writel(SH4_PCICR_PREFIX, chan->reg_base + SH4_PCICR);
294
295 memphys = __pa(memory_start);
296 memsize = roundup_pow_of_two(memory_end - memory_start);
297
298 /*
299 * If there's more than 512MB of memory, we need to roll over to
300 * LAR1/LSR1.
301 */
302 if (memsize > SZ_512M) {
303 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);
304 __raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1,
305 chan->reg_base + SH4_PCILSR1);
306 memsize = SZ_512M;
307 } else {
308 /*
309 * Otherwise just zero it out and disable it.
310 */
311 __raw_writel(0, chan->reg_base + SH4_PCILAR1);
312 __raw_writel(0, chan->reg_base + SH4_PCILSR1);
313 }
314
315 /*
316 * LAR0/LSR0 covers up to the first 512MB, which is enough to
317 * cover all of lowmem on most platforms.
318 */
319 __raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
320 __raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
321 chan->reg_base + SH4_PCILSR0);
322
323 /*
324 * Hook up the ERR and SERR IRQs.
325 */
326 ret = sh7780_pci_setup_irqs(chan);
327 if (unlikely(ret))
91 return ret; 328 return ret;
92 329
93 /* 330 /*
94 * Set the class and sub-class codes. 331 * Disable the cache snoop controller for non-coherent DMA.
95 */ 332 */
96 __raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8, 333 __raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
97 chan->reg_base + SH7780_PCIBCC); 334 __raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
98 __raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff, 335 __raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
99 chan->reg_base + SH7780_PCISUB); 336 __raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
100 337
101 /* 338 /*
102 * Set IO and Mem windows to local address 339 * Setup the memory BARs
103 * Make PCI and local address the same for easy 1 to 1 mapping
104 */ 340 */
105 pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0); 341 for (i = 1; i < chan->nr_resources; i++) {
106 /* Set the values on window 0 PCI config registers */ 342 struct resource *res = chan->resources + i;
107 pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0); 343 resource_size_t size;
108 pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
109 344
110 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); 345 if (unlikely(res->flags & IORESOURCE_IO))
346 continue;
111 347
112 /* Set up standard PCI config registers */ 348 /*
113 __raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS); 349 * Make sure we're in the right physical addressing mode
114 __raw_writew(0x0047, chan->reg_base + SH7780_PCICMD); 350 * for dealing with the resource.
115 __raw_writew(0x1912, chan->reg_base + SH7780_PCISVID); 351 */
116 __raw_writew(0x0001, chan->reg_base + SH7780_PCISID); 352 if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) {
353 chan->nr_resources--;
354 continue;
355 }
117 356
118 __raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF); 357 size = resource_size(res);
358
359 /*
360 * The MBMR mask is calculated in units of 256kB, which
361 * keeps things pretty simple.
362 */
363 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
364 chan->reg_base + SH7780_PCIMBMR(i - 1));
365 __raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));
366 }
119 367
120 /* Apply any last-minute PCIC fixups */ 368 /*
121 pci_fixup_pcic(chan); 369 * And I/O.
370 */
371 __raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
372 __raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
373 __raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
122 374
123 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0); 375 __raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
124 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0); 376 PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
377 PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
125 378
126#ifdef CONFIG_32BIT 379 /*
127 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2); 380 * Initialization mode complete, release the control register and
128 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); 381 * enable round robin mode to stop device overruns/starvation.
129#endif 382 */
383 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO,
384 chan->reg_base + SH4_PCICR);
130 385
131 /* Set IOBR for windows containing area specified in pci.h */ 386 ret = register_pci_controller(chan);
132 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1), 387 if (unlikely(ret))
133 SH7780_PCIIOBR); 388 goto err;
134 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
135 SH7780_PCIIOBMR);
136 389
137 /* SH7780 init done, set central function init complete */ 390 sh7780_pci66_init(chan);
138 /* use round robin mode to stop a device starving/overruning */
139 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
140 pci_write_reg(chan, word, SH4_PCICR);
141 391
142 register_pci_controller(chan); 392 printk(KERN_NOTICE "PCI: Running at %dMHz.\n",
393 (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ?
394 66 : 33);
143 395
144 return 0; 396 return 0;
397
398err:
399 sh7780_pci_teardown_irqs(chan);
400 return ret;
145} 401}
146arch_initcall(sh7780_pci_init); 402arch_initcall(sh7780_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 4a52478c97cf..205dcbefe275 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -12,12 +12,11 @@
12#ifndef _PCI_SH7780_H_ 12#ifndef _PCI_SH7780_H_
13#define _PCI_SH7780_H_ 13#define _PCI_SH7780_H_
14 14
15/* Platform Specific Values */ 15#define PCI_VENDOR_ID_RENESAS 0x1912
16#define SH7780_VENDOR_ID 0x1912 16#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001
17#define SH7781_DEVICE_ID 0x0001 17#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002
18#define SH7780_DEVICE_ID 0x0002 18#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004
19#define SH7763_DEVICE_ID 0x0004 19#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
20#define SH7785_DEVICE_ID 0x0007
21 20
22/* SH7780 Control Registers */ 21/* SH7780 Control Registers */
23#define PCIECR 0xFE000008 22#define PCIECR 0xFE000008
@@ -27,44 +26,9 @@
27#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 26#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
28#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ 27#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
29 28
30#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
31#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
32
33#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */
34#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
35
36#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 29#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
37 30
38/* SH7780 PCI Config Registers */ 31/* SH7780 PCI Config Registers */
39#define SH7780_PCIVID 0x000 /* Vendor ID */
40#define SH7780_PCIDID 0x002 /* Device ID */
41#define SH7780_PCICMD 0x004 /* Command */
42#define SH7780_PCISTATUS 0x006 /* Status */
43#define SH7780_PCIRID 0x008 /* Revision ID */
44#define SH7780_PCIPIF 0x009 /* Program Interface */
45#define SH7780_PCISUB 0x00a /* Sub class code */
46#define SH7780_PCIBCC 0x00b /* Base class code */
47#define SH7780_PCICLS 0x00c /* Cache line size */
48#define SH7780_PCILTM 0x00d /* latency timer */
49#define SH7780_PCIHDR 0x00e /* Header type */
50#define SH7780_PCIBIST 0x00f /* BIST */
51#define SH7780_PCIIBAR 0x010 /* IO Base address */
52#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
53#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
54#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
55#define SH7780_PCISID 0x02e /* Sub system ID */
56#define SH7780_PCICP 0x034
57#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
58#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
59#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
60#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
61#define SH7780_PCICID 0x040
62#define SH7780_PCINIP 0x041
63#define SH7780_PCIPMC 0x042
64#define SH7780_PCIPMCSR 0x044
65#define SH7780_PCIPMCSR_BSE 0x046
66#define SH7780_PCICDD 0x047
67
68#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 32#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
69#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 33#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
70#define SH7780_PCIAIR 0x11C /* Error Address Register */ 34#define SH7780_PCIAIR 0x11C /* Error Address Register */
@@ -76,10 +40,8 @@
76#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ 40#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
77#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ 41#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
78 42
79#define SH7780_PCIMBR0 0x1E0 43#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8))
80#define SH7780_PCIMBMR0 0x1E4 44#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8))
81#define SH7780_PCIMBR2 0x1F0
82#define SH7780_PCIMBMR2 0x1F4
83#define SH7780_PCIIOBR 0x1F8 45#define SH7780_PCIIOBR 0x1F8
84#define SH7780_PCIIOBMR 0x1FC 46#define SH7780_PCIIOBMR 0x1FC
85#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ 47#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
@@ -87,16 +49,4 @@
87#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ 49#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
88#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ 50#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
89 51
90/* General Memory Config Addresses */
91#define SH7780_CS0_BASE_ADDR 0x0
92#define SH7780_MEM_REGION_SIZE 0x04000000
93#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
94#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
95#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
96#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
97#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
98#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
99
100#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
101
102#endif /* _PCI_SH7780_H_ */ 52#endif /* _PCI_SH7780_H_ */
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 96213fd172ce..953af139e230 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -33,15 +33,22 @@ static int pci_initialized;
33static void __devinit pcibios_scanbus(struct pci_channel *hose) 33static void __devinit pcibios_scanbus(struct pci_channel *hose)
34{ 34{
35 static int next_busno; 35 static int next_busno;
36 static int need_domain_info;
36 struct pci_bus *bus; 37 struct pci_bus *bus;
37 38
38 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
40 hose->bus = bus;
41
42 need_domain_info = need_domain_info || hose->index;
43 hose->need_domain_info = need_domain_info;
39 if (bus) { 44 if (bus) {
40 next_busno = bus->subordinate + 1; 45 next_busno = bus->subordinate + 1;
41 /* Don't allow 8-bit bus number overflow inside the hose - 46 /* Don't allow 8-bit bus number overflow inside the hose -
42 reserve some space for bridges. */ 47 reserve some space for bridges. */
43 if (next_busno > 224) 48 if (next_busno > 224) {
44 next_busno = 0; 49 next_busno = 0;
50 need_domain_info = 1;
51 }
45 52
46 pci_bus_size_bridges(bus); 53 pci_bus_size_bridges(bus);
47 pci_bus_assign_resources(bus); 54 pci_bus_assign_resources(bus);
@@ -51,10 +58,21 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
51 58
52static DEFINE_MUTEX(pci_scan_mutex); 59static DEFINE_MUTEX(pci_scan_mutex);
53 60
54void __devinit register_pci_controller(struct pci_channel *hose) 61int __devinit register_pci_controller(struct pci_channel *hose)
55{ 62{
56 request_resource(&iomem_resource, hose->mem_resource); 63 int i;
57 request_resource(&ioport_resource, hose->io_resource); 64
65 for (i = 0; i < hose->nr_resources; i++) {
66 struct resource *res = hose->resources + i;
67
68 if (res->flags & IORESOURCE_IO) {
69 if (request_resource(&ioport_resource, res) < 0)
70 goto out;
71 } else {
72 if (request_resource(&iomem_resource, res) < 0)
73 goto out;
74 }
75 }
58 76
59 *hose_tail = hose; 77 *hose_tail = hose;
60 hose_tail = &hose->next; 78 hose_tail = &hose->next;
@@ -68,6 +86,11 @@ void __devinit register_pci_controller(struct pci_channel *hose)
68 } 86 }
69 87
70 /* 88 /*
89 * Setup the ERR/PERR and SERR timers, if available.
90 */
91 pcibios_enable_timers(hose);
92
93 /*
71 * Scan the bus if it is register after the PCI subsystem 94 * Scan the bus if it is register after the PCI subsystem
72 * initialization. 95 * initialization.
73 */ 96 */
@@ -76,6 +99,15 @@ void __devinit register_pci_controller(struct pci_channel *hose)
76 pcibios_scanbus(hose); 99 pcibios_scanbus(hose);
77 mutex_unlock(&pci_scan_mutex); 100 mutex_unlock(&pci_scan_mutex);
78 } 101 }
102
103 return 0;
104
105out:
106 for (--i; i >= 0; i--)
107 release_resource(&hose->resources[i]);
108
109 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
110 return -1;
79} 111}
80 112
81static int __init pcibios_init(void) 113static int __init pcibios_init(void)
@@ -127,11 +159,13 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
127{ 159{
128 struct pci_dev *dev = bus->self; 160 struct pci_dev *dev = bus->self;
129 struct list_head *ln; 161 struct list_head *ln;
130 struct pci_channel *chan = bus->sysdata; 162 struct pci_channel *hose = bus->sysdata;
131 163
132 if (!dev) { 164 if (!dev) {
133 bus->resource[0] = chan->io_resource; 165 int i;
134 bus->resource[1] = chan->mem_resource; 166
167 for (i = 0; i < hose->nr_resources; i++)
168 bus->resource[i] = hose->resources + i;
135 } 169 }
136 170
137 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 171 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
@@ -152,30 +186,25 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
152 resource_size_t size, resource_size_t align) 186 resource_size_t size, resource_size_t align)
153{ 187{
154 struct pci_dev *dev = data; 188 struct pci_dev *dev = data;
155 struct pci_channel *chan = dev->sysdata; 189 struct pci_channel *hose = dev->sysdata;
156 resource_size_t start = res->start; 190 resource_size_t start = res->start;
157 191
158 if (res->flags & IORESOURCE_IO) { 192 if (res->flags & IORESOURCE_IO) {
159 if (start < PCIBIOS_MIN_IO + chan->io_resource->start) 193 if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
160 start = PCIBIOS_MIN_IO + chan->io_resource->start; 194 start = PCIBIOS_MIN_IO + hose->resources[0].start;
161 195
162 /* 196 /*
163 * Put everything into 0x00-0xff region modulo 0x400. 197 * Put everything into 0x00-0xff region modulo 0x400.
164 */ 198 */
165 if (start & 0x300) { 199 if (start & 0x300)
166 start = (start + 0x3ff) & ~0x3ff; 200 start = (start + 0x3ff) & ~0x3ff;
167 res->start = start;
168 }
169 } else if (res->flags & IORESOURCE_MEM) {
170 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
171 start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
172 } 201 }
173 202
174 return start; 203 return start;
175} 204}
176 205
177void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 206void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
178 struct resource *res) 207 struct resource *res)
179{ 208{
180 struct pci_channel *hose = dev->sysdata; 209 struct pci_channel *hose = dev->sysdata;
181 unsigned long offset = 0; 210 unsigned long offset = 0;
@@ -189,9 +218,8 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
189 region->end = res->end - offset; 218 region->end = res->end - offset;
190} 219}
191 220
192void __devinit 221void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
193pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 222 struct pci_bus_region *region)
194 struct pci_bus_region *region)
195{ 223{
196 struct pci_channel *hose = dev->sysdata; 224 struct pci_channel *hose = dev->sysdata;
197 unsigned long offset = 0; 225 unsigned long offset = 0;
@@ -274,6 +302,86 @@ char * __devinit pcibios_setup(char *str)
274 return str; 302 return str;
275} 303}
276 304
305static void __init
306pcibios_bus_report_status_early(struct pci_channel *hose,
307 int top_bus, int current_bus,
308 unsigned int status_mask, int warn)
309{
310 unsigned int pci_devfn;
311 u16 status;
312 int ret;
313
314 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
315 if (PCI_FUNC(pci_devfn))
316 continue;
317 ret = early_read_config_word(hose, top_bus, current_bus,
318 pci_devfn, PCI_STATUS, &status);
319 if (ret != PCIBIOS_SUCCESSFUL)
320 continue;
321 if (status == 0xffff)
322 continue;
323
324 early_write_config_word(hose, top_bus, current_bus,
325 pci_devfn, PCI_STATUS,
326 status & status_mask);
327 if (warn)
328 printk("(%02x:%02x: %04X) ", current_bus,
329 pci_devfn, status);
330 }
331}
332
333/*
334 * We can't use pci_find_device() here since we are
335 * called from interrupt context.
336 */
337static void __init_refok
338pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
339 int warn)
340{
341 struct pci_dev *dev;
342
343 list_for_each_entry(dev, &bus->devices, bus_list) {
344 u16 status;
345
346 /*
347 * ignore host bridge - we handle
348 * that separately
349 */
350 if (dev->bus->number == 0 && dev->devfn == 0)
351 continue;
352
353 pci_read_config_word(dev, PCI_STATUS, &status);
354 if (status == 0xffff)
355 continue;
356
357 if ((status & status_mask) == 0)
358 continue;
359
360 /* clear the status errors */
361 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
362
363 if (warn)
364 printk("(%s: %04X) ", pci_name(dev), status);
365 }
366
367 list_for_each_entry(dev, &bus->devices, bus_list)
368 if (dev->subordinate)
369 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
370}
371
372void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
373{
374 struct pci_channel *hose;
375
376 for (hose = hose_head; hose; hose = hose->next) {
377 if (unlikely(!hose->bus))
378 pcibios_bus_report_status_early(hose, hose_head->index,
379 hose->index, status_mask, warn);
380 else
381 pcibios_bus_report_status(hose->bus, status_mask, warn);
382 }
383}
384
277int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 385int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
278 enum pci_mmap_state mmap_state, int write_combine) 386 enum pci_mmap_state mmap_state, int write_combine)
279{ 387{
@@ -302,9 +410,15 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
302{ 410{
303 struct pci_channel *chan = dev->sysdata; 411 struct pci_channel *chan = dev->sysdata;
304 412
305 if (!chan->io_map_base) 413 if (unlikely(!chan->io_map_base)) {
306 chan->io_map_base = generic_io_base; 414 chan->io_map_base = generic_io_base;
307 415
416 if (pci_domains_supported)
417 panic("To avoid data corruption io_map_base MUST be "
418 "set with multiple PCI domains.");
419 }
420
421
308 return (void __iomem *)(chan->io_map_base + port); 422 return (void __iomem *)(chan->io_map_base + port);
309} 423}
310 424
@@ -321,20 +435,9 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
321 435
322 if (flags & IORESOURCE_IO) 436 if (flags & IORESOURCE_IO)
323 return ioport_map_pci(dev, start, len); 437 return ioport_map_pci(dev, start, len);
324
325 /*
326 * Presently the IORESOURCE_MEM case is a bit special, most
327 * SH7751 style PCI controllers have PCI memory at a fixed
328 * location in the address space where no remapping is desired.
329 * With the IORESOURCE_MEM case more care has to be taken
330 * to inhibit page table mapping for legacy cores, but this is
331 * punted off to __ioremap().
332 * -- PFM.
333 */
334 if (flags & IORESOURCE_MEM) { 438 if (flags & IORESOURCE_MEM) {
335 if (flags & IORESOURCE_CACHEABLE) 439 if (flags & IORESOURCE_CACHEABLE)
336 return ioremap(start, len); 440 return ioremap(start, len);
337
338 return ioremap_nocache(start, len); 441 return ioremap_nocache(start, len);
339 } 442 }
340 443
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index ac37ee879bab..ae91a2dd9183 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Low-Level PCI Express Support for the SH7786 2 * Low-Level PCI Express Support for the SH7786
3 * 3 *
4 * Copyright (C) 2009 Paul Mundt 4 * Copyright (C) 2009 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -30,60 +30,84 @@ static struct sh7786_pcie_hwops {
30 int (*port_init_hw)(struct sh7786_pcie_port *port); 30 int (*port_init_hw)(struct sh7786_pcie_port *port);
31} *sh7786_pcie_hwops; 31} *sh7786_pcie_hwops;
32 32
33static struct resource sh7786_pci_32bit_mem_resources[] = { 33static struct resource sh7786_pci0_resources[] = {
34 { 34 {
35 .name = "pci0_mem", 35 .name = "PCIe0 IO",
36 .start = SH4A_PCIMEM_BASEA, 36 .start = 0xfd000000,
37 .end = SH4A_PCIMEM_BASEA + SZ_64M - 1, 37 .end = 0xfd000000 + SZ_8M - 1,
38 .flags = IORESOURCE_MEM, 38 .flags = IORESOURCE_IO,
39 }, { 39 }, {
40 .name = "pci1_mem", 40 .name = "PCIe0 MEM 0",
41 .start = SH4A_PCIMEM_BASEA1, 41 .start = 0xc0000000,
42 .end = SH4A_PCIMEM_BASEA1 + SZ_64M - 1, 42 .end = 0xc0000000 + SZ_512M - 1,
43 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
44 }, { 44 }, {
45 .name = "pci2_mem", 45 .name = "PCIe0 MEM 1",
46 .start = SH4A_PCIMEM_BASEA2, 46 .start = 0x10000000,
47 .end = SH4A_PCIMEM_BASEA2 + SZ_64M - 1, 47 .end = 0x10000000 + SZ_64M - 1,
48 .flags = IORESOURCE_MEM, 48 .flags = IORESOURCE_MEM,
49 }, {
50 .name = "PCIe0 MEM 2",
51 .start = 0xfe100000,
52 .end = 0xfe100000 + SZ_1M - 1,
49 }, 53 },
50}; 54};
51 55
52static struct resource sh7786_pci_29bit_mem_resource = { 56static struct resource sh7786_pci1_resources[] = {
53 .start = SH4A_PCIMEM_BASE, 57 {
54 .end = SH4A_PCIMEM_BASE + SZ_64M - 1, 58 .name = "PCIe1 IO",
55 .flags = IORESOURCE_MEM, 59 .start = 0xfd800000,
60 .end = 0xfd800000 + SZ_8M - 1,
61 .flags = IORESOURCE_IO,
62 }, {
63 .name = "PCIe1 MEM 0",
64 .start = 0xa0000000,
65 .end = 0xa0000000 + SZ_512M - 1,
66 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
67 }, {
68 .name = "PCIe1 MEM 1",
69 .start = 0x30000000,
70 .end = 0x30000000 + SZ_256M - 1,
71 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
72 }, {
73 .name = "PCIe1 MEM 2",
74 .start = 0xfe300000,
75 .end = 0xfe300000 + SZ_1M - 1,
76 },
56}; 77};
57 78
58static struct resource sh7786_pci_io_resources[] = { 79static struct resource sh7786_pci2_resources[] = {
59 { 80 {
60 .name = "pci0_io", 81 .name = "PCIe2 IO",
61 .start = SH4A_PCIIO_BASE, 82 .start = 0xfc800000,
62 .end = SH4A_PCIIO_BASE + SZ_8M - 1, 83 .end = 0xfc800000 + SZ_4M - 1,
63 .flags = IORESOURCE_IO,
64 }, { 84 }, {
65 .name = "pci1_io", 85 .name = "PCIe2 MEM 0",
66 .start = SH4A_PCIIO_BASE1, 86 .start = 0x80000000,
67 .end = SH4A_PCIIO_BASE1 + SZ_8M - 1, 87 .end = 0x80000000 + SZ_512M - 1,
68 .flags = IORESOURCE_IO, 88 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
69 }, { 89 }, {
70 .name = "pci2_io", 90 .name = "PCIe2 MEM 1",
71 .start = SH4A_PCIIO_BASE2, 91 .start = 0x20000000,
72 .end = SH4A_PCIIO_BASE2 + SZ_4M - 1, 92 .end = 0x20000000 + SZ_256M - 1,
73 .flags = IORESOURCE_IO, 93 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
94 }, {
95 .name = "PCIe2 MEM 2",
96 .start = 0xfcd00000,
97 .end = 0xfcd00000 + SZ_1M - 1,
74 }, 98 },
75}; 99};
76 100
77extern struct pci_ops sh7786_pci_ops; 101extern struct pci_ops sh7786_pci_ops;
78 102
79#define DEFINE_CONTROLLER(start, idx) \ 103#define DEFINE_CONTROLLER(start, idx) \
80{ \ 104{ \
81 .pci_ops = &sh7786_pci_ops, \ 105 .pci_ops = &sh7786_pci_ops, \
82 .reg_base = start, \ 106 .resources = sh7786_pci##idx##_resources, \
83 /* mem_resource filled in at probe time */ \ 107 .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
84 .mem_offset = 0, \ 108 .reg_base = start, \
85 .io_resource = &sh7786_pci_io_resources[idx], \ 109 .mem_offset = 0, \
86 .io_offset = 0, \ 110 .io_offset = 0, \
87} 111}
88 112
89static struct pci_channel sh7786_pci_channels[] = { 113static struct pci_channel sh7786_pci_channels[] = {
@@ -180,7 +204,9 @@ static int pcie_init(struct sh7786_pcie_port *port)
180{ 204{
181 struct pci_channel *chan = port->hose; 205 struct pci_channel *chan = port->hose;
182 unsigned int data; 206 unsigned int data;
183 int ret; 207 phys_addr_t memphys;
208 size_t memsize;
209 int ret, i;
184 210
185 /* Begin initialization */ 211 /* Begin initialization */
186 pci_write_reg(chan, 0, SH4A_PCIETCTLR); 212 pci_write_reg(chan, 0, SH4A_PCIETCTLR);
@@ -203,15 +229,24 @@ static int pcie_init(struct sh7786_pcie_port *port)
203 data |= PCI_CAP_ID_EXP; 229 data |= PCI_CAP_ID_EXP;
204 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0); 230 pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
205 231
206 /* Enable x4 link width and extended sync. */ 232 /* Enable data link layer active state reporting */
233 pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
234
235 /* Enable extended sync and ASPM L0s support */
207 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4); 236 data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
208 data &= ~(PCI_EXP_LNKSTA_NLW << 16); 237 data &= ~PCI_EXP_LNKCTL_ASPMC;
209 data |= (1 << 22) | PCI_EXP_LNKCTL_ES; 238 data |= PCI_EXP_LNKCTL_ES | 1;
210 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4); 239 pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
211 240
241 /* Write out the physical slot number */
242 data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
243 data &= ~PCI_EXP_SLTCAP_PSN;
244 data |= (port->index + 1) << 19;
245 pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
246
212 /* Set the completion timer timeout to the maximum 32ms. */ 247 /* Set the completion timer timeout to the maximum 32ms. */
213 data = pci_read_reg(chan, SH4A_PCIETLCTLR); 248 data = pci_read_reg(chan, SH4A_PCIETLCTLR);
214 data &= ~0xffff; 249 data &= ~0x3f00;
215 data |= 0x32 << 8; 250 data |= 0x32 << 8;
216 pci_write_reg(chan, data, SH4A_PCIETLCTLR); 251 pci_write_reg(chan, data, SH4A_PCIETLCTLR);
217 252
@@ -224,6 +259,33 @@ static int pcie_init(struct sh7786_pcie_port *port)
224 data |= (0xff << 16); 259 data |= (0xff << 16);
225 pci_write_reg(chan, data, SH4A_PCIEMACCTLR); 260 pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
226 261
262 memphys = __pa(memory_start);
263 memsize = roundup_pow_of_two(memory_end - memory_start);
264
265 /*
266 * If there's more than 512MB of memory, we need to roll over to
267 * LAR1/LAMR1.
268 */
269 if (memsize > SZ_512M) {
270 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
271 __raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
272 chan->reg_base + SH4A_PCIELAMR1);
273 memsize = SZ_512M;
274 } else {
275 /*
276 * Otherwise just zero it out and disable it.
277 */
278 __raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
279 __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
280 }
281
282 /*
283 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
284 * cover all of lowmem on most platforms.
285 */
286 __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
287 __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
288
227 /* Finish initialization */ 289 /* Finish initialization */
228 data = pci_read_reg(chan, SH4A_PCIETCTLR); 290 data = pci_read_reg(chan, SH4A_PCIETCTLR);
229 data |= 0x1; 291 data |= 0x1;
@@ -243,10 +305,14 @@ static int pcie_init(struct sh7786_pcie_port *port)
243 if (unlikely(ret != 0)) 305 if (unlikely(ret != 0))
244 return -ENODEV; 306 return -ENODEV;
245 307
246 pci_write_reg(chan, 0x00100007, SH4A_PCIEPCICONF1); 308 data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
309 data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
310 data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
311 (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
312 pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
313
247 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR); 314 pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
248 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR); 315 pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
249 pci_write_reg(chan, 0x000050A0, SH4A_PCIEEXPCAP2);
250 316
251 wmb(); 317 wmb();
252 318
@@ -254,15 +320,32 @@ static int pcie_init(struct sh7786_pcie_port *port)
254 printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n", 320 printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
255 port->index, (data >> 20) & 0x3f); 321 port->index, (data >> 20) & 0x3f);
256 322
257 pci_write_reg(chan, 0x007c0000, SH4A_PCIEPAMR0);
258 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH0);
259 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL0);
260 pci_write_reg(chan, 0x80000100, SH4A_PCIEPTCTLR0);
261 323
262 pci_write_reg(chan, 0x03fc0000, SH4A_PCIEPAMR2); 324 for (i = 0; i < chan->nr_resources; i++) {
263 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH2); 325 struct resource *res = chan->resources + i;
264 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL2); 326 resource_size_t size;
265 pci_write_reg(chan, 0x80000000, SH4A_PCIEPTCTLR2); 327 u32 enable_mask;
328
329 pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
330
331 size = resource_size(res);
332
333 /*
334 * The PAMR mask is calculated in units of 256kB, which
335 * keeps things pretty simple.
336 */
337 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
338 chan->reg_base + SH4A_PCIEPAMR(i));
339
340 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
341 pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
342
343 enable_mask = MASK_PARE;
344 if (res->flags & IORESOURCE_IO)
345 enable_mask |= MASK_SPC;
346
347 pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
348 }
266 349
267 return 0; 350 return 0;
268} 351}
@@ -296,9 +379,7 @@ static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
296 if (unlikely(ret < 0)) 379 if (unlikely(ret < 0))
297 return ret; 380 return ret;
298 381
299 register_pci_controller(port->hose); 382 return register_pci_controller(port->hose);
300
301 return 0;
302} 383}
303 384
304static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { 385static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
@@ -332,17 +413,7 @@ static int __init sh7786_pcie_init(void)
332 413
333 port->index = i; 414 port->index = i;
334 port->hose = sh7786_pci_channels + i; 415 port->hose = sh7786_pci_channels + i;
335 port->hose->io_map_base = port->hose->io_resource->start; 416 port->hose->io_map_base = port->hose->resources[0].start;
336
337 /*
338 * Check if we are booting in 29 or 32-bit mode
339 *
340 * 32-bit mode provides each controller with its own
341 * memory window, while 29-bit mode uses a shared one.
342 */
343 port->hose->mem_resource = test_mode_pin(MODE_PIN10) ?
344 &sh7786_pci_32bit_mem_resources[i] :
345 &sh7786_pci_29bit_mem_resource;
346 417
347 ret |= sh7786_pcie_hwops->port_init_hw(port); 418 ret |= sh7786_pcie_hwops->port_init_hw(port);
348 } 419 }
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index c655290a7750..90a6992576b0 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -30,47 +30,9 @@
30 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M) 30 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
31 */ 31 */
32 32
33/* PCI0-0: PCI I/O space */
34#define SH4A_PCIIO_BASE 0xFD000000 /* PCI I/O for controller 0 */
35#define SH4A_PCIIO_BASE1 0xFD800000 /* PCI I/O for controller 1 (Rev1.14)*/
36#define SH4A_PCIIO_BASE2 0xFC800000 /* PCI I/O for controller 2 (Rev1.171)*/
37
38#define SH4A_PCIIO_SIZE64 0x00010000 /* PLX allows only 64K */
39#define SH4A_PCIIO_SIZE 0x00800000 /* 8M */
40#define SH4A_PCIIO_SIZE2 0x00400000 /* 4M (Rev1.171)*/
41
42/* PCI0-1: PCI memory space 29-bit address */
43#define SH4A_PCIMEM_BASE 0x10000000
44#define SH4A_PCIMEM_SIZE 0x04000000 /* 64M */
45
46/* PCI0-2: PCI memory space 32-bit address */
47#define SH4A_PCIMEM_BASEA 0xC0000000 /* for controller 0 */
48#define SH4A_PCIMEM_BASEA1 0xA0000000 /* for controller 1 (Rev1.14)*/
49#define SH4A_PCIMEM_BASEA2 0x80000000 /* for controller 2 (Rev1.171)*/
50#define SH4A_PCIMEM_SIZEA 0x20000000 /* 512M */
51
52/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/ 33/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
53#define SH4A_PCIBMSTR_TRANSLATION 0x20000000 34#define SH4A_PCIBMSTR_TRANSLATION 0x20000000
54 35
55#define SH4A_PCI_DEVICE_ID 0x0002
56#define SH4A_PCI_VENDOR_ID 0x1912
57
58// PCI compatible 000-03f
59#define PCI_CMD 0x004
60#define PCI_RID 0x008
61#define PCI_IBAR 0x010
62#define PCI_MBAR0 0x014
63#define PCI_MBAR1 0x018
64
65/* PCI power management/MSI/capablity 040-0ff */
66/* PCIE extended 100-fff */
67
68/* SH7786 device identification */ // Rev1.171
69#define SH4A_PVR (0xFF000030)
70#define SH4A_PVR_SHX3 (0x10400000)
71#define SH4A_PRR (0xFF000044)
72#define SH4A_PRR_SH7786 (0x00000400) // Rev1.171
73
74/* SPVCR0 */ 36/* SPVCR0 */
75#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */ 37#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
76#define BITS_TOP_MB (24) 38#define BITS_TOP_MB (24)
@@ -350,23 +312,23 @@
350#define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */ 312#define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */
351#define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */ 313#define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */
352 314
353/* PCIEPARL0 */ 315/* PCIEPARL */
354#define SH4A_PCIEPARL0 (0x020400) /* R/W R/W 0x0000 0000 32 */ 316#define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
355#define BITS_PAL (18) 317#define BITS_PAL (18)
356#define MASK_PAL (0x3fff<<BITS_PAL) 318#define MASK_PAL (0x3fff<<BITS_PAL)
357 319
358/* PCIEPARH0 */ 320/* PCIEPARH */
359#define SH4A_PCIEPARH0 (0x020404) /* R/W R/W 0x0000 0000 32 */ 321#define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
360#define BITS_PAH (0) 322#define BITS_PAH (0)
361#define MASK_PAH (0xffffffff<<BITS_PAH) 323#define MASK_PAH (0xffffffff<<BITS_PAH)
362 324
363/* PCIEPAMR0 */ 325/* PCIEPAMR */
364#define SH4A_PCIEPAMR0 (0x020408) /* R/W R/W 0x0000 0000 32 */ 326#define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
365#define BITS_PAM (18) 327#define BITS_PAM (18)
366#define MASK_PAM (0x3fff<<BITS_PAM) 328#define MASK_PAM (0x3fff<<BITS_PAM)
367 329
368/* PCIEPTCTLR0 */ 330/* PCIEPTCTLR */
369#define SH4A_PCIEPTCTLR0 (0x02040C) /* R/W R/W 0x0000 0000 32 */ 331#define SH4A_PCIEPTCTLR(x) (0x02040C + ((x) * 0x20))
370#define BITS_PARE (31) 332#define BITS_PARE (31)
371#define MASK_PARE (0x1<<BITS_PARE) 333#define MASK_PARE (0x1<<BITS_PARE)
372#define BITS_TC (20) 334#define BITS_TC (20)
@@ -378,26 +340,6 @@
378#define BITS_SPC (8) 340#define BITS_SPC (8)
379#define MASK_SPC (0x1<<BITS_SPC) 341#define MASK_SPC (0x1<<BITS_SPC)
380 342
381#define SH4A_PCIEPARL1 (0x020420) /* R/W R/W 0x0000 0000 32 */
382#define SH4A_PCIEPARH1 (0x020424) /* R/W R/W 0x0000 0000 32 */
383#define SH4A_PCIEPAMR1 (0x020428) /* R/W R/W 0x0000 0000 32 */
384#define SH4A_PCIEPTCTLR1 (0x02042C) /* R/W R/W 0x0000 0000 32 */
385#define SH4A_PCIEPARL2 (0x020440) /* R/W R/W 0x0000 0000 32 */
386#define SH4A_PCIEPARH2 (0x020444) /* R/W R/W 0x0000 0000 32 */
387#define SH4A_PCIEPAMR2 (0x020448) /* R/W R/W 0x0000 0000 32 */
388#define SH4A_PCIEPTCTLR2 (0x02044C) /* R/W R/W 0x0000 0000 32 */
389#define SH4A_PCIEPARL3 (0x020460) /* R/W R/W 0x0000 0000 32 */
390#define SH4A_PCIEPARH3 (0x020464) /* R/W R/W 0x0000 0000 32 */
391#define SH4A_PCIEPAMR3 (0x020468) /* R/W R/W 0x0000 0000 32 */
392#define SH4A_PCIEPTCTLR3 (0x02046C) /* R/W R/W 0x0000 0000 32 */
393#define SH4A_PCIEPARL4 (0x020480) /* R/W R/W 0x0000 0000 32 */
394#define SH4A_PCIEPARH4 (0x020484) /* R/W R/W 0x0000 0000 32 */
395#define SH4A_PCIEPAMR4 (0x020488) /* R/W R/W 0x0000 0000 32 */
396#define SH4A_PCIEPTCTLR4 (0x02048C) /* R/W R/W 0x0000 0000 32 */
397#define SH4A_PCIEPARL5 (0x0204A0) /* R/W R/W 0x0000 0000 32 */
398#define SH4A_PCIEPARH5 (0x0204A4) /* R/W R/W 0x0000 0000 32 */
399#define SH4A_PCIEPAMR5 (0x0204A8) /* R/W R/W 0x0000 0000 32 */
400#define SH4A_PCIEPTCTLR5 (0x0204AC) /* R/W R/W 0x0000 0000 32 */
401#define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */ 343#define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */
402#define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */ 344#define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */
403#define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */ 345#define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 23:34:19 -0500