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-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c30
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h16
2 files changed, 38 insertions, 8 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 16b30a9e94bb..5508e45d4838 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -72,12 +72,27 @@ static int __init sh7780_pci_init(void)
72 } 72 }
73 73
74 /* Setup the INTC */ 74 /* Setup the INTC */
75 ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */ 75 if (mach_is_7780se()) {
76 ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */ 76 /* ICR0: IRL=use separately */
77 ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */ 77 ctrl_outl(0x00C00020, INTC_ICR0);
78 ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */ 78 /* ICR1: detect low level(for 2ndcut) */
79 ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */ 79 ctrl_outl(0xAAAA0000, INTC_ICR1);
80 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */ 80 /* INTPRI: priority=3(all) */
81 ctrl_outl(0x33333333, INTC_INTPRI);
82 } else {
83 /* INTC SH-4 Mode */
84 ctrl_outl(0x00200000, INTC_ICR0);
85 /* enable PCIINTA - PCIINTD */
86 ctrl_outl(0x00078000, INTC_INT2MSKCR);
87 /* disable IRL4-7 Interrupt */
88 ctrl_outl(0x40000000, INTC_INTMSK1);
89 /* disable IRL4-7 Interrupt */
90 ctrl_outl(0x0000fffe, INTC_INTMSK2);
91 /* enable IRL0-3 Interrupt */
92 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
93 /* enable IRL0-3 Interrupt */
94 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
95 }
81 96
82 if ((ret = sh4_pci_check_direct()) != 0) 97 if ((ret = sh4_pci_check_direct()) != 0)
83 return ret; 98 return ret;
@@ -147,9 +162,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
147 * DMA interrupts... 162 * DMA interrupts...
148 */ 163 */
149 164
150#ifdef CONFIG_SH_HIGHLANDER 165 /* Apply any last-minute PCIC fixups */
151 pci_fixup_pcic(); 166 pci_fixup_pcic();
152#endif
153 167
154 /* SH7780 init done, set central function init complete */ 168 /* SH7780 init done, set central function init complete */
155 /* use round robin mode to stop a device starving/overruning */ 169 /* use round robin mode to stop a device starving/overruning */
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index bd44255509e6..00d12d0f8c1f 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -66,6 +66,22 @@
66#define SH7780_PCIPMCSR_BSE 0x046 66#define SH7780_PCIPMCSR_BSE 0x046
67#define SH7780_PCICDD 0x047 67#define SH7780_PCICDD 0x047
68 68
69#define SH7780_PCICR 0x100 /* PCI Control Register */
70#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
71#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
72#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
73#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
74#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
75#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
76#define SH7780_PCIAIR 0x11C /* Error Address Register */
77#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
78#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
79#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
80#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
81#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
82#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
83#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
84
69#define SH7780_PCIMBR0 0x1E0 85#define SH7780_PCIMBR0 0x1E0
70#define SH7780_PCIMBMR0 0x1E4 86#define SH7780_PCIMBMR0 0x1E4
71#define SH7780_PCIMBR2 0x1F0 87#define SH7780_PCIMBR2 0x1F0