aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/drivers/pci
diff options
context:
space:
mode:
Diffstat (limited to 'arch/sh/drivers/pci')
-rw-r--r--arch/sh/drivers/pci/Makefile5
-rw-r--r--arch/sh/drivers/pci/fixups-lboxre2.c41
-rw-r--r--arch/sh/drivers/pci/fixups-se7780.c60
-rw-r--r--arch/sh/drivers/pci/ops-landisk.c4
-rw-r--r--arch/sh/drivers/pci/ops-lboxre2.c63
-rw-r--r--arch/sh/drivers/pci/ops-r7780rp.c27
-rw-r--r--arch/sh/drivers/pci/ops-se7780.c96
-rw-r--r--arch/sh/drivers/pci/ops-sh4.c6
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h2
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c15
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c45
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h19
12 files changed, 348 insertions, 35 deletions
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index cc8d0d0b1427..0e9b532b9fbc 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -8,12 +8,15 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o 8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
11 12
12obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ 13obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
13 dma-dreamcast.o 14 dma-dreamcast.o
14obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o 15obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
15obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o 16obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
16obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o 17obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
17obj-$(CONFIG_SH_R7780RP) += ops-r7780rp.o fixups-r7780rp.o 18obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o
18obj-$(CONFIG_SH_TITAN) += ops-titan.o 19obj-$(CONFIG_SH_TITAN) += ops-titan.o
19obj-$(CONFIG_SH_LANDISK) += ops-landisk.o 20obj-$(CONFIG_SH_LANDISK) += ops-landisk.o
21obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o
22obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c
new file mode 100644
index 000000000000..40b19bdfb891
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-lboxre2.c
@@ -0,0 +1,41 @@
1/*
2 * arch/sh/drivers/pci/fixups-lboxre2.c
3 *
4 * L-BOX RE2 PCI fixups
5 *
6 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include "pci-sh4.h"
13
14#define PCIMCR_MRSET_OFF 0xBFFFFFFF
15#define PCIMCR_RFSH_OFF 0xFFFFFFFB
16
17int pci_fixup_pcic(void)
18{
19 unsigned long bcr1, mcr;
20
21 bcr1 = inl(SH7751_BCR1);
22 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
23 pci_write_reg(bcr1, SH4_PCIBCR1);
24
25 /* Enable all interrupts, so we known what to fix */
26 pci_write_reg(0x0000c3ff, SH4_PCIINTM);
27 pci_write_reg(0x0000380f, SH4_PCIAINTM);
28 pci_write_reg(0xfb900047, SH7751_PCICONF1);
29 pci_write_reg(0xab000001, SH7751_PCICONF4);
30
31 mcr = inl(SH7751_MCR);
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
33 pci_write_reg(mcr, SH4_PCIMCR);
34
35 pci_write_reg(0x0c000000, SH7751_PCICONF5);
36 pci_write_reg(0xd0000000, SH7751_PCICONF6);
37 pci_write_reg(0x0c000000, SH4_PCILAR0);
38 pci_write_reg(0x00000000, SH4_PCILAR1);
39
40 return 0;
41}
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
new file mode 100644
index 000000000000..880cea1c0d89
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-se7780.c
@@ -0,0 +1,60 @@
1/*
2 * arch/sh/drivers/pci/fixups-se7780.c
3 *
4 * HITACHI UL Solution Engine 7780 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
15#include "pci-sh4.h"
16#include <asm/io.h>
17
18int pci_fixup_pcic(void)
19{
20 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21
22 /* Enable all interrupts, so we know what to fix */
23 pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
24 pci_write_reg(0x0000380F, SH7780_PCIAINTM);
25
26 /* Set up standard PCI config registers */
27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
28 ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
29 ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
30 ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
31 ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34
35 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
36 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
37 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
38
39 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
40 pci_write_reg(0x00000000, SH7780_PCILAR1);
41 pci_write_reg(0x00000000, SH7780_PCILSR1);
42
43 pci_write_reg(0xAB000801, SH7780_PCIIBAR);
44
45 /*
46 * Set the MBR so PCI address is one-to-one with window,
47 * meaning all calls go straight through... use ifdef to
48 * catch erroneous assumption.
49 */
50 pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
51 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
52
53 /* Set IOBR for window containing area specified in pci.h */
54 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
55 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
56
57 pci_write_reg(0xA5000C01, SH7780_PCICR);
58
59 return 0;
60}
diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/ops-landisk.c
index d06030815a96..bff09ecf3419 100644
--- a/arch/sh/drivers/pci/ops-landisk.c
+++ b/arch/sh/drivers/pci/ops-landisk.c
@@ -17,8 +17,8 @@
17 17
18static struct resource sh7751_io_resource = { 18static struct resource sh7751_io_resource = {
19 .name = "SH7751 IO", 19 .name = "SH7751 IO",
20 .start = 0x4000, 20 .start = SH7751_PCI_IO_BASE,
21 .end = 0x4000 + SH7751_PCI_IO_SIZE - 1, 21 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
22 .flags = IORESOURCE_IO 22 .flags = IORESOURCE_IO
23}; 23};
24 24
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c
new file mode 100644
index 000000000000..a13cb764b0b9
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-lboxre2.c
@@ -0,0 +1,63 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-lboxre2.c
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the NTT COMWARE L-BOX RE2
7 */
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <linux/io.h>
13#include <asm/lboxre2.h>
14#include "pci-sh4.h"
15
16static char lboxre2_irq_tab[] __initdata = {
17 IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
18};
19
20int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
21{
22 return lboxre2_irq_tab[slot];
23}
24
25static struct resource sh7751_io_resource = {
26 .name = "SH7751_IO",
27 .start = SH7751_PCI_IO_BASE ,
28 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
29 .flags = IORESOURCE_IO
30};
31
32static struct resource sh7751_mem_resource = {
33 .name = "SH7751_mem",
34 .start = SH7751_PCI_MEMORY_BASE,
35 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
36 .flags = IORESOURCE_MEM
37};
38
39extern struct pci_ops sh7751_pci_ops;
40
41struct pci_channel board_pci_channels[] = {
42 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
43 { NULL, NULL, NULL, 0, 0 },
44};
45
46EXPORT_SYMBOL(board_pci_channels);
47
48static struct sh4_pci_address_map sh7751_pci_map = {
49 .window0 = {
50 .base = SH7751_CS3_BASE_ADDR,
51 .size = 0x04000000,
52 },
53 .window1 = {
54 .base = 0x00000000, /* Unused */
55 .size = 0x00000000, /* Unused */
56 },
57 .flags = SH4_PCIC_NO_RESET,
58};
59
60int __init pcibios_init_platform(void)
61{
62 return sh7751_pcic_init(&sh7751_pci_map);
63}
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
index eeea1577e112..f2216081ab85 100644
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ b/arch/sh/drivers/pci/ops-r7780rp.c
@@ -17,18 +17,25 @@
17#include <asm/io.h> 17#include <asm/io.h>
18#include "pci-sh4.h" 18#include "pci-sh4.h"
19 19
20static char r7780rp_irq_tab[] __initdata = {
21 0, 1, 2, 3,
22};
23
24static char r7780mp_irq_tab[] __initdata = {
25 65, 66, 67, 68,
26};
27
20int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 28int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
21{ 29{
22 switch (slot) { 30 if (mach_is_r7780rp())
23 case 0: return IRQ_PCISLOT1; /* PCI Interrupt #1 */ 31 return r7780rp_irq_tab[slot];
24 case 1: return IRQ_PCISLOT2; /* PCI Interrupt #2 */ 32 if (mach_is_r7780mp() || mach_is_r7785rp())
25 case 2: return IRQ_PCISLOT3; /* PCI Interrupt #3 */ 33 return r7780mp_irq_tab[slot];
26 case 3: return IRQ_PCISLOT4; /* PCI Interrupt E4 */ 34
27 default: 35 printk(KERN_ERR "PCI: Bad IRQ mapping "
28 printk(KERN_ERR "PCI: Bad IRQ mapping " 36 "request for slot %d, func %d\n", slot, pin-1);
29 "request for slot %d, func %d\n", slot, pin-1); 37
30 return -1; 38 return -1;
31 }
32} 39}
33 40
34static struct resource sh7780_io_resource = { 41static struct resource sh7780_io_resource = {
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
new file mode 100644
index 000000000000..212674df5e13
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-se7780.c
@@ -0,0 +1,96 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-se7780.c
3 *
4 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the Hitachi UL Solution Engine 7780SE03
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <asm/se7780.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20/*
21 * IDSEL = AD16 PCI slot
22 * IDSEL = AD17 PCI slot
23 * IDSEL = AD18 Serial ATA Controller (Silicon Image SiL3512A)
24 * IDSEL = AD19 USB Host Controller (NEC uPD7210100A)
25 */
26
27/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
28static char se7780_irq_tab[4][16] __initdata = {
29 /* INTA */
30 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
31 /* INTB */
32 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
33 /* INTC */
34 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
35 /* INTD */
36 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
37};
38
39int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
40{
41 return se7780_irq_tab[pin-1][slot];
42}
43
44static struct resource se7780_io_resource = {
45 .name = "SH7780_IO",
46 .start = 0x2000,
47 .end = 0x2000 + SH7780_PCI_IO_SIZE - 1,
48 .flags = IORESOURCE_IO
49};
50
51static struct resource se7780_mem_resource = {
52 .name = "SH7780_mem",
53 .start = SH7780_PCI_MEMORY_BASE,
54 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
55 .flags = IORESOURCE_MEM
56};
57
58extern struct pci_ops se7780_pci_ops;
59
60struct pci_channel board_pci_channels[] = {
61 { &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
62 { NULL, NULL, NULL, 0, 0 },
63};
64EXPORT_SYMBOL(board_pci_channels);
65
66static struct sh4_pci_address_map se7780_pci_map = {
67 .window0 = {
68 .base = SH7780_CS2_BASE_ADDR,
69 .size = 0x04000000,
70 },
71 .flags = SH4_PCIC_NO_RESET,
72};
73
74int __init pcibios_init_platform(void)
75{
76 printk("SH7780 PCI: Finished initialization of the PCI controller\n");
77
78 /*
79 * FPGA PCISEL register initialize
80 *
81 * CPU || SLOT1 | SLOT2 | S-ATA | USB
82 * -------------------------------------
83 * INTA || INTA | INTD | -- | INTB
84 * -------------------------------------
85 * INTB || INTB | INTA | -- | INTC
86 * -------------------------------------
87 * INTC || INTC | INTB | INTA | --
88 * -------------------------------------
89 * INTD || INTD | INTC | -- | INTA
90 * -------------------------------------
91 */
92 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
93 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
94
95 return sh7780_pcic_init(&se7780_pci_map);
96}
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 2d4371009a5e..54232f13e406 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -162,3 +162,9 @@ char * __init pcibios_setup(char *str)
162 162
163 return str; 163 return str;
164} 164}
165
166int __attribute__((weak)) pci_fixup_pcic(void)
167{
168 /* Nothing to do. */
169 return 0;
170}
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 5a61d6041f2c..1901c33cde6a 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -1,7 +1,7 @@
1#ifndef __PCI_SH4_H 1#ifndef __PCI_SH4_H
2#define __PCI_SH4_H 2#define __PCI_SH4_H
3 3
4#ifdef CONFIG_CPU_SUBTYPE_SH7780 4#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
5#include "pci-sh7780.h" 5#include "pci-sh7780.h"
6#else 6#else
7#include "pci-sh7751.h" 7#include "pci-sh7751.h"
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 9ddff760d3c6..1aca7fe5783b 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -12,7 +12,6 @@
12 * License. See linux/COPYING for more information. 12 * License. See linux/COPYING for more information.
13 * 13 *
14 */ 14 */
15
16#undef DEBUG 15#undef DEBUG
17 16
18#include <linux/init.h> 17#include <linux/init.h>
@@ -28,7 +27,7 @@
28 * Initialization. Try all known PCI access methods. Note that we support 27 * Initialization. Try all known PCI access methods. Note that we support
29 * using both PCI BIOS and direct access: in such cases, we use I/O ports 28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
30 * to access config space. 29 * to access config space.
31 * 30 *
32 * Note that the platform specific initialization (BSC registers, and memory 31 * Note that the platform specific initialization (BSC registers, and memory
33 * space mapping) will be called via the platform defined function 32 * space mapping) will be called via the platform defined function
34 * pcibios_init_platform(). 33 * pcibios_init_platform().
@@ -115,7 +114,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
115 * Wait Cycle Control + Parity Enable + Bus Master + 114 * Wait Cycle Control + Parity Enable + Bus Master +
116 * Mem space enable 115 * Mem space enable
117 */ 116 */
118 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 117 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
119 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 118 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
120 pci_write_reg(word, SH7751_PCICONF1); 119 pci_write_reg(word, SH7751_PCICONF1);
121 120
@@ -123,10 +122,10 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
123 word = PCI_BASE_CLASS_BRIDGE << 24; 122 word = PCI_BASE_CLASS_BRIDGE << 24;
124 pci_write_reg(word, SH7751_PCICONF2); 123 pci_write_reg(word, SH7751_PCICONF2);
125 124
126 /* Set IO and Mem windows to local address 125 /* Set IO and Mem windows to local address
127 * Make PCI and local address the same for easy 1 to 1 mapping 126 * Make PCI and local address the same for easy 1 to 1 mapping
128 * Window0 = map->window0.size @ non-cached area base = SDRAM 127 * Window0 = map->window0.size @ non-cached area base = SDRAM
129 * Window1 = map->window1.size @ cached area base = SDRAM 128 * Window1 = map->window1.size @ cached area base = SDRAM
130 */ 129 */
131 word = map->window0.size - 1; 130 word = map->window0.size - 1;
132 pci_write_reg(word, SH4_PCILSR0); 131 pci_write_reg(word, SH4_PCILSR0);
@@ -175,7 +174,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
175 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break; 174 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
176 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break; 175 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
177 } 176 }
178 177
179 if (!word) 178 if (!word)
180 return 0; 179 return 0;
181 180
@@ -194,9 +193,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
194 * DMA interrupts... 193 * DMA interrupts...
195 */ 194 */
196 195
197#ifdef CONFIG_SH_RTS7751R2D
198 pci_fixup_pcic(); 196 pci_fixup_pcic();
199#endif
200 197
201 /* SH7751 init done, set central function init complete */ 198 /* SH7751 init done, set central function init complete */
202 /* use round robin mode to stop a device starving/overruning */ 199 /* use round robin mode to stop a device starving/overruning */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 602b644c35ad..5508e45d4838 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -48,7 +48,7 @@
48static int __init sh7780_pci_init(void) 48static int __init sh7780_pci_init(void)
49{ 49{
50 unsigned int id; 50 unsigned int id;
51 int ret; 51 int ret, match = 0;
52 52
53 pr_debug("PCI: Starting intialization.\n"); 53 pr_debug("PCI: Starting intialization.\n");
54 54
@@ -56,19 +56,43 @@ static int __init sh7780_pci_init(void)
56 56
57 /* check for SH7780/SH7780R hardware */ 57 /* check for SH7780/SH7780R hardware */
58 id = pci_read_reg(SH7780_PCIVID); 58 id = pci_read_reg(SH7780_PCIVID);
59 if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) && 59 if ((id & 0xffff) == SH7780_VENDOR_ID) {
60 (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) { 60 switch ((id >> 16) & 0xffff) {
61 case SH7780_DEVICE_ID:
62 case SH7781_DEVICE_ID:
63 case SH7785_DEVICE_ID:
64 match = 1;
65 break;
66 }
67 }
68
69 if (unlikely(!match)) {
61 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); 70 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
62 return -ENODEV; 71 return -ENODEV;
63 } 72 }
64 73
65 /* Setup the INTC */ 74 /* Setup the INTC */
66 ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */ 75 if (mach_is_7780se()) {
67 ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */ 76 /* ICR0: IRL=use separately */
68 ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */ 77 ctrl_outl(0x00C00020, INTC_ICR0);
69 ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */ 78 /* ICR1: detect low level(for 2ndcut) */
70 ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */ 79 ctrl_outl(0xAAAA0000, INTC_ICR1);
71 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */ 80 /* INTPRI: priority=3(all) */
81 ctrl_outl(0x33333333, INTC_INTPRI);
82 } else {
83 /* INTC SH-4 Mode */
84 ctrl_outl(0x00200000, INTC_ICR0);
85 /* enable PCIINTA - PCIINTD */
86 ctrl_outl(0x00078000, INTC_INT2MSKCR);
87 /* disable IRL4-7 Interrupt */
88 ctrl_outl(0x40000000, INTC_INTMSK1);
89 /* disable IRL4-7 Interrupt */
90 ctrl_outl(0x0000fffe, INTC_INTMSK2);
91 /* enable IRL0-3 Interrupt */
92 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
93 /* enable IRL0-3 Interrupt */
94 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
95 }
72 96
73 if ((ret = sh4_pci_check_direct()) != 0) 97 if ((ret = sh4_pci_check_direct()) != 0)
74 return ret; 98 return ret;
@@ -138,9 +162,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
138 * DMA interrupts... 162 * DMA interrupts...
139 */ 163 */
140 164
141#ifdef CONFIG_SH_R7780RP 165 /* Apply any last-minute PCIC fixups */
142 pci_fixup_pcic(); 166 pci_fixup_pcic();
143#endif
144 167
145 /* SH7780 init done, set central function init complete */ 168 /* SH7780 init done, set central function init complete */
146 /* use round robin mode to stop a device starving/overruning */ 169 /* use round robin mode to stop a device starving/overruning */
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index f02d2180a4bc..00d12d0f8c1f 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -14,8 +14,9 @@
14 14
15/* Platform Specific Values */ 15/* Platform Specific Values */
16#define SH7780_VENDOR_ID 0x1912 16#define SH7780_VENDOR_ID 0x1912
17#define SH7780_DEVICE_ID 0x0002
18#define SH7781_DEVICE_ID 0x0001 17#define SH7781_DEVICE_ID 0x0001
18#define SH7780_DEVICE_ID 0x0002
19#define SH7785_DEVICE_ID 0x0007
19 20
20/* SH7780 Control Registers */ 21/* SH7780 Control Registers */
21#define SH7780_PCI_VCR0 0xFE000000 22#define SH7780_PCI_VCR0 0xFE000000
@@ -65,6 +66,22 @@
65#define SH7780_PCIPMCSR_BSE 0x046 66#define SH7780_PCIPMCSR_BSE 0x046
66#define SH7780_PCICDD 0x047 67#define SH7780_PCICDD 0x047
67 68
69#define SH7780_PCICR 0x100 /* PCI Control Register */
70#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
71#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
72#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
73#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
74#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
75#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
76#define SH7780_PCIAIR 0x11C /* Error Address Register */
77#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
78#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
79#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
80#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
81#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
82#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
83#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
84
68#define SH7780_PCIMBR0 0x1E0 85#define SH7780_PCIMBR0 0x1E0
69#define SH7780_PCIMBMR0 0x1E4 86#define SH7780_PCIMBMR0 0x1E4
70#define SH7780_PCIMBR2 0x1F0 87#define SH7780_PCIMBR2 0x1F0
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 09:35:26 -0500