diff options
Diffstat (limited to 'arch/sh/drivers/pci/pcie-sh7786.h')
| -rw-r--r-- | arch/sh/drivers/pci/pcie-sh7786.h | 36 |
1 files changed, 8 insertions, 28 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h index 6666ea29cba8..90a6992576b0 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.h +++ b/arch/sh/drivers/pci/pcie-sh7786.h | |||
| @@ -312,23 +312,23 @@ | |||
| 312 | #define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */ | 312 | #define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */ |
| 313 | #define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */ | 313 | #define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */ |
| 314 | 314 | ||
| 315 | /* PCIEPARL0 */ | 315 | /* PCIEPARL */ |
| 316 | #define SH4A_PCIEPARL0 (0x020400) /* R/W R/W 0x0000 0000 32 */ | 316 | #define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */ |
| 317 | #define BITS_PAL (18) | 317 | #define BITS_PAL (18) |
| 318 | #define MASK_PAL (0x3fff<<BITS_PAL) | 318 | #define MASK_PAL (0x3fff<<BITS_PAL) |
| 319 | 319 | ||
| 320 | /* PCIEPARH0 */ | 320 | /* PCIEPARH */ |
| 321 | #define SH4A_PCIEPARH0 (0x020404) /* R/W R/W 0x0000 0000 32 */ | 321 | #define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */ |
| 322 | #define BITS_PAH (0) | 322 | #define BITS_PAH (0) |
| 323 | #define MASK_PAH (0xffffffff<<BITS_PAH) | 323 | #define MASK_PAH (0xffffffff<<BITS_PAH) |
| 324 | 324 | ||
| 325 | /* PCIEPAMR0 */ | 325 | /* PCIEPAMR */ |
| 326 | #define SH4A_PCIEPAMR0 (0x020408) /* R/W R/W 0x0000 0000 32 */ | 326 | #define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */ |
| 327 | #define BITS_PAM (18) | 327 | #define BITS_PAM (18) |
| 328 | #define MASK_PAM (0x3fff<<BITS_PAM) | 328 | #define MASK_PAM (0x3fff<<BITS_PAM) |
| 329 | 329 | ||
| 330 | /* PCIEPTCTLR0 */ | 330 | /* PCIEPTCTLR */ |
| 331 | #define SH4A_PCIEPTCTLR0 (0x02040C) /* R/W R/W 0x0000 0000 32 */ | 331 | #define SH4A_PCIEPTCTLR(x) (0x02040C + ((x) * 0x20)) |
| 332 | #define BITS_PARE (31) | 332 | #define BITS_PARE (31) |
| 333 | #define MASK_PARE (0x1<<BITS_PARE) | 333 | #define MASK_PARE (0x1<<BITS_PARE) |
| 334 | #define BITS_TC (20) | 334 | #define BITS_TC (20) |
| @@ -340,26 +340,6 @@ | |||
| 340 | #define BITS_SPC (8) | 340 | #define BITS_SPC (8) |
| 341 | #define MASK_SPC (0x1<<BITS_SPC) | 341 | #define MASK_SPC (0x1<<BITS_SPC) |
| 342 | 342 | ||
| 343 | #define SH4A_PCIEPARL1 (0x020420) /* R/W R/W 0x0000 0000 32 */ | ||
| 344 | #define SH4A_PCIEPARH1 (0x020424) /* R/W R/W 0x0000 0000 32 */ | ||
| 345 | #define SH4A_PCIEPAMR1 (0x020428) /* R/W R/W 0x0000 0000 32 */ | ||
| 346 | #define SH4A_PCIEPTCTLR1 (0x02042C) /* R/W R/W 0x0000 0000 32 */ | ||
| 347 | #define SH4A_PCIEPARL2 (0x020440) /* R/W R/W 0x0000 0000 32 */ | ||
| 348 | #define SH4A_PCIEPARH2 (0x020444) /* R/W R/W 0x0000 0000 32 */ | ||
| 349 | #define SH4A_PCIEPAMR2 (0x020448) /* R/W R/W 0x0000 0000 32 */ | ||
| 350 | #define SH4A_PCIEPTCTLR2 (0x02044C) /* R/W R/W 0x0000 0000 32 */ | ||
| 351 | #define SH4A_PCIEPARL3 (0x020460) /* R/W R/W 0x0000 0000 32 */ | ||
| 352 | #define SH4A_PCIEPARH3 (0x020464) /* R/W R/W 0x0000 0000 32 */ | ||
| 353 | #define SH4A_PCIEPAMR3 (0x020468) /* R/W R/W 0x0000 0000 32 */ | ||
| 354 | #define SH4A_PCIEPTCTLR3 (0x02046C) /* R/W R/W 0x0000 0000 32 */ | ||
| 355 | #define SH4A_PCIEPARL4 (0x020480) /* R/W R/W 0x0000 0000 32 */ | ||
| 356 | #define SH4A_PCIEPARH4 (0x020484) /* R/W R/W 0x0000 0000 32 */ | ||
| 357 | #define SH4A_PCIEPAMR4 (0x020488) /* R/W R/W 0x0000 0000 32 */ | ||
| 358 | #define SH4A_PCIEPTCTLR4 (0x02048C) /* R/W R/W 0x0000 0000 32 */ | ||
| 359 | #define SH4A_PCIEPARL5 (0x0204A0) /* R/W R/W 0x0000 0000 32 */ | ||
| 360 | #define SH4A_PCIEPARH5 (0x0204A4) /* R/W R/W 0x0000 0000 32 */ | ||
| 361 | #define SH4A_PCIEPAMR5 (0x0204A8) /* R/W R/W 0x0000 0000 32 */ | ||
| 362 | #define SH4A_PCIEPTCTLR5 (0x0204AC) /* R/W R/W 0x0000 0000 32 */ | ||
| 363 | #define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */ | 343 | #define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */ |
| 364 | #define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */ | 344 | #define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */ |
| 365 | #define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */ | 345 | #define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */ |