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-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c215
1 files changed, 99 insertions, 116 deletions
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 3065eb184f01..70c1999a0ec4 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -1,88 +1,100 @@
1/* 1/*
2 * Low-Level PCI Support for the SH7751 2 * Low-Level PCI Support for the SH7751
3 * 3 *
4 * Dustin McIntire (dustin@sensoria.com) 4 * Copyright (C) 2003 - 2009 Paul Mundt
5 * Derived from arch/i386/kernel/pci-*.c which bore the message: 5 * Copyright (C) 2001 Dustin McIntire
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 * 6 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org> 7 * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
14 */ 12 */
15#undef DEBUG
16
17#include <linux/init.h> 13#include <linux/init.h>
18#include <linux/pci.h> 14#include <linux/pci.h>
19#include <linux/types.h> 15#include <linux/types.h>
20#include <linux/errno.h> 16#include <linux/errno.h>
21#include <linux/delay.h> 17#include <linux/io.h>
22#include "pci-sh4.h" 18#include "pci-sh4.h"
23#include <asm/addrspace.h> 19#include <asm/addrspace.h>
24#include <asm/io.h>
25 20
26/* 21static int __init __area_sdram_check(struct pci_channel *chan,
27 * Initialization. Try all known PCI access methods. Note that we support 22 unsigned int area)
28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
29 * to access config space.
30 *
31 * Note that the platform specific initialization (BSC registers, and memory
32 * space mapping) will be called via the platform defined function
33 * pcibios_init_platform().
34 */
35static int __init sh7751_pci_init(void)
36{ 23{
37 unsigned int id; 24 unsigned long word;
38 int ret;
39
40 pr_debug("PCI: Starting intialization.\n");
41 25
42 /* check for SH7751/SH7751R hardware */ 26 word = __raw_readl(SH7751_BCR1);
43 id = pci_read_reg(SH7751_PCICONF0);
44 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
45 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
46 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
47 return -ENODEV;
48 }
49
50 if ((ret = sh4_pci_check_direct()) != 0)
51 return ret;
52
53 return pcibios_init_platform();
54}
55subsys_initcall(sh7751_pci_init);
56
57static int __init __area_sdram_check(unsigned int area)
58{
59 u32 word;
60
61 word = ctrl_inl(SH7751_BCR1);
62 /* check BCR for SDRAM in area */ 27 /* check BCR for SDRAM in area */
63 if (((word >> area) & 1) == 0) { 28 if (((word >> area) & 1) == 0) {
64 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", 29 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
65 area, word); 30 area, word);
66 return 0; 31 return 0;
67 } 32 }
68 pci_write_reg(word, SH4_PCIBCR1); 33 pci_write_reg(chan, word, SH4_PCIBCR1);
69 34
70 word = (u16)ctrl_inw(SH7751_BCR2); 35 word = __raw_readw(SH7751_BCR2);
71 /* check BCR2 for 32bit SDRAM interface*/ 36 /* check BCR2 for 32bit SDRAM interface*/
72 if (((word >> (area << 1)) & 0x3) != 0x3) { 37 if (((word >> (area << 1)) & 0x3) != 0x3) {
73 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", 38 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
74 area, word); 39 area, word);
75 return 0; 40 return 0;
76 } 41 }
77 pci_write_reg(word, SH4_PCIBCR2); 42 pci_write_reg(chan, word, SH4_PCIBCR2);
78 43
79 return 1; 44 return 1;
80} 45}
81 46
82int __init sh7751_pcic_init(struct sh4_pci_address_map *map) 47static struct resource sh7751_io_resource = {
48 .name = "SH7751_IO",
49 .start = SH7751_PCI_IO_BASE,
50 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
51 .flags = IORESOURCE_IO
52};
53
54static struct resource sh7751_mem_resource = {
55 .name = "SH7751_mem",
56 .start = SH7751_PCI_MEMORY_BASE,
57 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
58 .flags = IORESOURCE_MEM
59};
60
61static struct pci_channel sh7751_pci_controller = {
62 .pci_ops = &sh4_pci_ops,
63 .mem_resource = &sh7751_mem_resource,
64 .mem_offset = 0x00000000,
65 .io_resource = &sh7751_io_resource,
66 .io_offset = 0x00000000,
67 .io_map_base = SH7751_PCI_IO_BASE,
68};
69
70static struct sh4_pci_address_map sh7751_pci_map = {
71 .window0 = {
72 .base = SH7751_CS3_BASE_ADDR,
73 .size = 0x04000000,
74 },
75};
76
77static int __init sh7751_pci_init(void)
83{ 78{
84 u32 reg; 79 struct pci_channel *chan = &sh7751_pci_controller;
85 u32 word; 80 unsigned int id;
81 u32 word, reg;
82 int ret;
83
84 printk(KERN_NOTICE "PCI: Starting intialization.\n");
85
86 chan->reg_base = 0xfe200000;
87
88 /* check for SH7751/SH7751R hardware */
89 id = pci_read_reg(chan, SH7751_PCICONF0);
90 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
91 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
92 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
93 return -ENODEV;
94 }
95
96 if ((ret = sh4_pci_check_direct(chan)) != 0)
97 return ret;
86 98
87 /* Set the BCR's to enable PCI access */ 99 /* Set the BCR's to enable PCI access */
88 reg = ctrl_inl(SH7751_BCR1); 100 reg = ctrl_inl(SH7751_BCR1);
@@ -90,25 +102,10 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
90 ctrl_outl(reg, SH7751_BCR1); 102 ctrl_outl(reg, SH7751_BCR1);
91 103
92 /* Turn the clocks back on (not done in reset)*/ 104 /* Turn the clocks back on (not done in reset)*/
93 pci_write_reg(0, SH4_PCICLKR); 105 pci_write_reg(chan, 0, SH4_PCICLKR);
94 /* Clear Powerdown IRQ's (not done in reset) */ 106 /* Clear Powerdown IRQ's (not done in reset) */
95 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; 107 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
96 pci_write_reg(word, SH4_PCIPINT); 108 pci_write_reg(chan, word, SH4_PCIPINT);
97
98 /*
99 * This code is unused for some boards as it is done in the
100 * bootloader and doing it here means the MAC addresses loaded
101 * by the bootloader get lost.
102 */
103 if (!(map->flags & SH4_PCIC_NO_RESET)) {
104 /* toggle PCI reset pin */
105 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
106 pci_write_reg(word, SH4_PCICR);
107 /* Wait for a long time... not 1 sec. but long enough */
108 mdelay(100);
109 word = SH4_PCICR_PREFIX;
110 pci_write_reg(word, SH4_PCICR);
111 }
112 109
113 /* set the command/status bits to: 110 /* set the command/status bits to:
114 * Wait Cycle Control + Parity Enable + Bus Master + 111 * Wait Cycle Control + Parity Enable + Bus Master +
@@ -116,89 +113,75 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
116 */ 113 */
117 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 114 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
118 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 115 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
119 pci_write_reg(word, SH7751_PCICONF1); 116 pci_write_reg(chan, word, SH7751_PCICONF1);
120 117
121 /* define this host as the host bridge */ 118 /* define this host as the host bridge */
122 word = PCI_BASE_CLASS_BRIDGE << 24; 119 word = PCI_BASE_CLASS_BRIDGE << 24;
123 pci_write_reg(word, SH7751_PCICONF2); 120 pci_write_reg(chan, word, SH7751_PCICONF2);
124 121
125 /* Set IO and Mem windows to local address 122 /* Set IO and Mem windows to local address
126 * Make PCI and local address the same for easy 1 to 1 mapping 123 * Make PCI and local address the same for easy 1 to 1 mapping
127 * Window0 = map->window0.size @ non-cached area base = SDRAM
128 * Window1 = map->window1.size @ cached area base = SDRAM
129 */ 124 */
130 word = map->window0.size - 1; 125 word = sh7751_pci_map.window0.size - 1;
131 pci_write_reg(word, SH4_PCILSR0); 126 pci_write_reg(chan, word, SH4_PCILSR0);
132 word = map->window1.size - 1;
133 pci_write_reg(word, SH4_PCILSR1);
134 /* Set the values on window 0 PCI config registers */ 127 /* Set the values on window 0 PCI config registers */
135 word = P2SEGADDR(map->window0.base); 128 word = P2SEGADDR(sh7751_pci_map.window0.base);
136 pci_write_reg(word, SH4_PCILAR0); 129 pci_write_reg(chan, word, SH4_PCILAR0);
137 pci_write_reg(word, SH7751_PCICONF5); 130 pci_write_reg(chan, word, SH7751_PCICONF5);
138 /* Set the values on window 1 PCI config registers */
139 word = PHYSADDR(map->window1.base);
140 pci_write_reg(word, SH4_PCILAR1);
141 pci_write_reg(word, SH7751_PCICONF6);
142 131
143 /* Set the local 16MB PCI memory space window to 132 /* Set the local 16MB PCI memory space window to
144 * the lowest PCI mapped address 133 * the lowest PCI mapped address
145 */ 134 */
146 word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK; 135 word = chan->mem_resource->start & SH4_PCIMBR_MASK;
147 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 136 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
148 pci_write_reg(word , SH4_PCIMBR); 137 pci_write_reg(chan, word , SH4_PCIMBR);
149
150 /* Map IO space into PCI IO window
151 * The IO window is 64K-PCIBIOS_MIN_IO in size
152 * IO addresses will be translated to the
153 * PCI IO window base address
154 */
155 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
156 PCIBIOS_MIN_IO, (64 << 10),
157 SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
158 138
159 /* Make sure the MSB's of IO window are set to access PCI space 139 /* Make sure the MSB's of IO window are set to access PCI space
160 * correctly */ 140 * correctly */
161 word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK; 141 word = chan->io_resource->start & SH4_PCIIOBR_MASK;
162 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 142 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
163 pci_write_reg(word, SH4_PCIIOBR); 143 pci_write_reg(chan, word, SH4_PCIIOBR);
164 144
165 /* Set PCI WCRx, BCRx's, copy from BSC locations */ 145 /* Set PCI WCRx, BCRx's, copy from BSC locations */
166 146
167 /* check BCR for SDRAM in specified area */ 147 /* check BCR for SDRAM in specified area */
168 switch (map->window0.base) { 148 switch (sh7751_pci_map.window0.base) {
169 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break; 149 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
170 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break; 150 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
171 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break; 151 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
172 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break; 152 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
173 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break; 153 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
174 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break; 154 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
175 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break; 155 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
176 } 156 }
177 157
178 if (!word) 158 if (!word)
179 return 0; 159 return -1;
180 160
181 /* configure the wait control registers */ 161 /* configure the wait control registers */
182 word = ctrl_inl(SH7751_WCR1); 162 word = ctrl_inl(SH7751_WCR1);
183 pci_write_reg(word, SH4_PCIWCR1); 163 pci_write_reg(chan, word, SH4_PCIWCR1);
184 word = ctrl_inl(SH7751_WCR2); 164 word = ctrl_inl(SH7751_WCR2);
185 pci_write_reg(word, SH4_PCIWCR2); 165 pci_write_reg(chan, word, SH4_PCIWCR2);
186 word = ctrl_inl(SH7751_WCR3); 166 word = ctrl_inl(SH7751_WCR3);
187 pci_write_reg(word, SH4_PCIWCR3); 167 pci_write_reg(chan, word, SH4_PCIWCR3);
188 word = ctrl_inl(SH7751_MCR); 168 word = ctrl_inl(SH7751_MCR);
189 pci_write_reg(word, SH4_PCIMCR); 169 pci_write_reg(chan, word, SH4_PCIMCR);
190 170
191 /* NOTE: I'm ignoring the PCI error IRQs for now.. 171 /* NOTE: I'm ignoring the PCI error IRQs for now..
192 * TODO: add support for the internal error interrupts and 172 * TODO: add support for the internal error interrupts and
193 * DMA interrupts... 173 * DMA interrupts...
194 */ 174 */
195 175
196 pci_fixup_pcic(); 176 pci_fixup_pcic(chan);
197 177
198 /* SH7751 init done, set central function init complete */ 178 /* SH7751 init done, set central function init complete */
199 /* use round robin mode to stop a device starving/overruning */ 179 /* use round robin mode to stop a device starving/overruning */
200 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 180 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
201 pci_write_reg(word, SH4_PCICR); 181 pci_write_reg(chan, word, SH4_PCICR);
202 182
203 return 1; 183 register_pci_controller(chan);
184
185 return 0;
204} 186}
187arch_initcall(sh7751_pci_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 23:40:25 -0500