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path: root/arch/sh/drivers/pci/pci-sh5.c
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Diffstat (limited to 'arch/sh/drivers/pci/pci-sh5.c')
-rw-r--r--arch/sh/drivers/pci/pci-sh5.c55
1 files changed, 25 insertions, 30 deletions
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index 7a97438762c8..873ed2b44055 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -89,8 +89,21 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
89 return IRQ_NONE; 89 return IRQ_NONE;
90} 90}
91 91
92int __init sh5pci_init(unsigned long memStart, unsigned long memSize) 92static struct resource sh5_io_resource = { /* place holder */ };
93static struct resource sh5_mem_resource = { /* place holder */ };
94
95static struct pci_channel sh5pci_controller = {
96 .pci_ops = &sh5_pci_ops,
97 .mem_resource = &sh5_mem_resource,
98 .mem_offset = 0x00000000,
99 .io_resource = &sh5_io_resource,
100 .io_offset = 0x00000000,
101};
102
103static int __init sh5pci_init(void)
93{ 104{
105 unsigned long memStart = __pa(memory_start);
106 unsigned long memSize = __pa(memory_end) - memStart;
94 u32 lsr0; 107 u32 lsr0;
95 u32 uval; 108 u32 uval;
96 109
@@ -106,12 +119,12 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
106 return -EINVAL; 119 return -EINVAL;
107 } 120 }
108 121
109 pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR"); 122 pcicr_virt = (unsigned long)ioremap_nocache(SH5PCI_ICR_BASE, 1024);
110 if (!pcicr_virt) { 123 if (!pcicr_virt) {
111 panic("Unable to remap PCICR\n"); 124 panic("Unable to remap PCICR\n");
112 } 125 }
113 126
114 PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO"); 127 PCI_IO_AREA = (unsigned long)ioremap_nocache(SH5PCI_IO_BASE, 0x10000);
115 if (!PCI_IO_AREA) { 128 if (!PCI_IO_AREA) {
116 panic("Unable to remap PCIIO\n"); 129 panic("Unable to remap PCIIO\n");
117 } 130 }
@@ -197,32 +210,14 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
197 SH5PCI_WRITE(AINTM, ~0); 210 SH5PCI_WRITE(AINTM, ~0);
198 SH5PCI_WRITE(PINTM, ~0); 211 SH5PCI_WRITE(PINTM, ~0);
199 212
200 return 0; 213 sh5_io_resource.start = PCI_IO_AREA;
201} 214 sh5_io_resource.end = PCI_IO_AREA + 0x10000;
202 215
203void __devinit pcibios_fixup_bus(struct pci_bus *bus) 216 sh5_mem_resource.start = memStart;
204{ 217 sh5_mem_resource.end = memStart + memSize;
205 struct pci_dev *dev = bus->self; 218
206 int i; 219 register_pci_controller(&sh5pci_controller);
207 220
208 if (dev) { 221 return 0;
209 for (i= 0; i < 3; i++) {
210 bus->resource[i] =
211 &dev->resource[PCI_BRIDGE_RESOURCES+i];
212 bus->resource[i]->name = bus->name;
213 }
214 bus->resource[0]->flags |= IORESOURCE_IO;
215 bus->resource[1]->flags |= IORESOURCE_MEM;
216
217 /* For now, propagate host limits to the bus;
218 * we'll adjust them later. */
219 bus->resource[0]->end = 64*1024 - 1 ;
220 bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
221 bus->resource[0]->start = PCIBIOS_MIN_IO;
222 bus->resource[1]->start = PCIBIOS_MIN_MEM;
223
224 /* Turn off downstream PF memory address range by default */
225 bus->resource[2]->start = 1024*1024;
226 bus->resource[2]->end = bus->resource[2]->start - 1;
227 }
228} 222}
223arch_initcall(sh5pci_init);