diff options
Diffstat (limited to 'arch/sh/drivers/pci/ops-sh4.c')
-rw-r--r-- | arch/sh/drivers/pci/ops-sh4.c | 79 |
1 files changed, 23 insertions, 56 deletions
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c index 710a3b0306e5..78bebebdc99c 100644 --- a/arch/sh/drivers/pci/ops-sh4.c +++ b/arch/sh/drivers/pci/ops-sh4.c | |||
@@ -1,22 +1,22 @@ | |||
1 | /* | 1 | /* |
2 | * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780). | 2 | * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780). |
3 | * | 3 | * |
4 | * Copyright (C) 2002 - 2006 Paul Mundt | 4 | * Copyright (C) 2002 - 2009 Paul Mundt |
5 | * | 5 | * |
6 | * This file is subject to the terms and conditions of the GNU General Public | 6 | * This file is subject to the terms and conditions of the GNU General Public |
7 | * License v2. See the file "COPYING" in the main directory of this archive | 7 | * License v2. See the file "COPYING" in the main directory of this archive |
8 | * for more details. | 8 | * for more details. |
9 | */ | 9 | */ |
10 | #include <linux/pci.h> | 10 | #include <linux/pci.h> |
11 | #include <linux/io.h> | ||
11 | #include <asm/addrspace.h> | 12 | #include <asm/addrspace.h> |
12 | #include <asm/io.h> | ||
13 | #include "pci-sh4.h" | 13 | #include "pci-sh4.h" |
14 | 14 | ||
15 | /* | 15 | /* |
16 | * Direct access to PCI hardware... | 16 | * Direct access to PCI hardware... |
17 | */ | 17 | */ |
18 | #define CONFIG_CMD(bus, devfn, where) \ | 18 | #define CONFIG_CMD(bus, devfn, where) \ |
19 | P1SEGADDR((bus->number << 16) | (devfn << 8) | (where & ~3)) | 19 | (P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3)) |
20 | 20 | ||
21 | static DEFINE_SPINLOCK(sh4_pci_lock); | 21 | static DEFINE_SPINLOCK(sh4_pci_lock); |
22 | 22 | ||
@@ -26,6 +26,7 @@ static DEFINE_SPINLOCK(sh4_pci_lock); | |||
26 | static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, | 26 | static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, |
27 | int where, int size, u32 *val) | 27 | int where, int size, u32 *val) |
28 | { | 28 | { |
29 | struct pci_channel *chan = bus->sysdata; | ||
29 | unsigned long flags; | 30 | unsigned long flags; |
30 | u32 data; | 31 | u32 data; |
31 | 32 | ||
@@ -34,8 +35,8 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, | |||
34 | * so we must do byte alignment by hand | 35 | * so we must do byte alignment by hand |
35 | */ | 36 | */ |
36 | spin_lock_irqsave(&sh4_pci_lock, flags); | 37 | spin_lock_irqsave(&sh4_pci_lock, flags); |
37 | pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); | 38 | pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); |
38 | data = pci_read_reg(SH4_PCIPDR); | 39 | data = pci_read_reg(chan, SH4_PCIPDR); |
39 | spin_unlock_irqrestore(&sh4_pci_lock, flags); | 40 | spin_unlock_irqrestore(&sh4_pci_lock, flags); |
40 | 41 | ||
41 | switch (size) { | 42 | switch (size) { |
@@ -63,13 +64,14 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, | |||
63 | static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, | 64 | static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, |
64 | int where, int size, u32 val) | 65 | int where, int size, u32 val) |
65 | { | 66 | { |
67 | struct pci_channel *chan = bus->sysdata; | ||
66 | unsigned long flags; | 68 | unsigned long flags; |
67 | int shift; | 69 | int shift; |
68 | u32 data; | 70 | u32 data; |
69 | 71 | ||
70 | spin_lock_irqsave(&sh4_pci_lock, flags); | 72 | spin_lock_irqsave(&sh4_pci_lock, flags); |
71 | pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); | 73 | pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); |
72 | data = pci_read_reg(SH4_PCIPDR); | 74 | data = pci_read_reg(chan, SH4_PCIPDR); |
73 | spin_unlock_irqrestore(&sh4_pci_lock, flags); | 75 | spin_unlock_irqrestore(&sh4_pci_lock, flags); |
74 | 76 | ||
75 | switch (size) { | 77 | switch (size) { |
@@ -90,7 +92,7 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, | |||
90 | return PCIBIOS_FUNC_NOT_SUPPORTED; | 92 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
91 | } | 93 | } |
92 | 94 | ||
93 | pci_write_reg(data, SH4_PCIPDR); | 95 | pci_write_reg(chan, data, SH4_PCIPDR); |
94 | 96 | ||
95 | return PCIBIOS_SUCCESSFUL; | 97 | return PCIBIOS_SUCCESSFUL; |
96 | } | 98 | } |
@@ -104,66 +106,31 @@ struct pci_ops sh4_pci_ops = { | |||
104 | * Not really related to pci_ops, but it's common and not worth shoving | 106 | * Not really related to pci_ops, but it's common and not worth shoving |
105 | * somewhere else for now.. | 107 | * somewhere else for now.. |
106 | */ | 108 | */ |
107 | static unsigned int pci_probe = PCI_PROBE_CONF1; | 109 | int __init sh4_pci_check_direct(struct pci_channel *chan) |
108 | |||
109 | int __init sh4_pci_check_direct(void) | ||
110 | { | 110 | { |
111 | /* | 111 | /* |
112 | * Check if configuration works. | 112 | * Check if configuration works. |
113 | */ | 113 | */ |
114 | if (pci_probe & PCI_PROBE_CONF1) { | 114 | unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR); |
115 | unsigned int tmp = pci_read_reg(SH4_PCIPAR); | ||
116 | |||
117 | pci_write_reg(P1SEG, SH4_PCIPAR); | ||
118 | 115 | ||
119 | if (pci_read_reg(SH4_PCIPAR) == P1SEG) { | 116 | pci_write_reg(chan, P1SEG, SH4_PCIPAR); |
120 | pci_write_reg(tmp, SH4_PCIPAR); | ||
121 | printk(KERN_INFO "PCI: Using configuration type 1\n"); | ||
122 | request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1"); | ||
123 | 117 | ||
124 | return 0; | 118 | if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) { |
125 | } | 119 | pci_write_reg(chan, tmp, SH4_PCIPAR); |
126 | 120 | printk(KERN_INFO "PCI: Using configuration type 1\n"); | |
127 | pci_write_reg(tmp, SH4_PCIPAR); | 121 | request_region(chan->reg_base + SH4_PCIPAR, 8, |
122 | "PCI conf1"); | ||
123 | return 0; | ||
128 | } | 124 | } |
129 | 125 | ||
130 | pr_debug("PCI: pci_check_direct failed\n"); | 126 | pci_write_reg(chan, tmp, SH4_PCIPAR); |
131 | return -EINVAL; | ||
132 | } | ||
133 | 127 | ||
134 | /* Handle generic fixups */ | 128 | printk(KERN_ERR "PCI: %s failed\n", __func__); |
135 | static void __init pci_fixup_ide_bases(struct pci_dev *d) | ||
136 | { | ||
137 | int i; | ||
138 | 129 | ||
139 | /* | 130 | return -EINVAL; |
140 | * PCI IDE controllers use non-standard I/O port decoding, respect it. | ||
141 | */ | ||
142 | if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) | ||
143 | return; | ||
144 | pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d)); | ||
145 | for(i = 0; i < 4; i++) { | ||
146 | struct resource *r = &d->resource[i]; | ||
147 | |||
148 | if ((r->start & ~0x80) == 0x374) { | ||
149 | r->start |= 2; | ||
150 | r->end = r->start; | ||
151 | } | ||
152 | } | ||
153 | } | ||
154 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); | ||
155 | |||
156 | char * __devinit pcibios_setup(char *str) | ||
157 | { | ||
158 | if (!strcmp(str, "off")) { | ||
159 | pci_probe = 0; | ||
160 | return NULL; | ||
161 | } | ||
162 | |||
163 | return str; | ||
164 | } | 131 | } |
165 | 132 | ||
166 | int __attribute__((weak)) pci_fixup_pcic(void) | 133 | int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan) |
167 | { | 134 | { |
168 | /* Nothing to do. */ | 135 | /* Nothing to do. */ |
169 | return 0; | 136 | return 0; |