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Diffstat (limited to 'arch/sh/drivers/pci/fixups-rts7751r2d.c')
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c48
1 files changed, 36 insertions, 12 deletions
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 904bce8768d3..052b354236dc 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -1,43 +1,67 @@
1/* 1/*
2 * arch/sh/drivers/pci/fixups-rts7751r2d.c 2 * arch/sh/drivers/pci/fixups-rts7751r2d.c
3 * 3 *
4 * RTS7751R2D PCI fixups 4 * RTS7751R2D / LBOXRE2 PCI fixups
5 * 5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc. 6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 Paul Mundt 7 * Copyright (C) 2004 Paul Mundt
8 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 * 9 *
9 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 12 * for more details.
12 */ 13 */
14#include <linux/pci.h>
15#include <mach/lboxre2.h>
16#include <mach/r2d.h>
13#include "pci-sh4.h" 17#include "pci-sh4.h"
18#include <asm/machtypes.h>
14 19
15#define PCIMCR_MRSET_OFF 0xBFFFFFFF 20#define PCIMCR_MRSET_OFF 0xBFFFFFFF
16#define PCIMCR_RFSH_OFF 0xFFFFFFFB 21#define PCIMCR_RFSH_OFF 0xFFFFFFFB
17 22
18int pci_fixup_pcic(void) 23static u8 rts7751r2d_irq_tab[] __initdata = {
24 IRQ_PCI_INTA,
25 IRQ_PCI_INTB,
26 IRQ_PCI_INTC,
27 IRQ_PCI_INTD,
28};
29
30static char lboxre2_irq_tab[] __initdata = {
31 IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
32};
33
34int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
35{
36 if (mach_is_lboxre2())
37 return lboxre2_irq_tab[slot];
38 else
39 return rts7751r2d_irq_tab[slot];
40}
41
42int pci_fixup_pcic(struct pci_channel *chan)
19{ 43{
20 unsigned long bcr1, mcr; 44 unsigned long bcr1, mcr;
21 45
22 bcr1 = ctrl_inl(SH7751_BCR1); 46 bcr1 = ctrl_inl(SH7751_BCR1);
23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
24 pci_write_reg(bcr1, SH4_PCIBCR1); 48 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
25 49
26 /* Enable all interrupts, so we known what to fix */ 50 /* Enable all interrupts, so we known what to fix */
27 pci_write_reg(0x0000c3ff, SH4_PCIINTM); 51 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
28 pci_write_reg(0x0000380f, SH4_PCIAINTM); 52 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
29 53
30 pci_write_reg(0xfb900047, SH7751_PCICONF1); 54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
31 pci_write_reg(0xab000001, SH7751_PCICONF4); 55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
32 56
33 mcr = ctrl_inl(SH7751_MCR); 57 mcr = ctrl_inl(SH7751_MCR);
34 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
35 pci_write_reg(mcr, SH4_PCIMCR); 59 pci_write_reg(chan, mcr, SH4_PCIMCR);
36 60
37 pci_write_reg(0x0c000000, SH7751_PCICONF5); 61 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
38 pci_write_reg(0xd0000000, SH7751_PCICONF6); 62 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
39 pci_write_reg(0x0c000000, SH4_PCILAR0); 63 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
40 pci_write_reg(0x00000000, SH4_PCILAR1); 64 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
41 65
42 return 0; 66 return 0;
43} 67}