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path: root/arch/sh/drivers/pci/fixups-lboxre2.c
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Diffstat (limited to 'arch/sh/drivers/pci/fixups-lboxre2.c')
-rw-r--r--arch/sh/drivers/pci/fixups-lboxre2.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c
index 1c1d41255ec0..a82011d03cb0 100644
--- a/arch/sh/drivers/pci/fixups-lboxre2.c
+++ b/arch/sh/drivers/pci/fixups-lboxre2.c
@@ -9,33 +9,34 @@
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details. 10 * for more details.
11 */ 11 */
12#include <linux/pci.h>
12#include "pci-sh4.h" 13#include "pci-sh4.h"
13 14
14#define PCIMCR_MRSET_OFF 0xBFFFFFFF 15#define PCIMCR_MRSET_OFF 0xBFFFFFFF
15#define PCIMCR_RFSH_OFF 0xFFFFFFFB 16#define PCIMCR_RFSH_OFF 0xFFFFFFFB
16 17
17int pci_fixup_pcic(void) 18int pci_fixup_pcic(struct pci_channel *chan)
18{ 19{
19 unsigned long bcr1, mcr; 20 unsigned long bcr1, mcr;
20 21
21 bcr1 = ctrl_inl(SH7751_BCR1); 22 bcr1 = ctrl_inl(SH7751_BCR1);
22 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
23 pci_write_reg(bcr1, SH4_PCIBCR1); 24 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
24 25
25 /* Enable all interrupts, so we known what to fix */ 26 /* Enable all interrupts, so we known what to fix */
26 pci_write_reg(0x0000c3ff, SH4_PCIINTM); 27 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
27 pci_write_reg(0x0000380f, SH4_PCIAINTM); 28 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
28 pci_write_reg(0xfb900047, SH7751_PCICONF1); 29 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
29 pci_write_reg(0xab000001, SH7751_PCICONF4); 30 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
30 31
31 mcr = ctrl_inl(SH7751_MCR); 32 mcr = ctrl_inl(SH7751_MCR);
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 33 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
33 pci_write_reg(mcr, SH4_PCIMCR); 34 pci_write_reg(chan, mcr, SH4_PCIMCR);
34 35
35 pci_write_reg(0x0c000000, SH7751_PCICONF5); 36 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
36 pci_write_reg(0xd0000000, SH7751_PCICONF6); 37 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
37 pci_write_reg(0x0c000000, SH4_PCILAR0); 38 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
38 pci_write_reg(0x00000000, SH4_PCILAR1); 39 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
39 40
40 return 0; 41 return 0;
41} 42}