diff options
Diffstat (limited to 'arch/sh/cchips')
-rw-r--r-- | arch/sh/cchips/hd6446x/hd64465/setup.c | 47 |
1 files changed, 14 insertions, 33 deletions
diff --git a/arch/sh/cchips/hd6446x/hd64465/setup.c b/arch/sh/cchips/hd6446x/hd64465/setup.c index 5cef0db4018b..9b8820c36701 100644 --- a/arch/sh/cchips/hd6446x/hd64465/setup.c +++ b/arch/sh/cchips/hd6446x/hd64465/setup.c | |||
@@ -17,10 +17,8 @@ | |||
17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
20 | |||
21 | #include <asm/io.h> | 20 | #include <asm/io.h> |
22 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
23 | |||
24 | #include <asm/hd64465/hd64465.h> | 22 | #include <asm/hd64465/hd64465.h> |
25 | 23 | ||
26 | static void disable_hd64465_irq(unsigned int irq) | 24 | static void disable_hd64465_irq(unsigned int irq) |
@@ -28,51 +26,45 @@ static void disable_hd64465_irq(unsigned int irq) | |||
28 | unsigned short nimr; | 26 | unsigned short nimr; |
29 | unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); | 27 | unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); |
30 | 28 | ||
31 | pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask); | 29 | pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask); |
32 | nimr = inw(HD64465_REG_NIMR); | 30 | nimr = inw(HD64465_REG_NIMR); |
33 | nimr |= mask; | 31 | nimr |= mask; |
34 | outw(nimr, HD64465_REG_NIMR); | 32 | outw(nimr, HD64465_REG_NIMR); |
35 | } | 33 | } |
36 | 34 | ||
37 | |||
38 | static void enable_hd64465_irq(unsigned int irq) | 35 | static void enable_hd64465_irq(unsigned int irq) |
39 | { | 36 | { |
40 | unsigned short nimr; | 37 | unsigned short nimr; |
41 | unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); | 38 | unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); |
42 | 39 | ||
43 | pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask); | 40 | pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask); |
44 | nimr = inw(HD64465_REG_NIMR); | 41 | nimr = inw(HD64465_REG_NIMR); |
45 | nimr &= ~mask; | 42 | nimr &= ~mask; |
46 | outw(nimr, HD64465_REG_NIMR); | 43 | outw(nimr, HD64465_REG_NIMR); |
47 | } | 44 | } |
48 | 45 | ||
49 | |||
50 | static void mask_and_ack_hd64465(unsigned int irq) | 46 | static void mask_and_ack_hd64465(unsigned int irq) |
51 | { | 47 | { |
52 | disable_hd64465_irq(irq); | 48 | disable_hd64465_irq(irq); |
53 | } | 49 | } |
54 | 50 | ||
55 | |||
56 | static void end_hd64465_irq(unsigned int irq) | 51 | static void end_hd64465_irq(unsigned int irq) |
57 | { | 52 | { |
58 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | 53 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
59 | enable_hd64465_irq(irq); | 54 | enable_hd64465_irq(irq); |
60 | } | 55 | } |
61 | 56 | ||
62 | |||
63 | static unsigned int startup_hd64465_irq(unsigned int irq) | 57 | static unsigned int startup_hd64465_irq(unsigned int irq) |
64 | { | 58 | { |
65 | enable_hd64465_irq(irq); | 59 | enable_hd64465_irq(irq); |
66 | return 0; | 60 | return 0; |
67 | } | 61 | } |
68 | 62 | ||
69 | |||
70 | static void shutdown_hd64465_irq(unsigned int irq) | 63 | static void shutdown_hd64465_irq(unsigned int irq) |
71 | { | 64 | { |
72 | disable_hd64465_irq(irq); | 65 | disable_hd64465_irq(irq); |
73 | } | 66 | } |
74 | 67 | ||
75 | |||
76 | static struct hw_interrupt_type hd64465_irq_type = { | 68 | static struct hw_interrupt_type hd64465_irq_type = { |
77 | .typename = "HD64465-IRQ", | 69 | .typename = "HD64465-IRQ", |
78 | .startup = startup_hd64465_irq, | 70 | .startup = startup_hd64465_irq, |
@@ -83,7 +75,6 @@ static struct hw_interrupt_type hd64465_irq_type = { | |||
83 | .end = end_hd64465_irq, | 75 | .end = end_hd64465_irq, |
84 | }; | 76 | }; |
85 | 77 | ||
86 | |||
87 | static irqreturn_t hd64465_interrupt(int irq, void *dev_id) | 78 | static irqreturn_t hd64465_interrupt(int irq, void *dev_id) |
88 | { | 79 | { |
89 | printk(KERN_INFO | 80 | printk(KERN_INFO |
@@ -93,9 +84,6 @@ static irqreturn_t hd64465_interrupt(int irq, void *dev_id) | |||
93 | return IRQ_NONE; | 84 | return IRQ_NONE; |
94 | } | 85 | } |
95 | 86 | ||
96 | |||
97 | /*====================================================*/ | ||
98 | |||
99 | /* | 87 | /* |
100 | * Support for a secondary IRQ demux step. This is necessary | 88 | * Support for a secondary IRQ demux step. This is necessary |
101 | * because the HD64465 presents a very thin interface to the | 89 | * because the HD64465 presents a very thin interface to the |
@@ -103,8 +91,7 @@ static irqreturn_t hd64465_interrupt(int irq, void *dev_id) | |||
103 | * normally done in hardware by other PCMCIA host bridges is | 91 | * normally done in hardware by other PCMCIA host bridges is |
104 | * instead done in software. | 92 | * instead done in software. |
105 | */ | 93 | */ |
106 | static struct | 94 | static struct { |
107 | { | ||
108 | int (*func)(int, void *); | 95 | int (*func)(int, void *); |
109 | void *dev; | 96 | void *dev; |
110 | } hd64465_demux[HD64465_IRQ_NUM]; | 97 | } hd64465_demux[HD64465_IRQ_NUM]; |
@@ -112,19 +99,17 @@ static struct | |||
112 | void hd64465_register_irq_demux(int irq, | 99 | void hd64465_register_irq_demux(int irq, |
113 | int (*demux)(int irq, void *dev), void *dev) | 100 | int (*demux)(int irq, void *dev), void *dev) |
114 | { | 101 | { |
115 | hd64465_demux[irq - HD64465_IRQ_BASE].func = demux; | 102 | hd64465_demux[irq - HD64465_IRQ_BASE].func = demux; |
116 | hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev; | 103 | hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev; |
117 | } | 104 | } |
118 | EXPORT_SYMBOL(hd64465_register_irq_demux); | 105 | EXPORT_SYMBOL(hd64465_register_irq_demux); |
119 | 106 | ||
120 | void hd64465_unregister_irq_demux(int irq) | 107 | void hd64465_unregister_irq_demux(int irq) |
121 | { | 108 | { |
122 | hd64465_demux[irq - HD64465_IRQ_BASE].func = 0; | 109 | hd64465_demux[irq - HD64465_IRQ_BASE].func = 0; |
123 | } | 110 | } |
124 | EXPORT_SYMBOL(hd64465_unregister_irq_demux); | 111 | EXPORT_SYMBOL(hd64465_unregister_irq_demux); |
125 | 112 | ||
126 | |||
127 | |||
128 | int hd64465_irq_demux(int irq) | 113 | int hd64465_irq_demux(int irq) |
129 | { | 114 | { |
130 | if (irq == CONFIG_HD64465_IRQ) { | 115 | if (irq == CONFIG_HD64465_IRQ) { |
@@ -132,16 +117,16 @@ int hd64465_irq_demux(int irq) | |||
132 | unsigned short nirr = inw(HD64465_REG_NIRR); | 117 | unsigned short nirr = inw(HD64465_REG_NIRR); |
133 | unsigned short nimr = inw(HD64465_REG_NIMR); | 118 | unsigned short nimr = inw(HD64465_REG_NIMR); |
134 | 119 | ||
135 | pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr); | 120 | pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr); |
136 | nirr &= ~nimr; | 121 | nirr &= ~nimr; |
137 | for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++) | 122 | for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++) |
138 | if (nirr & bit) | 123 | if (nirr & bit) |
139 | break; | 124 | break; |
140 | 125 | ||
141 | if (i < HD64465_IRQ_NUM) { | 126 | if (i < HD64465_IRQ_NUM) { |
142 | irq = HD64465_IRQ_BASE + i; | 127 | irq = HD64465_IRQ_BASE + i; |
143 | if (hd64465_demux[i].func != 0) | 128 | if (hd64465_demux[i].func != 0) |
144 | irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev); | 129 | irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev); |
145 | } | 130 | } |
146 | } | 131 | } |
147 | return irq; | 132 | return irq; |
@@ -154,7 +139,6 @@ static struct irqaction irq0 = { | |||
154 | .name = "HD64465", | 139 | .name = "HD64465", |
155 | }; | 140 | }; |
156 | 141 | ||
157 | |||
158 | static int __init setup_hd64465(void) | 142 | static int __init setup_hd64465(void) |
159 | { | 143 | { |
160 | int i; | 144 | int i; |
@@ -176,8 +160,8 @@ static int __init setup_hd64465(void) | |||
176 | 160 | ||
177 | rev = inw(HD64465_REG_SRR); | 161 | rev = inw(HD64465_REG_SRR); |
178 | printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff); | 162 | printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff); |
179 | 163 | ||
180 | outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */ | 164 | outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */ |
181 | 165 | ||
182 | for (i = 0; i < HD64465_IRQ_NUM ; i++) { | 166 | for (i = 0; i < HD64465_IRQ_NUM ; i++) { |
183 | irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type; | 167 | irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type; |
@@ -185,16 +169,13 @@ static int __init setup_hd64465(void) | |||
185 | 169 | ||
186 | setup_irq(CONFIG_HD64465_IRQ, &irq0); | 170 | setup_irq(CONFIG_HD64465_IRQ, &irq0); |
187 | 171 | ||
188 | #ifdef CONFIG_SERIAL | ||
189 | /* wake up the UART from STANDBY at this point */ | 172 | /* wake up the UART from STANDBY at this point */ |
190 | smscr = inw(HD64465_REG_SMSCR); | 173 | smscr = inw(HD64465_REG_SMSCR); |
191 | outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR); | 174 | outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR); |
192 | 175 | ||
193 | /* remap IO ports for first ISA serial port to HD64465 UART */ | 176 | /* remap IO ports for first ISA serial port to HD64465 UART */ |
194 | hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1); | 177 | hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1); |
195 | #endif | ||
196 | 178 | ||
197 | return 0; | 179 | return 0; |
198 | } | 180 | } |
199 | |||
200 | module_init(setup_hd64465); | 181 | module_init(setup_hd64465); |