diff options
Diffstat (limited to 'arch/sh/cchips/hd6446x/hd64461.c')
| -rw-r--r-- | arch/sh/cchips/hd6446x/hd64461.c | 115 |
1 files changed, 25 insertions, 90 deletions
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c index f1a4a0763c59..27ceeb948bb1 100644 --- a/arch/sh/cchips/hd6446x/hd64461.c +++ b/arch/sh/cchips/hd6446x/hd64461.c | |||
| @@ -10,99 +10,49 @@ | |||
| 10 | #include <linux/interrupt.h> | 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/irq.h> | 12 | #include <linux/irq.h> |
| 13 | #include <asm/io.h> | 13 | #include <linux/io.h> |
| 14 | #include <asm/irq.h> | 14 | #include <asm/irq.h> |
| 15 | #include <asm/hd64461.h> | 15 | #include <asm/hd64461.h> |
| 16 | 16 | ||
| 17 | /* This belongs in cpu specific */ | 17 | /* This belongs in cpu specific */ |
| 18 | #define INTC_ICR1 0xA4140010UL | 18 | #define INTC_ICR1 0xA4140010UL |
| 19 | 19 | ||
| 20 | static void disable_hd64461_irq(unsigned int irq) | 20 | static void hd64461_mask_irq(unsigned int irq) |
| 21 | { | 21 | { |
| 22 | unsigned short nimr; | 22 | unsigned short nimr; |
| 23 | unsigned short mask = 1 << (irq - HD64461_IRQBASE); | 23 | unsigned short mask = 1 << (irq - HD64461_IRQBASE); |
| 24 | 24 | ||
| 25 | nimr = inw(HD64461_NIMR); | 25 | nimr = __raw_readw(HD64461_NIMR); |
| 26 | nimr |= mask; | 26 | nimr |= mask; |
| 27 | outw(nimr, HD64461_NIMR); | 27 | __raw_writew(nimr, HD64461_NIMR); |
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | static void enable_hd64461_irq(unsigned int irq) | 30 | static void hd64461_unmask_irq(unsigned int irq) |
| 31 | { | 31 | { |
| 32 | unsigned short nimr; | 32 | unsigned short nimr; |
| 33 | unsigned short mask = 1 << (irq - HD64461_IRQBASE); | 33 | unsigned short mask = 1 << (irq - HD64461_IRQBASE); |
| 34 | 34 | ||
| 35 | nimr = inw(HD64461_NIMR); | 35 | nimr = __raw_readw(HD64461_NIMR); |
| 36 | nimr &= ~mask; | 36 | nimr &= ~mask; |
| 37 | outw(nimr, HD64461_NIMR); | 37 | __raw_writew(nimr, HD64461_NIMR); |
| 38 | } | 38 | } |
| 39 | 39 | ||
| 40 | static void mask_and_ack_hd64461(unsigned int irq) | 40 | static void hd64461_mask_and_ack_irq(unsigned int irq) |
| 41 | { | 41 | { |
| 42 | disable_hd64461_irq(irq); | 42 | hd64461_mask_irq(irq); |
| 43 | #ifdef CONFIG_HD64461_ENABLER | 43 | #ifdef CONFIG_HD64461_ENABLER |
| 44 | if (irq == HD64461_IRQBASE + 13) | 44 | if (irq == HD64461_IRQBASE + 13) |
| 45 | outb(0x00, HD64461_PCC1CSCR); | 45 | __raw_writeb(0x00, HD64461_PCC1CSCR); |
| 46 | #endif | 46 | #endif |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | static void end_hd64461_irq(unsigned int irq) | 49 | static struct irq_chip hd64461_irq_chip = { |
| 50 | { | 50 | .name = "HD64461-IRQ", |
| 51 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | 51 | .mask = hd64461_mask_irq, |
| 52 | enable_hd64461_irq(irq); | 52 | .mask_ack = hd64461_mask_and_ack_irq, |
| 53 | } | 53 | .unmask = hd64461_unmask_irq, |
| 54 | |||
| 55 | static unsigned int startup_hd64461_irq(unsigned int irq) | ||
| 56 | { | ||
| 57 | enable_hd64461_irq(irq); | ||
| 58 | return 0; | ||
| 59 | } | ||
| 60 | |||
| 61 | static void shutdown_hd64461_irq(unsigned int irq) | ||
| 62 | { | ||
| 63 | disable_hd64461_irq(irq); | ||
| 64 | } | ||
| 65 | |||
| 66 | static struct hw_interrupt_type hd64461_irq_type = { | ||
| 67 | .typename = "HD64461-IRQ", | ||
| 68 | .startup = startup_hd64461_irq, | ||
| 69 | .shutdown = shutdown_hd64461_irq, | ||
| 70 | .enable = enable_hd64461_irq, | ||
| 71 | .disable = disable_hd64461_irq, | ||
| 72 | .ack = mask_and_ack_hd64461, | ||
| 73 | .end = end_hd64461_irq, | ||
| 74 | }; | 54 | }; |
| 75 | 55 | ||
| 76 | static irqreturn_t hd64461_interrupt(int irq, void *dev_id) | ||
| 77 | { | ||
| 78 | printk(KERN_INFO | ||
| 79 | "HD64461: spurious interrupt, nirr: 0x%x nimr: 0x%x\n", | ||
| 80 | inw(HD64461_NIRR), inw(HD64461_NIMR)); | ||
| 81 | |||
| 82 | return IRQ_NONE; | ||
| 83 | } | ||
| 84 | |||
| 85 | static struct { | ||
| 86 | int (*func) (int, void *); | ||
| 87 | void *dev; | ||
| 88 | } hd64461_demux[HD64461_IRQ_NUM]; | ||
| 89 | |||
| 90 | void hd64461_register_irq_demux(int irq, | ||
| 91 | int (*demux) (int irq, void *dev), void *dev) | ||
| 92 | { | ||
| 93 | hd64461_demux[irq - HD64461_IRQBASE].func = demux; | ||
| 94 | hd64461_demux[irq - HD64461_IRQBASE].dev = dev; | ||
| 95 | } | ||
| 96 | |||
| 97 | EXPORT_SYMBOL(hd64461_register_irq_demux); | ||
| 98 | |||
| 99 | void hd64461_unregister_irq_demux(int irq) | ||
| 100 | { | ||
| 101 | hd64461_demux[irq - HD64461_IRQBASE].func = 0; | ||
| 102 | } | ||
| 103 | |||
| 104 | EXPORT_SYMBOL(hd64461_unregister_irq_demux); | ||
| 105 | |||
| 106 | int hd64461_irq_demux(int irq) | 56 | int hd64461_irq_demux(int irq) |
| 107 | { | 57 | { |
| 108 | if (irq == CONFIG_HD64461_IRQ) { | 58 | if (irq == CONFIG_HD64461_IRQ) { |
| @@ -115,25 +65,11 @@ int hd64461_irq_demux(int irq) | |||
| 115 | for (bit = 1, i = 0; i < 16; bit <<= 1, i++) | 65 | for (bit = 1, i = 0; i < 16; bit <<= 1, i++) |
| 116 | if (nirr & bit) | 66 | if (nirr & bit) |
| 117 | break; | 67 | break; |
| 118 | if (i == 16) | 68 | irq = HD64461_IRQBASE + i; |
| 119 | irq = CONFIG_HD64461_IRQ; | ||
| 120 | else { | ||
| 121 | irq = HD64461_IRQBASE + i; | ||
| 122 | if (hd64461_demux[i].func != 0) { | ||
| 123 | irq = hd64461_demux[i].func(irq, hd64461_demux[i].dev); | ||
| 124 | } | ||
| 125 | } | ||
| 126 | } | 69 | } |
| 127 | return irq; | 70 | return irq; |
| 128 | } | 71 | } |
| 129 | 72 | ||
| 130 | static struct irqaction irq0 = { | ||
| 131 | .handler = hd64461_interrupt, | ||
| 132 | .flags = IRQF_DISABLED, | ||
| 133 | .mask = CPU_MASK_NONE, | ||
| 134 | .name = "HD64461", | ||
| 135 | }; | ||
| 136 | |||
| 137 | int __init setup_hd64461(void) | 73 | int __init setup_hd64461(void) |
| 138 | { | 74 | { |
| 139 | int i; | 75 | int i; |
| @@ -146,22 +82,21 @@ int __init setup_hd64461(void) | |||
| 146 | CONFIG_HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE, | 82 | CONFIG_HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE, |
| 147 | HD64461_IRQBASE + 15); | 83 | HD64461_IRQBASE + 15); |
| 148 | 84 | ||
| 149 | #if defined(CONFIG_CPU_SUBTYPE_SH7709) /* Should be at processor specific part.. */ | 85 | /* Should be at processor specific part.. */ |
| 150 | outw(0x2240, INTC_ICR1); | 86 | #if defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 87 | __raw_writew(0x2240, INTC_ICR1); | ||
| 151 | #endif | 88 | #endif |
| 152 | outw(0xffff, HD64461_NIMR); | 89 | __raw_writew(0xffff, HD64461_NIMR); |
| 153 | 90 | ||
| 154 | /* IRQ 80 -> 95 belongs to HD64461 */ | 91 | /* IRQ 80 -> 95 belongs to HD64461 */ |
| 155 | for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) { | 92 | for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) |
| 156 | irq_desc[i].chip = &hd64461_irq_type; | 93 | set_irq_chip_and_handler(i, &hd64461_irq_chip, |
| 157 | } | 94 | handle_level_irq); |
| 158 | |||
| 159 | setup_irq(CONFIG_HD64461_IRQ, &irq0); | ||
| 160 | 95 | ||
| 161 | #ifdef CONFIG_HD64461_ENABLER | 96 | #ifdef CONFIG_HD64461_ENABLER |
| 162 | printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); | 97 | printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); |
| 163 | outb(0x4c, HD64461_PCC1CSCIER); | 98 | __raw_writeb(0x4c, HD64461_PCC1CSCIER); |
| 164 | outb(0x00, HD64461_PCC1CSCR); | 99 | __raw_writeb(0x00, HD64461_PCC1CSCR); |
| 165 | #endif | 100 | #endif |
| 166 | 101 | ||
| 167 | return 0; | 102 | return 0; |
