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-rw-r--r--arch/sh/boards/Kconfig15
-rw-r--r--arch/sh/boards/board-ap325rxa.c12
-rw-r--r--arch/sh/boards/board-sh7785lcr.c44
-rw-r--r--arch/sh/boards/mach-cayman/Makefile2
-rw-r--r--arch/sh/boards/mach-cayman/irq.c17
-rw-r--r--arch/sh/boards/mach-cayman/panic.c49
-rw-r--r--arch/sh/boards/mach-cayman/setup.c2
-rw-r--r--arch/sh/boards/mach-dreamcast/setup.c6
-rw-r--r--arch/sh/boards/mach-migor/setup.c19
-rw-r--r--arch/sh/boards/mach-r2d/setup.c50
-rw-r--r--arch/sh/boards/mach-se/7724/Makefile10
-rw-r--r--arch/sh/boards/mach-se/7724/irq.c139
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c448
-rw-r--r--arch/sh/boards/mach-se/7751/Makefile2
-rw-r--r--arch/sh/boards/mach-se/7751/io.c16
-rw-r--r--arch/sh/boards/mach-se/7751/pci.c147
-rw-r--r--arch/sh/boards/mach-se/7780/irq.c27
-rw-r--r--arch/sh/boards/mach-se/Makefile1
-rw-r--r--arch/sh/boards/mach-sh03/rtc.c10
-rw-r--r--arch/sh/boards/mach-snapgear/io.c16
-rw-r--r--arch/sh/boards/mach-systemh/io.c16
-rw-r--r--arch/sh/boards/mach-titan/io.c20
22 files changed, 816 insertions, 252 deletions
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index dcc1af8a2cfe..1c91b1f565d5 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -46,6 +46,15 @@ config SH_7722_SOLUTION_ENGINE
46 Select 7722 SolutionEngine if configuring for a Hitachi SH772 46 Select 7722 SolutionEngine if configuring for a Hitachi SH772
47 evaluation board. 47 evaluation board.
48 48
49config SH_7724_SOLUTION_ENGINE
50 bool "SolutionEngine7724"
51 select SOLUTION_ENGINE
52 depends on CPU_SUBTYPE_SH7724
53 select ARCH_REQUIRE_GPIOLIB
54 help
55 Select 7724 SolutionEngine if configuring for a Hitachi SH7724
56 evaluation board.
57
49config SH_7751_SOLUTION_ENGINE 58config SH_7751_SOLUTION_ENGINE
50 bool "SolutionEngine7751" 59 bool "SolutionEngine7751"
51 select SOLUTION_ENGINE 60 select SOLUTION_ENGINE
@@ -121,7 +130,7 @@ config SH_RTS7751R2D
121 bool "RTS7751R2D" 130 bool "RTS7751R2D"
122 depends on CPU_SUBTYPE_SH7751R 131 depends on CPU_SUBTYPE_SH7751R
123 select SYS_SUPPORTS_PCI 132 select SYS_SUPPORTS_PCI
124 select IO_TRAPPED 133 select IO_TRAPPED if MMU
125 help 134 help
126 Select RTS7751R2D if configuring for a Renesas Technology 135 Select RTS7751R2D if configuring for a Renesas Technology
127 Sales SH-Graphics board. 136 Sales SH-Graphics board.
@@ -145,13 +154,13 @@ config SH_HIGHLANDER
145 bool "Highlander" 154 bool "Highlander"
146 depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 155 depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
147 select SYS_SUPPORTS_PCI 156 select SYS_SUPPORTS_PCI
148 select IO_TRAPPED 157 select IO_TRAPPED if MMU
149 158
150config SH_SH7785LCR 159config SH_SH7785LCR
151 bool "SH7785LCR" 160 bool "SH7785LCR"
152 depends on CPU_SUBTYPE_SH7785 161 depends on CPU_SUBTYPE_SH7785
153 select SYS_SUPPORTS_PCI 162 select SYS_SUPPORTS_PCI
154 select IO_TRAPPED 163 select IO_TRAPPED if MMU
155 164
156config SH_SH7785LCR_29BIT_PHYSMAPS 165config SH_SH7785LCR_29BIT_PHYSMAPS
157 bool "SH7785LCR 29bit physmaps" 166 bool "SH7785LCR 29bit physmaps"
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index f2a29641b6a3..1c4d83ef2a47 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -535,6 +535,18 @@ static int __init ap325rxa_devices_setup(void)
535} 535}
536device_initcall(ap325rxa_devices_setup); 536device_initcall(ap325rxa_devices_setup);
537 537
538/* Return the board specific boot mode pin configuration */
539static int ap325rxa_mode_pins(void)
540{
541 /* MD0=0, MD1=0, MD2=0: Clock Mode 0
542 * MD3=0: 16-bit Area0 Bus Width
543 * MD5=1: Little Endian
544 * TSTMD=1, MD8=1: Test Mode Disabled
545 */
546 return MODE_PIN5 | MODE_PIN8;
547}
548
538static struct sh_machine_vector mv_ap325rxa __initmv = { 549static struct sh_machine_vector mv_ap325rxa __initmv = {
539 .mv_name = "AP-325RXA", 550 .mv_name = "AP-325RXA",
551 .mv_mode_pins = ap325rxa_mode_pins,
540}; 552};
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 6f94f17adc46..7be56fb06c1f 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -2,12 +2,12 @@
2 * Renesas Technology Corp. R0P7785LC0011RL Support. 2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda 4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 9 * for more details.
9 */ 10 */
10
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/sm501.h> 13#include <linux/sm501.h>
@@ -19,8 +19,12 @@
19#include <linux/i2c-pca-platform.h> 19#include <linux/i2c-pca-platform.h>
20#include <linux/i2c-algo-pca.h> 20#include <linux/i2c-algo-pca.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <asm/heartbeat.h> 22#include <linux/clk.h>
23#include <linux/errno.h>
23#include <mach/sh7785lcr.h> 24#include <mach/sh7785lcr.h>
25#include <asm/heartbeat.h>
26#include <asm/clock.h>
27#include <cpu/sh7785.h>
24 28
25/* 29/*
26 * NOTE: This board has 2 physical memory maps. 30 * NOTE: This board has 2 physical memory maps.
@@ -273,6 +277,20 @@ void __init init_sh7785lcr_IRQ(void)
273 plat_irq_setup_pins(IRQ_MODE_IRQ3210); 277 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
274} 278}
275 279
280static int sh7785lcr_clk_init(void)
281{
282 struct clk *clk;
283 int ret;
284
285 clk = clk_get(NULL, "extal");
286 if (!clk || IS_ERR(clk))
287 return PTR_ERR(clk);
288 ret = clk_set_rate(clk, 33333333);
289 clk_put(clk);
290
291 return ret;
292}
293
276static void sh7785lcr_power_off(void) 294static void sh7785lcr_power_off(void)
277{ 295{
278 unsigned char *p; 296 unsigned char *p;
@@ -303,12 +321,34 @@ static void __init sh7785lcr_setup(char **cmdline_p)
303 writel(0x000307c2, sm501_reg); 321 writel(0x000307c2, sm501_reg);
304} 322}
305 323
324/* Return the board specific boot mode pin configuration */
325static int sh7785lcr_mode_pins(void)
326{
327 int value = 0;
328
329 /* These are the factory default settings of S1 and S2.
330 * If you change these dip switches then you will need to
331 * adjust the values below as well.
332 */
333 value |= MODE_PIN4; /* Clock Mode 16 */
334 value |= MODE_PIN5; /* 32-bit Area0 bus width */
335 value |= MODE_PIN6; /* 32-bit Area0 bus width */
336 value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
337 value |= MODE_PIN8; /* Little Endian */
338 value |= MODE_PIN9; /* Master Mode */
339 value |= MODE_PIN14; /* No PLL step-up */
340
341 return value;
342}
343
306/* 344/*
307 * The Machine Vector 345 * The Machine Vector
308 */ 346 */
309static struct sh_machine_vector mv_sh7785lcr __initmv = { 347static struct sh_machine_vector mv_sh7785lcr __initmv = {
310 .mv_name = "SH7785LCR", 348 .mv_name = "SH7785LCR",
311 .mv_setup = sh7785lcr_setup, 349 .mv_setup = sh7785lcr_setup,
350 .mv_clk_init = sh7785lcr_clk_init,
312 .mv_init_irq = init_sh7785lcr_IRQ, 351 .mv_init_irq = init_sh7785lcr_IRQ,
352 .mv_mode_pins = sh7785lcr_mode_pins,
313}; 353};
314 354
diff --git a/arch/sh/boards/mach-cayman/Makefile b/arch/sh/boards/mach-cayman/Makefile
index cafe1ac3b29c..00fa3eaecb1b 100644
--- a/arch/sh/boards/mach-cayman/Makefile
+++ b/arch/sh/boards/mach-cayman/Makefile
@@ -1,4 +1,4 @@
1# 1#
2# Makefile for the Hitachi Cayman specific parts of the kernel 2# Makefile for the Hitachi Cayman specific parts of the kernel
3# 3#
4obj-y := setup.o irq.o 4obj-y := setup.o irq.o panic.o
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index da62ad516994..33f770856319 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -142,26 +142,11 @@ int cayman_irq_demux(int evt)
142 return irq; 142 return irq;
143} 143}
144 144
145#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
146int cayman_irq_describe(char* p, int irq)
147{
148 if (irq < NR_INTC_IRQS) {
149 return intc_irq_describe(p, irq);
150 } else if (irq < NR_INTC_IRQS + 8) {
151 return sprintf(p, "(SMSC %d)", irq - NR_INTC_IRQS);
152 } else if ((irq >= NR_INTC_IRQS + 24) && (irq < NR_INTC_IRQS + 32)) {
153 return sprintf(p, "(PCI2 %d)", irq - (NR_INTC_IRQS + 24));
154 }
155
156 return 0;
157}
158#endif
159
160void init_cayman_irq(void) 145void init_cayman_irq(void)
161{ 146{
162 int i; 147 int i;
163 148
164 epld_virt = onchip_remap(EPLD_BASE, 1024, "EPLD"); 149 epld_virt = (unsigned long)ioremap_nocache(EPLD_BASE, 1024);
165 if (!epld_virt) { 150 if (!epld_virt) {
166 printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n"); 151 printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n");
167 return; 152 return;
diff --git a/arch/sh/boards/mach-cayman/panic.c b/arch/sh/boards/mach-cayman/panic.c
new file mode 100644
index 000000000000..d1e67306d07c
--- /dev/null
+++ b/arch/sh/boards/mach-cayman/panic.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright (C) 2003 Richard Curnow, SuperH UK Limited
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8
9#include <linux/kernel.h>
10#include <linux/io.h>
11#include <cpu/registers.h>
12
13/* THIS IS A PHYSICAL ADDRESS */
14#define HDSP2534_ADDR (0x04002100)
15
16static void poor_mans_delay(void)
17{
18 int i;
19
20 for (i = 0; i < 2500000; i++)
21 cpu_relax();
22}
23
24static void show_value(unsigned long x)
25{
26 int i;
27 unsigned nibble;
28 for (i = 0; i < 8; i++) {
29 nibble = ((x >> (i * 4)) & 0xf);
30
31 __raw_writeb(nibble + ((nibble > 9) ? 55 : 48),
32 HDSP2534_ADDR + 0xe0 + ((7 - i) << 2));
33 }
34}
35
36void
37panic_handler(unsigned long panicPC, unsigned long panicSSR,
38 unsigned long panicEXPEVT)
39{
40 while (1) {
41 /* This piece of code displays the PC on the LED display */
42 show_value(panicPC);
43 poor_mans_delay();
44 show_value(panicSSR);
45 poor_mans_delay();
46 show_value(panicEXPEVT);
47 poor_mans_delay();
48 }
49}
diff --git a/arch/sh/boards/mach-cayman/setup.c b/arch/sh/boards/mach-cayman/setup.c
index e7f9cc5f2ff1..7e8216ac31bd 100644
--- a/arch/sh/boards/mach-cayman/setup.c
+++ b/arch/sh/boards/mach-cayman/setup.c
@@ -102,7 +102,7 @@ static int __init smsc_superio_setup(void)
102{ 102{
103 unsigned char devid, devrev; 103 unsigned char devid, devrev;
104 104
105 smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO"); 105 smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
106 if (!smsc_superio_virt) { 106 if (!smsc_superio_virt) {
107 panic("Unable to remap SMSC SuperIO\n"); 107 panic("Unable to remap SMSC SuperIO\n");
108 } 108 }
diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c
index d1bee4884cd6..ebe99227d4e6 100644
--- a/arch/sh/boards/mach-dreamcast/setup.c
+++ b/arch/sh/boards/mach-dreamcast/setup.c
@@ -30,7 +30,6 @@
30 30
31extern struct irq_chip systemasic_int; 31extern struct irq_chip systemasic_int;
32extern void aica_time_init(void); 32extern void aica_time_init(void);
33extern int gapspci_init(void);
34extern int systemasic_irq_demux(int); 33extern int systemasic_irq_demux(int);
35 34
36static void __init dreamcast_setup(char **cmdline_p) 35static void __init dreamcast_setup(char **cmdline_p)
@@ -51,11 +50,6 @@ static void __init dreamcast_setup(char **cmdline_p)
51 handle_level_irq); 50 handle_level_irq);
52 51
53 board_time_init = aica_time_init; 52 board_time_init = aica_time_init;
54
55#ifdef CONFIG_PCI
56 if (gapspci_init() < 0)
57 printk(KERN_WARNING "GAPSPCI was not detected.\n");
58#endif
59} 53}
60 54
61static struct sh_machine_vector mv_dreamcast __initmv = { 55static struct sh_machine_vector mv_dreamcast __initmv = {
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 1ee1de0bc1c3..6ed401cd3156 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -584,3 +584,22 @@ static int __init migor_devices_setup(void)
584 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); 584 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
585} 585}
586__initcall(migor_devices_setup); 586__initcall(migor_devices_setup);
587
588/* Return the board specific boot mode pin configuration */
589static int migor_mode_pins(void)
590{
591 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
592 * MD3=0: 16-bit Area0 Bus Width
593 * MD5=1: Little Endian
594 * TSTMD=1, MD8=0: Test Mode Disabled
595 */
596 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
597}
598
599/*
600 * The Machine Vector
601 */
602static struct sh_machine_vector mv_migor __initmv = {
603 .mv_name = "Migo-R",
604 .mv_mode_pins = migor_mode_pins,
605};
diff --git a/arch/sh/boards/mach-r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index c585be00956e..a625ecb93e47 100644
--- a/arch/sh/boards/mach-r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
@@ -10,6 +10,9 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15#include <linux/mtd/physmap.h>
13#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
14#include <linux/sm501.h> 17#include <linux/sm501.h>
15#include <linux/sm501-regs.h> 18#include <linux/sm501-regs.h>
@@ -181,6 +184,50 @@ static struct platform_device sm501_device = {
181 .resource = sm501_resources, 184 .resource = sm501_resources,
182}; 185};
183 186
187static struct mtd_partition r2d_partitions[] = {
188 {
189 .name = "U-Boot",
190 .offset = 0x00000000,
191 .size = 0x00040000,
192 .mask_flags = MTD_WRITEABLE,
193 }, {
194 .name = "Environment",
195 .offset = MTDPART_OFS_NXTBLK,
196 .size = 0x00040000,
197 .mask_flags = MTD_WRITEABLE,
198 }, {
199 .name = "Kernel",
200 .offset = MTDPART_OFS_NXTBLK,
201 .size = 0x001c0000,
202 }, {
203 .name = "Flash_FS",
204 .offset = MTDPART_OFS_NXTBLK,
205 .size = MTDPART_SIZ_FULL,
206 }
207};
208
209static struct physmap_flash_data flash_data = {
210 .width = 2,
211 .nr_parts = ARRAY_SIZE(r2d_partitions),
212 .parts = r2d_partitions,
213};
214
215static struct resource flash_resource = {
216 .start = 0x00000000,
217 .end = 0x02000000,
218 .flags = IORESOURCE_MEM,
219};
220
221static struct platform_device flash_device = {
222 .name = "physmap-flash",
223 .id = -1,
224 .resource = &flash_resource,
225 .num_resources = 1,
226 .dev = {
227 .platform_data = &flash_data,
228 },
229};
230
184static struct platform_device *rts7751r2d_devices[] __initdata = { 231static struct platform_device *rts7751r2d_devices[] __initdata = {
185 &sm501_device, 232 &sm501_device,
186 &heartbeat_device, 233 &heartbeat_device,
@@ -203,6 +250,9 @@ static int __init rts7751r2d_devices_setup(void)
203 if (register_trapped_io(&cf_trapped_io) == 0) 250 if (register_trapped_io(&cf_trapped_io) == 0)
204 platform_device_register(&cf_ide_device); 251 platform_device_register(&cf_ide_device);
205 252
253 if (mach_is_r2d_plus())
254 platform_device_register(&flash_device);
255
206 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); 256 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
207 257
208 return platform_add_devices(rts7751r2d_devices, 258 return platform_add_devices(rts7751r2d_devices,
diff --git a/arch/sh/boards/mach-se/7724/Makefile b/arch/sh/boards/mach-se/7724/Makefile
new file mode 100644
index 000000000000..349cbd6ce82d
--- /dev/null
+++ b/arch/sh/boards/mach-se/7724/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for the HITACHI UL SolutionEngine 7724 specific parts of the kernel
3#
4# This file is subject to the terms and conditions of the GNU General Public
5# License. See the file "COPYING" in the main directory of this archive
6# for more details.
7#
8#
9
10obj-y := setup.o irq.o \ No newline at end of file
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
new file mode 100644
index 000000000000..f76cf3b49f23
--- /dev/null
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -0,0 +1,139 @@
1/*
2 * linux/arch/sh/boards/se/7724/irq.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on linux/arch/sh/boards/se/7722/irq.c
9 * Copyright (C) 2007 Nobuhiro Iwamatsu
10 *
11 * Hitachi UL SolutionEngine 7724 Support.
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/init.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <asm/irq.h>
21#include <asm/io.h>
22#include <mach-se/mach/se7724.h>
23
24struct fpga_irq {
25 unsigned long sraddr;
26 unsigned long mraddr;
27 unsigned short mask;
28 unsigned int base;
29};
30
31static unsigned int fpga2irq(unsigned int irq)
32{
33 if (irq >= IRQ0_BASE &&
34 irq <= IRQ0_END)
35 return IRQ0_IRQ;
36 else if (irq >= IRQ1_BASE &&
37 irq <= IRQ1_END)
38 return IRQ1_IRQ;
39 else
40 return IRQ2_IRQ;
41}
42
43static struct fpga_irq get_fpga_irq(unsigned int irq)
44{
45 struct fpga_irq set;
46
47 switch (irq) {
48 case IRQ0_IRQ:
49 set.sraddr = IRQ0_SR;
50 set.mraddr = IRQ0_MR;
51 set.mask = IRQ0_MASK;
52 set.base = IRQ0_BASE;
53 break;
54 case IRQ1_IRQ:
55 set.sraddr = IRQ1_SR;
56 set.mraddr = IRQ1_MR;
57 set.mask = IRQ1_MASK;
58 set.base = IRQ1_BASE;
59 break;
60 default:
61 set.sraddr = IRQ2_SR;
62 set.mraddr = IRQ2_MR;
63 set.mask = IRQ2_MASK;
64 set.base = IRQ2_BASE;
65 break;
66 }
67
68 return set;
69}
70
71static void disable_se7724_irq(unsigned int irq)
72{
73 struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
74 unsigned int bit = irq - set.base;
75 ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr);
76}
77
78static void enable_se7724_irq(unsigned int irq)
79{
80 struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
81 unsigned int bit = irq - set.base;
82 ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
83}
84
85static struct irq_chip se7724_irq_chip __read_mostly = {
86 .name = "SE7724-FPGA",
87 .mask = disable_se7724_irq,
88 .unmask = enable_se7724_irq,
89 .mask_ack = disable_se7724_irq,
90};
91
92static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
93{
94 struct fpga_irq set = get_fpga_irq(irq);
95 unsigned short intv = ctrl_inw(set.sraddr);
96 struct irq_desc *ext_desc;
97 unsigned int ext_irq = set.base;
98
99 intv &= set.mask;
100
101 while (intv) {
102 if (intv & 0x0001) {
103 ext_desc = irq_desc + ext_irq;
104 handle_level_irq(ext_irq, ext_desc);
105 }
106 intv >>= 1;
107 ext_irq++;
108 }
109}
110
111/*
112 * Initialize IRQ setting
113 */
114void __init init_se7724_IRQ(void)
115{
116 int i;
117
118 ctrl_outw(0xffff, IRQ0_MR); /* mask all */
119 ctrl_outw(0xffff, IRQ1_MR); /* mask all */
120 ctrl_outw(0xffff, IRQ2_MR); /* mask all */
121 ctrl_outw(0x0000, IRQ0_SR); /* clear irq */
122 ctrl_outw(0x0000, IRQ1_SR); /* clear irq */
123 ctrl_outw(0x0000, IRQ2_SR); /* clear irq */
124 ctrl_outw(0x002a, IRQ_MODE); /* set irq type */
125
126 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
127 set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
128 &se7724_irq_chip,
129 handle_level_irq, "level");
130
131 set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
132 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
133
134 set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
135 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
136
137 set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
138 set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
139}
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
new file mode 100644
index 000000000000..9cd04bd558b8
--- /dev/null
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -0,0 +1,448 @@
1/*
2 * linux/arch/sh/boards/se/7724/setup.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/delay.h>
19#include <linux/smc91x.h>
20#include <linux/gpio.h>
21#include <linux/input.h>
22#include <video/sh_mobile_lcdc.h>
23#include <media/sh_mobile_ceu.h>
24#include <asm/io.h>
25#include <asm/heartbeat.h>
26#include <asm/sh_keysc.h>
27#include <cpu/sh7724.h>
28#include <mach-se/mach/se7724.h>
29
30/*
31 * SWx 1234 5678
32 * ------------------------------------
33 * SW31 : 1001 1100 : default
34 * SW32 : 0111 1111 : use on board flash
35 *
36 * SW41 : abxx xxxx -> a = 0 : Analog monitor
37 * 1 : Digital monitor
38 * b = 0 : VGA
39 * 1 : SVGA
40 */
41
42/* Heartbeat */
43static struct heartbeat_data heartbeat_data = {
44 .regsize = 16,
45};
46
47static struct resource heartbeat_resources[] = {
48 [0] = {
49 .start = PA_LED,
50 .end = PA_LED,
51 .flags = IORESOURCE_MEM,
52 },
53};
54
55static struct platform_device heartbeat_device = {
56 .name = "heartbeat",
57 .id = -1,
58 .dev = {
59 .platform_data = &heartbeat_data,
60 },
61 .num_resources = ARRAY_SIZE(heartbeat_resources),
62 .resource = heartbeat_resources,
63};
64
65/* LAN91C111 */
66static struct smc91x_platdata smc91x_info = {
67 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
68};
69
70static struct resource smc91x_eth_resources[] = {
71 [0] = {
72 .name = "SMC91C111" ,
73 .start = 0x1a300300,
74 .end = 0x1a30030f,
75 .flags = IORESOURCE_MEM,
76 },
77 [1] = {
78 .start = IRQ0_SMC,
79 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
80 },
81};
82
83static struct platform_device smc91x_eth_device = {
84 .name = "smc91x",
85 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
86 .resource = smc91x_eth_resources,
87 .dev = {
88 .platform_data = &smc91x_info,
89 },
90};
91
92/* MTD */
93static struct mtd_partition nor_flash_partitions[] = {
94 {
95 .name = "uboot",
96 .offset = 0,
97 .size = (1 * 1024 * 1024),
98 .mask_flags = MTD_WRITEABLE, /* Read-only */
99 }, {
100 .name = "kernel",
101 .offset = MTDPART_OFS_APPEND,
102 .size = (2 * 1024 * 1024),
103 }, {
104 .name = "free-area",
105 .offset = MTDPART_OFS_APPEND,
106 .size = MTDPART_SIZ_FULL,
107 },
108};
109
110static struct physmap_flash_data nor_flash_data = {
111 .width = 2,
112 .parts = nor_flash_partitions,
113 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
114};
115
116static struct resource nor_flash_resources[] = {
117 [0] = {
118 .name = "NOR Flash",
119 .start = 0x00000000,
120 .end = 0x01ffffff,
121 .flags = IORESOURCE_MEM,
122 }
123};
124
125static struct platform_device nor_flash_device = {
126 .name = "physmap-flash",
127 .resource = nor_flash_resources,
128 .num_resources = ARRAY_SIZE(nor_flash_resources),
129 .dev = {
130 .platform_data = &nor_flash_data,
131 },
132};
133
134/* LCDC */
135static struct sh_mobile_lcdc_info lcdc_info = {
136 .clock_source = LCDC_CLK_EXTERNAL,
137 .ch[0] = {
138 .chan = LCDC_CHAN_MAINLCD,
139 .bpp = 16,
140 .clock_divider = 1,
141 .lcd_cfg = {
142 .name = "LB070WV1",
143 .sync = 0, /* hsync and vsync are active low */
144 },
145 .lcd_size_cfg = { /* 7.0 inch */
146 .width = 152,
147 .height = 91,
148 },
149 .board_cfg = {
150 },
151 }
152};
153
154static struct resource lcdc_resources[] = {
155 [0] = {
156 .name = "LCDC",
157 .start = 0xfe940000,
158 .end = 0xfe941fff,
159 .flags = IORESOURCE_MEM,
160 },
161 [1] = {
162 .start = 106,
163 .flags = IORESOURCE_IRQ,
164 },
165};
166
167static struct platform_device lcdc_device = {
168 .name = "sh_mobile_lcdc_fb",
169 .num_resources = ARRAY_SIZE(lcdc_resources),
170 .resource = lcdc_resources,
171 .dev = {
172 .platform_data = &lcdc_info,
173 },
174};
175
176/* CEU0 */
177static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
178 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
179};
180
181static struct resource ceu0_resources[] = {
182 [0] = {
183 .name = "CEU0",
184 .start = 0xfe910000,
185 .end = 0xfe91009f,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = 52,
190 .flags = IORESOURCE_IRQ,
191 },
192 [2] = {
193 /* place holder for contiguous memory */
194 },
195};
196
197static struct platform_device ceu0_device = {
198 .name = "sh_mobile_ceu",
199 .id = 0, /* "ceu0" clock */
200 .num_resources = ARRAY_SIZE(ceu0_resources),
201 .resource = ceu0_resources,
202 .dev = {
203 .platform_data = &sh_mobile_ceu0_info,
204 },
205};
206
207/* CEU1 */
208static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
209 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
210};
211
212static struct resource ceu1_resources[] = {
213 [0] = {
214 .name = "CEU1",
215 .start = 0xfe914000,
216 .end = 0xfe91409f,
217 .flags = IORESOURCE_MEM,
218 },
219 [1] = {
220 .start = 63,
221 .flags = IORESOURCE_IRQ,
222 },
223 [2] = {
224 /* place holder for contiguous memory */
225 },
226};
227
228static struct platform_device ceu1_device = {
229 .name = "sh_mobile_ceu",
230 .id = 1, /* "ceu1" clock */
231 .num_resources = ARRAY_SIZE(ceu1_resources),
232 .resource = ceu1_resources,
233 .dev = {
234 .platform_data = &sh_mobile_ceu1_info,
235 },
236};
237
238/* KEYSC */
239static struct sh_keysc_info keysc_info = {
240 .mode = SH_KEYSC_MODE_1,
241 .scan_timing = 10,
242 .delay = 50,
243 .keycodes = {
244 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
245 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
246 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
247 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
248 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
249 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
250 },
251};
252
253static struct resource keysc_resources[] = {
254 [0] = {
255 .start = 0x1a204000,
256 .end = 0x1a20400f,
257 .flags = IORESOURCE_MEM,
258 },
259 [1] = {
260 .start = IRQ0_KEY,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device keysc_device = {
266 .name = "sh_keysc",
267 .id = 0, /* "keysc0" clock */
268 .num_resources = ARRAY_SIZE(keysc_resources),
269 .resource = keysc_resources,
270 .dev = {
271 .platform_data = &keysc_info,
272 },
273};
274
275static struct platform_device *ms7724se_devices[] __initdata = {
276 &heartbeat_device,
277 &smc91x_eth_device,
278 &lcdc_device,
279 &nor_flash_device,
280 &ceu0_device,
281 &ceu1_device,
282 &keysc_device,
283};
284
285#define SW4140 0xBA201000
286#define FPGA_OUT 0xBA200400
287#define PORT_HIZA 0xA4050158
288
289#define SW41_A 0x0100
290#define SW41_B 0x0200
291#define SW41_C 0x0400
292#define SW41_D 0x0800
293#define SW41_E 0x1000
294#define SW41_F 0x2000
295#define SW41_G 0x4000
296#define SW41_H 0x8000
297static int __init devices_setup(void)
298{
299 u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
300
301 /* Reset Release */
302 ctrl_outw(ctrl_inw(FPGA_OUT) &
303 ~((1 << 1) | /* LAN */
304 (1 << 6) | /* VIDEO DAC */
305 (1 << 12)), /* USB0 */
306 FPGA_OUT);
307
308 /* enable IRQ 0,1,2 */
309 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
310 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
311 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
312
313 /* enable SCIFA3 */
314 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
315 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
316 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
317 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
318 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
319
320 /* enable LCDC */
321 gpio_request(GPIO_FN_LCDD23, NULL);
322 gpio_request(GPIO_FN_LCDD22, NULL);
323 gpio_request(GPIO_FN_LCDD21, NULL);
324 gpio_request(GPIO_FN_LCDD20, NULL);
325 gpio_request(GPIO_FN_LCDD19, NULL);
326 gpio_request(GPIO_FN_LCDD18, NULL);
327 gpio_request(GPIO_FN_LCDD17, NULL);
328 gpio_request(GPIO_FN_LCDD16, NULL);
329 gpio_request(GPIO_FN_LCDD15, NULL);
330 gpio_request(GPIO_FN_LCDD14, NULL);
331 gpio_request(GPIO_FN_LCDD13, NULL);
332 gpio_request(GPIO_FN_LCDD12, NULL);
333 gpio_request(GPIO_FN_LCDD11, NULL);
334 gpio_request(GPIO_FN_LCDD10, NULL);
335 gpio_request(GPIO_FN_LCDD9, NULL);
336 gpio_request(GPIO_FN_LCDD8, NULL);
337 gpio_request(GPIO_FN_LCDD7, NULL);
338 gpio_request(GPIO_FN_LCDD6, NULL);
339 gpio_request(GPIO_FN_LCDD5, NULL);
340 gpio_request(GPIO_FN_LCDD4, NULL);
341 gpio_request(GPIO_FN_LCDD3, NULL);
342 gpio_request(GPIO_FN_LCDD2, NULL);
343 gpio_request(GPIO_FN_LCDD1, NULL);
344 gpio_request(GPIO_FN_LCDD0, NULL);
345 gpio_request(GPIO_FN_LCDDISP, NULL);
346 gpio_request(GPIO_FN_LCDHSYN, NULL);
347 gpio_request(GPIO_FN_LCDDCK, NULL);
348 gpio_request(GPIO_FN_LCDVSYN, NULL);
349 gpio_request(GPIO_FN_LCDDON, NULL);
350 gpio_request(GPIO_FN_LCDVEPWC, NULL);
351 gpio_request(GPIO_FN_LCDVCPWC, NULL);
352 gpio_request(GPIO_FN_LCDRD, NULL);
353 gpio_request(GPIO_FN_LCDLCLK, NULL);
354 ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
355
356 /* enable CEU0 */
357 gpio_request(GPIO_FN_VIO0_D15, NULL);
358 gpio_request(GPIO_FN_VIO0_D14, NULL);
359 gpio_request(GPIO_FN_VIO0_D13, NULL);
360 gpio_request(GPIO_FN_VIO0_D12, NULL);
361 gpio_request(GPIO_FN_VIO0_D11, NULL);
362 gpio_request(GPIO_FN_VIO0_D10, NULL);
363 gpio_request(GPIO_FN_VIO0_D9, NULL);
364 gpio_request(GPIO_FN_VIO0_D8, NULL);
365 gpio_request(GPIO_FN_VIO0_D7, NULL);
366 gpio_request(GPIO_FN_VIO0_D6, NULL);
367 gpio_request(GPIO_FN_VIO0_D5, NULL);
368 gpio_request(GPIO_FN_VIO0_D4, NULL);
369 gpio_request(GPIO_FN_VIO0_D3, NULL);
370 gpio_request(GPIO_FN_VIO0_D2, NULL);
371 gpio_request(GPIO_FN_VIO0_D1, NULL);
372 gpio_request(GPIO_FN_VIO0_D0, NULL);
373 gpio_request(GPIO_FN_VIO0_VD, NULL);
374 gpio_request(GPIO_FN_VIO0_CLK, NULL);
375 gpio_request(GPIO_FN_VIO0_FLD, NULL);
376 gpio_request(GPIO_FN_VIO0_HD, NULL);
377 platform_resource_setup_memory(&ceu0_device, "ceu", 4 << 20);
378
379 /* enable CEU1 */
380 gpio_request(GPIO_FN_VIO1_D7, NULL);
381 gpio_request(GPIO_FN_VIO1_D6, NULL);
382 gpio_request(GPIO_FN_VIO1_D5, NULL);
383 gpio_request(GPIO_FN_VIO1_D4, NULL);
384 gpio_request(GPIO_FN_VIO1_D3, NULL);
385 gpio_request(GPIO_FN_VIO1_D2, NULL);
386 gpio_request(GPIO_FN_VIO1_D1, NULL);
387 gpio_request(GPIO_FN_VIO1_D0, NULL);
388 gpio_request(GPIO_FN_VIO1_FLD, NULL);
389 gpio_request(GPIO_FN_VIO1_HD, NULL);
390 gpio_request(GPIO_FN_VIO1_VD, NULL);
391 gpio_request(GPIO_FN_VIO1_CLK, NULL);
392 platform_resource_setup_memory(&ceu1_device, "ceu", 4 << 20);
393
394 /* KEYSC */
395 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
396 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
397 gpio_request(GPIO_FN_KEYIN4, NULL);
398 gpio_request(GPIO_FN_KEYIN3, NULL);
399 gpio_request(GPIO_FN_KEYIN2, NULL);
400 gpio_request(GPIO_FN_KEYIN1, NULL);
401 gpio_request(GPIO_FN_KEYIN0, NULL);
402 gpio_request(GPIO_FN_KEYOUT3, NULL);
403 gpio_request(GPIO_FN_KEYOUT2, NULL);
404 gpio_request(GPIO_FN_KEYOUT1, NULL);
405 gpio_request(GPIO_FN_KEYOUT0, NULL);
406
407 if (sw & SW41_B) {
408 /* SVGA */
409 lcdc_info.ch[0].lcd_cfg.xres = 800;
410 lcdc_info.ch[0].lcd_cfg.yres = 600;
411 lcdc_info.ch[0].lcd_cfg.left_margin = 142;
412 lcdc_info.ch[0].lcd_cfg.right_margin = 52;
413 lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
414 lcdc_info.ch[0].lcd_cfg.upper_margin = 24;
415 lcdc_info.ch[0].lcd_cfg.lower_margin = 2;
416 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
417 } else {
418 /* VGA */
419 lcdc_info.ch[0].lcd_cfg.xres = 640;
420 lcdc_info.ch[0].lcd_cfg.yres = 480;
421 lcdc_info.ch[0].lcd_cfg.left_margin = 105;
422 lcdc_info.ch[0].lcd_cfg.right_margin = 50;
423 lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
424 lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
425 lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
426 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
427 }
428
429 if (sw & SW41_A) {
430 /* Digital monitor */
431 lcdc_info.ch[0].interface_type = RGB18;
432 lcdc_info.ch[0].flags = 0;
433 } else {
434 /* Analog monitor */
435 lcdc_info.ch[0].interface_type = RGB24;
436 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
437 }
438
439 return platform_add_devices(ms7724se_devices,
440 ARRAY_SIZE(ms7724se_devices));
441}
442device_initcall(devices_setup);
443
444static struct sh_machine_vector mv_ms7724se __initmv = {
445 .mv_name = "ms7724se",
446 .mv_init_irq = init_se7724_IRQ,
447 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
448};
diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index dbc29f3a9de5..e6f4341bfe6e 100644
--- a/arch/sh/boards/mach-se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := setup.o io.o irq.o 5obj-y := setup.o io.o irq.o
6
7obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c
index 6287ae570319..6e75bd4459e5 100644
--- a/arch/sh/boards/mach-se/7751/io.c
+++ b/arch/sh/boards/mach-se/7751/io.c
@@ -34,8 +34,6 @@ unsigned char sh7751se_inb(unsigned long port)
34{ 34{
35 if (PXSEG(port)) 35 if (PXSEG(port))
36 return *(volatile unsigned char *)port; 36 return *(volatile unsigned char *)port;
37 else if (is_pci_ioaddr(port))
38 return *(volatile unsigned char *)pci_ioaddr(port);
39 else 37 else
40 return (*port2adr(port)) & 0xff; 38 return (*port2adr(port)) & 0xff;
41} 39}
@@ -46,8 +44,6 @@ unsigned char sh7751se_inb_p(unsigned long port)
46 44
47 if (PXSEG(port)) 45 if (PXSEG(port))
48 v = *(volatile unsigned char *)port; 46 v = *(volatile unsigned char *)port;
49 else if (is_pci_ioaddr(port))
50 v = *(volatile unsigned char *)pci_ioaddr(port);
51 else 47 else
52 v = (*port2adr(port)) & 0xff; 48 v = (*port2adr(port)) & 0xff;
53 ctrl_delay(); 49 ctrl_delay();
@@ -58,8 +54,6 @@ unsigned short sh7751se_inw(unsigned long port)
58{ 54{
59 if (PXSEG(port)) 55 if (PXSEG(port))
60 return *(volatile unsigned short *)port; 56 return *(volatile unsigned short *)port;
61 else if (is_pci_ioaddr(port))
62 return *(volatile unsigned short *)pci_ioaddr(port);
63 else if (port >= 0x2000) 57 else if (port >= 0x2000)
64 return *port2adr(port); 58 return *port2adr(port);
65 else 59 else
@@ -71,8 +65,6 @@ unsigned int sh7751se_inl(unsigned long port)
71{ 65{
72 if (PXSEG(port)) 66 if (PXSEG(port))
73 return *(volatile unsigned long *)port; 67 return *(volatile unsigned long *)port;
74 else if (is_pci_ioaddr(port))
75 return *(volatile unsigned int *)pci_ioaddr(port);
76 else if (port >= 0x2000) 68 else if (port >= 0x2000)
77 return *port2adr(port); 69 return *port2adr(port);
78 else 70 else
@@ -85,8 +77,6 @@ void sh7751se_outb(unsigned char value, unsigned long port)
85 77
86 if (PXSEG(port)) 78 if (PXSEG(port))
87 *(volatile unsigned char *)port = value; 79 *(volatile unsigned char *)port = value;
88 else if (is_pci_ioaddr(port))
89 *((unsigned char*)pci_ioaddr(port)) = value;
90 else 80 else
91 *(port2adr(port)) = value; 81 *(port2adr(port)) = value;
92} 82}
@@ -95,8 +85,6 @@ void sh7751se_outb_p(unsigned char value, unsigned long port)
95{ 85{
96 if (PXSEG(port)) 86 if (PXSEG(port))
97 *(volatile unsigned char *)port = value; 87 *(volatile unsigned char *)port = value;
98 else if (is_pci_ioaddr(port))
99 *((unsigned char*)pci_ioaddr(port)) = value;
100 else 88 else
101 *(port2adr(port)) = value; 89 *(port2adr(port)) = value;
102 ctrl_delay(); 90 ctrl_delay();
@@ -106,8 +94,6 @@ void sh7751se_outw(unsigned short value, unsigned long port)
106{ 94{
107 if (PXSEG(port)) 95 if (PXSEG(port))
108 *(volatile unsigned short *)port = value; 96 *(volatile unsigned short *)port = value;
109 else if (is_pci_ioaddr(port))
110 *((unsigned short *)pci_ioaddr(port)) = value;
111 else if (port >= 0x2000) 97 else if (port >= 0x2000)
112 *port2adr(port) = value; 98 *port2adr(port) = value;
113 else 99 else
@@ -118,8 +104,6 @@ void sh7751se_outl(unsigned int value, unsigned long port)
118{ 104{
119 if (PXSEG(port)) 105 if (PXSEG(port))
120 *(volatile unsigned long *)port = value; 106 *(volatile unsigned long *)port = value;
121 else if (is_pci_ioaddr(port))
122 *((unsigned long*)pci_ioaddr(port)) = value;
123 else 107 else
124 maybebadio(port); 108 maybebadio(port);
125} 109}
diff --git a/arch/sh/boards/mach-se/7751/pci.c b/arch/sh/boards/mach-se/7751/pci.c
deleted file mode 100644
index 203b2923fe7f..000000000000
--- a/arch/sh/boards/mach-se/7751/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * linux/arch/sh/boards/se/7751/pci.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01)
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19
20#include <asm/io.h>
21#include "../../../drivers/pci/pci-sh7751.h"
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33/*
34 * Description: This function sets up and initializes the pcic, sets
35 * up the BARS, maps the DRAM into the address space etc, etc.
36 */
37int __init pcibios_init_platform(void)
38{
39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
40 unsigned short bcr2;
41
42 /*
43 * Initialize the slave bus controller on the pcic. The values used
44 * here should not be hardcoded, but they should be taken from the bsc
45 * on the processor, to make this function as generic as possible.
46 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
47 * for the pcic to work, its settings need to be exactly the same.)
48 */
49 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
50 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
51 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
52 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
53 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
55
56 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
57 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
58
59 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
60 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
61 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
62 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
63 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
64 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
67
68
69 /* Enable all interrupts, so we know what to fix */
70 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
71 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
72
73 /* Set up standard PCI config registers */
74 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
75 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
76 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
77 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
78 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
79 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
80 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
81 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
82 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
83 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
84
85 /* Now turn it on... */
86 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
87
88 /*
89 * Set PCIMBR and PCIIOBR here, assuming a single window
90 * (16M MEM, 256K IO) is enough. If a larger space is
91 * needed, the readx/writex and inx/outx functions will
92 * have to do more (e.g. setting registers for each call).
93 */
94
95 /*
96 * Set the MBR so PCI address is one-to-one with window,
97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption.
99 */
100 BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);
101
102 PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM);
103
104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));
106
107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
109
110 return 1;
111}
112
113int __init pcibios_map_platform_irq(u8 slot, u8 pin)
114{
115 switch (slot) {
116 case 0: return 13;
117 case 1: return 13; /* AMD Ethernet controller */
118 case 2: return -1;
119 case 3: return -1;
120 case 4: return -1;
121 default:
122 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
123 return -1;
124 }
125}
126
127static struct resource sh7751_io_resource = {
128 .name = "SH7751 IO",
129 .start = SH7751_PCI_IO_BASE,
130 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
131 .flags = IORESOURCE_IO
132};
133
134static struct resource sh7751_mem_resource = {
135 .name = "SH7751 mem",
136 .start = SH7751_PCI_MEMORY_BASE,
137 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
138 .flags = IORESOURCE_MEM
139};
140
141extern struct pci_ops sh7751_pci_ops;
142
143struct pci_channel board_pci_channels[] = {
144 { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
145 { NULL, NULL, NULL, 0, 0 },
146};
147
diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c
index 66ad292c9fc3..b8d43b638fcf 100644
--- a/arch/sh/boards/mach-se/7780/irq.c
+++ b/arch/sh/boards/mach-se/7780/irq.c
@@ -12,10 +12,13 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <asm/irq.h> 15#include <linux/irq.h>
16#include <asm/io.h> 16#include <linux/io.h>
17#include <mach-se/mach/se7780.h> 17#include <mach-se/mach/se7780.h>
18 18
19#define INTC_BASE 0xffd00000
20#define INTC_ICR1 (INTC_BASE+0x1c)
21
19/* 22/*
20 * Initialize IRQ setting 23 * Initialize IRQ setting
21 */ 24 */
@@ -43,4 +46,24 @@ void __init init_se7780_IRQ(void)
43 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); 46 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
44 47
45 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ 48 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
49
50 /* ICR1: detect low level(for 2ndcut) */
51 ctrl_outl(0xAAAA0000, INTC_ICR1);
52
53 /*
54 * FPGA PCISEL register initialize
55 *
56 * CPU || SLOT1 | SLOT2 | S-ATA | USB
57 * -------------------------------------
58 * INTA || INTA | INTD | -- | INTB
59 * -------------------------------------
60 * INTB || INTB | INTA | -- | INTC
61 * -------------------------------------
62 * INTC || INTC | INTB | INTA | --
63 * -------------------------------------
64 * INTD || INTD | INTC | -- | INTA
65 * -------------------------------------
66 */
67 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
68 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
46} 69}
diff --git a/arch/sh/boards/mach-se/Makefile b/arch/sh/boards/mach-se/Makefile
index 2de42bae4b4f..b537e238c6bc 100644
--- a/arch/sh/boards/mach-se/Makefile
+++ b/arch/sh/boards/mach-se/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/
7obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/ 7obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/
8obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/ 8obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/
9obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/ 9obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/
10obj-$(CONFIG_SH_7724_SOLUTION_ENGINE) += 7724/
diff --git a/arch/sh/boards/mach-sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c
index 0a9266bb51c5..a8b9f844ab5b 100644
--- a/arch/sh/boards/mach-sh03/rtc.c
+++ b/arch/sh/boards/mach-sh03/rtc.c
@@ -35,13 +35,13 @@
35#define RTC_BUSY 1 35#define RTC_BUSY 1
36#define RTC_STOP 2 36#define RTC_STOP 2
37 37
38extern spinlock_t rtc_lock; 38static DEFINE_SPINLOCK(sh03_rtc_lock);
39 39
40unsigned long get_cmos_time(void) 40unsigned long get_cmos_time(void)
41{ 41{
42 unsigned int year, mon, day, hour, min, sec; 42 unsigned int year, mon, day, hour, min, sec;
43 43
44 spin_lock(&rtc_lock); 44 spin_lock(&sh03_rtc_lock);
45 again: 45 again:
46 do { 46 do {
47 sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10; 47 sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10;
@@ -73,7 +73,7 @@ unsigned long get_cmos_time(void)
73 goto again; 73 goto again;
74 } 74 }
75 75
76 spin_unlock(&rtc_lock); 76 spin_unlock(&sh03_rtc_lock);
77 return mktime(year, mon, day, hour, min, sec); 77 return mktime(year, mon, day, hour, min, sec);
78} 78}
79 79
@@ -91,7 +91,7 @@ static int set_rtc_mmss(unsigned long nowtime)
91 int i; 91 int i;
92 92
93 /* gets recalled with irq locally disabled */ 93 /* gets recalled with irq locally disabled */
94 spin_lock(&rtc_lock); 94 spin_lock(&sh03_rtc_lock);
95 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ 95 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
96 if (!(ctrl_inb(RTC_CTL) & RTC_BUSY)) 96 if (!(ctrl_inb(RTC_CTL) & RTC_BUSY))
97 break; 97 break;
@@ -113,7 +113,7 @@ static int set_rtc_mmss(unsigned long nowtime)
113 cmos_minutes, real_minutes); 113 cmos_minutes, real_minutes);
114 retval = -1; 114 retval = -1;
115 } 115 }
116 spin_unlock(&rtc_lock); 116 spin_unlock(&sh03_rtc_lock);
117 117
118 return retval; 118 return retval;
119} 119}
diff --git a/arch/sh/boards/mach-snapgear/io.c b/arch/sh/boards/mach-snapgear/io.c
index 0f4824264557..476650e42dbc 100644
--- a/arch/sh/boards/mach-snapgear/io.c
+++ b/arch/sh/boards/mach-snapgear/io.c
@@ -36,8 +36,6 @@ unsigned char snapgear_inb(unsigned long port)
36{ 36{
37 if (PXSEG(port)) 37 if (PXSEG(port))
38 return *(volatile unsigned char *)port; 38 return *(volatile unsigned char *)port;
39 else if (is_pci_ioaddr(port))
40 return *(volatile unsigned char *)pci_ioaddr(port);
41 else 39 else
42 return (*port2adr(port)) & 0xff; 40 return (*port2adr(port)) & 0xff;
43} 41}
@@ -48,8 +46,6 @@ unsigned char snapgear_inb_p(unsigned long port)
48 46
49 if (PXSEG(port)) 47 if (PXSEG(port))
50 v = *(volatile unsigned char *)port; 48 v = *(volatile unsigned char *)port;
51 else if (is_pci_ioaddr(port))
52 v = *(volatile unsigned char *)pci_ioaddr(port);
53 else 49 else
54 v = (*port2adr(port))&0xff; 50 v = (*port2adr(port))&0xff;
55 ctrl_delay(); 51 ctrl_delay();
@@ -60,8 +56,6 @@ unsigned short snapgear_inw(unsigned long port)
60{ 56{
61 if (PXSEG(port)) 57 if (PXSEG(port))
62 return *(volatile unsigned short *)port; 58 return *(volatile unsigned short *)port;
63 else if (is_pci_ioaddr(port))
64 return *(volatile unsigned short *)pci_ioaddr(port);
65 else if (port >= 0x2000) 59 else if (port >= 0x2000)
66 return *port2adr(port); 60 return *port2adr(port);
67 else 61 else
@@ -73,8 +67,6 @@ unsigned int snapgear_inl(unsigned long port)
73{ 67{
74 if (PXSEG(port)) 68 if (PXSEG(port))
75 return *(volatile unsigned long *)port; 69 return *(volatile unsigned long *)port;
76 else if (is_pci_ioaddr(port))
77 return *(volatile unsigned int *)pci_ioaddr(port);
78 else if (port >= 0x2000) 70 else if (port >= 0x2000)
79 return *port2adr(port); 71 return *port2adr(port);
80 else 72 else
@@ -87,8 +79,6 @@ void snapgear_outb(unsigned char value, unsigned long port)
87 79
88 if (PXSEG(port)) 80 if (PXSEG(port))
89 *(volatile unsigned char *)port = value; 81 *(volatile unsigned char *)port = value;
90 else if (is_pci_ioaddr(port))
91 *((unsigned char*)pci_ioaddr(port)) = value;
92 else 82 else
93 *(port2adr(port)) = value; 83 *(port2adr(port)) = value;
94} 84}
@@ -97,8 +87,6 @@ void snapgear_outb_p(unsigned char value, unsigned long port)
97{ 87{
98 if (PXSEG(port)) 88 if (PXSEG(port))
99 *(volatile unsigned char *)port = value; 89 *(volatile unsigned char *)port = value;
100 else if (is_pci_ioaddr(port))
101 *((unsigned char*)pci_ioaddr(port)) = value;
102 else 90 else
103 *(port2adr(port)) = value; 91 *(port2adr(port)) = value;
104 ctrl_delay(); 92 ctrl_delay();
@@ -108,8 +96,6 @@ void snapgear_outw(unsigned short value, unsigned long port)
108{ 96{
109 if (PXSEG(port)) 97 if (PXSEG(port))
110 *(volatile unsigned short *)port = value; 98 *(volatile unsigned short *)port = value;
111 else if (is_pci_ioaddr(port))
112 *((unsigned short *)pci_ioaddr(port)) = value;
113 else if (port >= 0x2000) 99 else if (port >= 0x2000)
114 *port2adr(port) = value; 100 *port2adr(port) = value;
115 else 101 else
@@ -120,8 +106,6 @@ void snapgear_outl(unsigned int value, unsigned long port)
120{ 106{
121 if (PXSEG(port)) 107 if (PXSEG(port))
122 *(volatile unsigned long *)port = value; 108 *(volatile unsigned long *)port = value;
123 else if (is_pci_ioaddr(port))
124 *((unsigned long*)pci_ioaddr(port)) = value;
125 else 109 else
126 maybebadio(port); 110 maybebadio(port);
127} 111}
diff --git a/arch/sh/boards/mach-systemh/io.c b/arch/sh/boards/mach-systemh/io.c
index dec3db0ee933..15577ff1f715 100644
--- a/arch/sh/boards/mach-systemh/io.c
+++ b/arch/sh/boards/mach-systemh/io.c
@@ -35,8 +35,6 @@ unsigned char sh7751systemh_inb(unsigned long port)
35{ 35{
36 if (PXSEG(port)) 36 if (PXSEG(port))
37 return *(volatile unsigned char *)port; 37 return *(volatile unsigned char *)port;
38 else if (is_pci_ioaddr(port))
39 return *(volatile unsigned char *)pci_ioaddr(port);
40 else if (port <= 0x3F1) 38 else if (port <= 0x3F1)
41 return *(volatile unsigned char *)ETHER_IOMAP(port); 39 return *(volatile unsigned char *)ETHER_IOMAP(port);
42 else 40 else
@@ -49,8 +47,6 @@ unsigned char sh7751systemh_inb_p(unsigned long port)
49 47
50 if (PXSEG(port)) 48 if (PXSEG(port))
51 v = *(volatile unsigned char *)port; 49 v = *(volatile unsigned char *)port;
52 else if (is_pci_ioaddr(port))
53 v = *(volatile unsigned char *)pci_ioaddr(port);
54 else if (port <= 0x3F1) 50 else if (port <= 0x3F1)
55 v = *(volatile unsigned char *)ETHER_IOMAP(port); 51 v = *(volatile unsigned char *)ETHER_IOMAP(port);
56 else 52 else
@@ -63,8 +59,6 @@ unsigned short sh7751systemh_inw(unsigned long port)
63{ 59{
64 if (PXSEG(port)) 60 if (PXSEG(port))
65 return *(volatile unsigned short *)port; 61 return *(volatile unsigned short *)port;
66 else if (is_pci_ioaddr(port))
67 return *(volatile unsigned short *)pci_ioaddr(port);
68 else if (port >= 0x2000) 62 else if (port >= 0x2000)
69 return *port2adr(port); 63 return *port2adr(port);
70 else if (port <= 0x3F1) 64 else if (port <= 0x3F1)
@@ -78,8 +72,6 @@ unsigned int sh7751systemh_inl(unsigned long port)
78{ 72{
79 if (PXSEG(port)) 73 if (PXSEG(port))
80 return *(volatile unsigned long *)port; 74 return *(volatile unsigned long *)port;
81 else if (is_pci_ioaddr(port))
82 return *(volatile unsigned int *)pci_ioaddr(port);
83 else if (port >= 0x2000) 75 else if (port >= 0x2000)
84 return *port2adr(port); 76 return *port2adr(port);
85 else if (port <= 0x3F1) 77 else if (port <= 0x3F1)
@@ -94,8 +86,6 @@ void sh7751systemh_outb(unsigned char value, unsigned long port)
94 86
95 if (PXSEG(port)) 87 if (PXSEG(port))
96 *(volatile unsigned char *)port = value; 88 *(volatile unsigned char *)port = value;
97 else if (is_pci_ioaddr(port))
98 *((unsigned char*)pci_ioaddr(port)) = value;
99 else if (port <= 0x3F1) 89 else if (port <= 0x3F1)
100 *(volatile unsigned char *)ETHER_IOMAP(port) = value; 90 *(volatile unsigned char *)ETHER_IOMAP(port) = value;
101 else 91 else
@@ -106,8 +96,6 @@ void sh7751systemh_outb_p(unsigned char value, unsigned long port)
106{ 96{
107 if (PXSEG(port)) 97 if (PXSEG(port))
108 *(volatile unsigned char *)port = value; 98 *(volatile unsigned char *)port = value;
109 else if (is_pci_ioaddr(port))
110 *((unsigned char*)pci_ioaddr(port)) = value;
111 else if (port <= 0x3F1) 99 else if (port <= 0x3F1)
112 *(volatile unsigned char *)ETHER_IOMAP(port) = value; 100 *(volatile unsigned char *)ETHER_IOMAP(port) = value;
113 else 101 else
@@ -119,8 +107,6 @@ void sh7751systemh_outw(unsigned short value, unsigned long port)
119{ 107{
120 if (PXSEG(port)) 108 if (PXSEG(port))
121 *(volatile unsigned short *)port = value; 109 *(volatile unsigned short *)port = value;
122 else if (is_pci_ioaddr(port))
123 *((unsigned short *)pci_ioaddr(port)) = value;
124 else if (port >= 0x2000) 110 else if (port >= 0x2000)
125 *port2adr(port) = value; 111 *port2adr(port) = value;
126 else if (port <= 0x3F1) 112 else if (port <= 0x3F1)
@@ -133,8 +119,6 @@ void sh7751systemh_outl(unsigned int value, unsigned long port)
133{ 119{
134 if (PXSEG(port)) 120 if (PXSEG(port))
135 *(volatile unsigned long *)port = value; 121 *(volatile unsigned long *)port = value;
136 else if (is_pci_ioaddr(port))
137 *((unsigned long*)pci_ioaddr(port)) = value;
138 else 122 else
139 maybebadio(port); 123 maybebadio(port);
140} 124}
diff --git a/arch/sh/boards/mach-titan/io.c b/arch/sh/boards/mach-titan/io.c
index 4badad4c6f30..0130e9826aca 100644
--- a/arch/sh/boards/mach-titan/io.c
+++ b/arch/sh/boards/mach-titan/io.c
@@ -17,8 +17,6 @@ u8 titan_inb(unsigned long port)
17{ 17{
18 if (PXSEG(port)) 18 if (PXSEG(port))
19 return ctrl_inb(port); 19 return ctrl_inb(port);
20 else if (is_pci_ioaddr(port))
21 return ctrl_inb(pci_ioaddr(port));
22 return ctrl_inw(port2adr(port)) & 0xff; 20 return ctrl_inw(port2adr(port)) & 0xff;
23} 21}
24 22
@@ -28,8 +26,6 @@ u8 titan_inb_p(unsigned long port)
28 26
29 if (PXSEG(port)) 27 if (PXSEG(port))
30 v = ctrl_inb(port); 28 v = ctrl_inb(port);
31 else if (is_pci_ioaddr(port))
32 v = ctrl_inb(pci_ioaddr(port));
33 else 29 else
34 v = ctrl_inw(port2adr(port)) & 0xff; 30 v = ctrl_inw(port2adr(port)) & 0xff;
35 ctrl_delay(); 31 ctrl_delay();
@@ -40,8 +36,6 @@ u16 titan_inw(unsigned long port)
40{ 36{
41 if (PXSEG(port)) 37 if (PXSEG(port))
42 return ctrl_inw(port); 38 return ctrl_inw(port);
43 else if (is_pci_ioaddr(port))
44 return ctrl_inw(pci_ioaddr(port));
45 else if (port >= 0x2000) 39 else if (port >= 0x2000)
46 return ctrl_inw(port2adr(port)); 40 return ctrl_inw(port2adr(port));
47 else 41 else
@@ -53,8 +47,6 @@ u32 titan_inl(unsigned long port)
53{ 47{
54 if (PXSEG(port)) 48 if (PXSEG(port))
55 return ctrl_inl(port); 49 return ctrl_inl(port);
56 else if (is_pci_ioaddr(port))
57 return ctrl_inl(pci_ioaddr(port));
58 else if (port >= 0x2000) 50 else if (port >= 0x2000)
59 return ctrl_inw(port2adr(port)); 51 return ctrl_inw(port2adr(port));
60 else 52 else
@@ -66,8 +58,6 @@ void titan_outb(u8 value, unsigned long port)
66{ 58{
67 if (PXSEG(port)) 59 if (PXSEG(port))
68 ctrl_outb(value, port); 60 ctrl_outb(value, port);
69 else if (is_pci_ioaddr(port))
70 ctrl_outb(value, pci_ioaddr(port));
71 else 61 else
72 ctrl_outw(value, port2adr(port)); 62 ctrl_outw(value, port2adr(port));
73} 63}
@@ -76,8 +66,6 @@ void titan_outb_p(u8 value, unsigned long port)
76{ 66{
77 if (PXSEG(port)) 67 if (PXSEG(port))
78 ctrl_outb(value, port); 68 ctrl_outb(value, port);
79 else if (is_pci_ioaddr(port))
80 ctrl_outb(value, pci_ioaddr(port));
81 else 69 else
82 ctrl_outw(value, port2adr(port)); 70 ctrl_outw(value, port2adr(port));
83 ctrl_delay(); 71 ctrl_delay();
@@ -87,8 +75,6 @@ void titan_outw(u16 value, unsigned long port)
87{ 75{
88 if (PXSEG(port)) 76 if (PXSEG(port))
89 ctrl_outw(value, port); 77 ctrl_outw(value, port);
90 else if (is_pci_ioaddr(port))
91 ctrl_outw(value, pci_ioaddr(port));
92 else if (port >= 0x2000) 78 else if (port >= 0x2000)
93 ctrl_outw(value, port2adr(port)); 79 ctrl_outw(value, port2adr(port));
94 else 80 else
@@ -99,8 +85,6 @@ void titan_outl(u32 value, unsigned long port)
99{ 85{
100 if (PXSEG(port)) 86 if (PXSEG(port))
101 ctrl_outl(value, port); 87 ctrl_outl(value, port);
102 else if (is_pci_ioaddr(port))
103 ctrl_outl(value, pci_ioaddr(port));
104 else 88 else
105 maybebadio(port); 89 maybebadio(port);
106} 90}
@@ -117,10 +101,8 @@ void titan_outsl(unsigned long port, const void *src, unsigned long count)
117 101
118void __iomem *titan_ioport_map(unsigned long port, unsigned int size) 102void __iomem *titan_ioport_map(unsigned long port, unsigned int size)
119{ 103{
120 if (PXSEG(port) || is_pci_memaddr(port)) 104 if (PXSEG(port))
121 return (void __iomem *)port; 105 return (void __iomem *)port;
122 else if (is_pci_ioaddr(port))
123 return (void __iomem *)pci_ioaddr(port);
124 106
125 return (void __iomem *)port2adr(port); 107 return (void __iomem *)port2adr(port);
126} 108}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 12:55:45 -0500