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-rw-r--r--arch/sh/boards/superh/microdev/Makefile8
-rw-r--r--arch/sh/boards/superh/microdev/io.c370
-rw-r--r--arch/sh/boards/superh/microdev/irq.c200
-rw-r--r--arch/sh/boards/superh/microdev/led.c102
-rw-r--r--arch/sh/boards/superh/microdev/setup.c278
5 files changed, 958 insertions, 0 deletions
diff --git a/arch/sh/boards/superh/microdev/Makefile b/arch/sh/boards/superh/microdev/Makefile
new file mode 100644
index 000000000000..1387dd6c85eb
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the SuperH MicroDev specific parts of the kernel
3#
4
5obj-y := setup.o irq.o io.o
6
7obj-$(CONFIG_HEARTBEAT) += led.o
8
diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/superh/microdev/io.c
new file mode 100644
index 000000000000..fe83b2c03076
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/io.c
@@ -0,0 +1,370 @@
1/*
2 * linux/arch/sh/kernel/io_microdev.c
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 * Copyright (C) 2003, 2004 SuperH, Inc.
6 * Copyright (C) 2004 Paul Mundt
7 *
8 * SuperH SH4-202 MicroDev board support.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/wait.h>
18#include <asm/io.h>
19#include <asm/mach/io.h>
20
21 /*
22 * we need to have a 'safe' address to re-direct all I/O requests
23 * that we do not explicitly wish to handle. This safe address
24 * must have the following properies:
25 *
26 * * writes are ignored (no exception)
27 * * reads are benign (no side-effects)
28 * * accesses of width 1, 2 and 4-bytes are all valid.
29 *
30 * The Processor Version Register (PVR) has these properties.
31 */
32#define PVR 0xff000030 /* Processor Version Register */
33
34
35#define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */
36#define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */
37#define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */
38#define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */
39#define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */
40#define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */
41#define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */
42#define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */
43#define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */
44
45#define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */
46#define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */
47#define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */
48#define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */
49#define IO_SERIAL_EXTENT 0x10ul
50
51#define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */
52#define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */
53#define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */
54
55#define PORT2ADDR(x) (microdev_isa_port2addr(x))
56
57
58static inline void delay(void)
59{
60#if defined(CONFIG_PCI)
61 /* System board present, just make a dummy SRAM access. (CS0 will be
62 mapped to PCI memory, probably good to avoid it.) */
63 ctrl_inw(0xa6800000);
64#else
65 /* CS0 will be mapped to flash, ROM etc so safe to access it. */
66 ctrl_inw(0xa0000000);
67#endif
68}
69
70unsigned char microdev_inb(unsigned long port)
71{
72#ifdef CONFIG_PCI
73 if (port >= PCIBIOS_MIN_IO)
74 return microdev_pci_inb(port);
75#endif
76 return *(volatile unsigned char*)PORT2ADDR(port);
77}
78
79unsigned short microdev_inw(unsigned long port)
80{
81#ifdef CONFIG_PCI
82 if (port >= PCIBIOS_MIN_IO)
83 return microdev_pci_inw(port);
84#endif
85 return *(volatile unsigned short*)PORT2ADDR(port);
86}
87
88unsigned int microdev_inl(unsigned long port)
89{
90#ifdef CONFIG_PCI
91 if (port >= PCIBIOS_MIN_IO)
92 return microdev_pci_inl(port);
93#endif
94 return *(volatile unsigned int*)PORT2ADDR(port);
95}
96
97void microdev_outb(unsigned char b, unsigned long port)
98{
99#ifdef CONFIG_PCI
100 if (port >= PCIBIOS_MIN_IO) {
101 microdev_pci_outb(b, port);
102 return;
103 }
104#endif
105
106 /*
107 * There is a board feature with the current SH4-202 MicroDev in
108 * that the 2 byte enables (nBE0 and nBE1) are tied together (and
109 * to the Chip Select Line (Ethernet_CS)). Due to this conectivity,
110 * it is not possible to safely perform 8-bit writes to the
111 * Ethernet registers, as 16-bits will be consumed from the Data
112 * lines (corrupting the other byte). Hence, this function is
113 * written to impliment 16-bit read/modify/write for all byte-wide
114 * acceses.
115 *
116 * Note: there is no problem with byte READS (even or odd).
117 *
118 * Sean McGoogan - 16th June 2003.
119 */
120 if ((port >= IO_LAN91C111_BASE) &&
121 (port < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
122 /*
123 * Then are trying to perform a byte-write to the
124 * LAN91C111. This needs special care.
125 */
126 if (port % 2 == 1) { /* is the port odd ? */
127 /* unset bit-0, i.e. make even */
128 const unsigned long evenPort = port-1;
129 unsigned short word;
130
131 /*
132 * do a 16-bit read/write to write to 'port',
133 * preserving even byte.
134 *
135 * Even addresses are bits 0-7
136 * Odd addresses are bits 8-15
137 */
138 word = microdev_inw(evenPort);
139 word = (word & 0xffu) | (b << 8);
140 microdev_outw(word, evenPort);
141 } else {
142 /* else, we are trying to do an even byte write */
143 unsigned short word;
144
145 /*
146 * do a 16-bit read/write to write to 'port',
147 * preserving odd byte.
148 *
149 * Even addresses are bits 0-7
150 * Odd addresses are bits 8-15
151 */
152 word = microdev_inw(port);
153 word = (word & 0xff00u) | (b);
154 microdev_outw(word, port);
155 }
156 } else {
157 *(volatile unsigned char*)PORT2ADDR(port) = b;
158 }
159}
160
161void microdev_outw(unsigned short b, unsigned long port)
162{
163#ifdef CONFIG_PCI
164 if (port >= PCIBIOS_MIN_IO) {
165 microdev_pci_outw(b, port);
166 return;
167 }
168#endif
169 *(volatile unsigned short*)PORT2ADDR(port) = b;
170}
171
172void microdev_outl(unsigned int b, unsigned long port)
173{
174#ifdef CONFIG_PCI
175 if (port >= PCIBIOS_MIN_IO) {
176 microdev_pci_outl(b, port);
177 return;
178 }
179#endif
180 *(volatile unsigned int*)PORT2ADDR(port) = b;
181}
182
183unsigned char microdev_inb_p(unsigned long port)
184{
185 unsigned char v = microdev_inb(port);
186 delay();
187 return v;
188}
189
190unsigned short microdev_inw_p(unsigned long port)
191{
192 unsigned short v = microdev_inw(port);
193 delay();
194 return v;
195}
196
197unsigned int microdev_inl_p(unsigned long port)
198{
199 unsigned int v = microdev_inl(port);
200 delay();
201 return v;
202}
203
204void microdev_outb_p(unsigned char b, unsigned long port)
205{
206 microdev_outb(b, port);
207 delay();
208}
209
210void microdev_outw_p(unsigned short b, unsigned long port)
211{
212 microdev_outw(b, port);
213 delay();
214}
215
216void microdev_outl_p(unsigned int b, unsigned long port)
217{
218 microdev_outl(b, port);
219 delay();
220}
221
222void microdev_insb(unsigned long port, void *buffer, unsigned long count)
223{
224 volatile unsigned char *port_addr;
225 unsigned char *buf = buffer;
226
227 port_addr = (volatile unsigned char *)PORT2ADDR(port);
228
229 while (count--)
230 *buf++ = *port_addr;
231}
232
233void microdev_insw(unsigned long port, void *buffer, unsigned long count)
234{
235 volatile unsigned short *port_addr;
236 unsigned short *buf = buffer;
237
238 port_addr = (volatile unsigned short *)PORT2ADDR(port);
239
240 while (count--)
241 *buf++ = *port_addr;
242}
243
244void microdev_insl(unsigned long port, void *buffer, unsigned long count)
245{
246 volatile unsigned long *port_addr;
247 unsigned int *buf = buffer;
248
249 port_addr = (volatile unsigned long *)PORT2ADDR(port);
250
251 while (count--)
252 *buf++ = *port_addr;
253}
254
255void microdev_outsb(unsigned long port, const void *buffer, unsigned long count)
256{
257 volatile unsigned char *port_addr;
258 const unsigned char *buf = buffer;
259
260 port_addr = (volatile unsigned char *)PORT2ADDR(port);
261
262 while (count--)
263 *port_addr = *buf++;
264}
265
266void microdev_outsw(unsigned long port, const void *buffer, unsigned long count)
267{
268 volatile unsigned short *port_addr;
269 const unsigned short *buf = buffer;
270
271 port_addr = (volatile unsigned short *)PORT2ADDR(port);
272
273 while (count--)
274 *port_addr = *buf++;
275}
276
277void microdev_outsl(unsigned long port, const void *buffer, unsigned long count)
278{
279 volatile unsigned long *port_addr;
280 const unsigned int *buf = buffer;
281
282 port_addr = (volatile unsigned long *)PORT2ADDR(port);
283
284 while (count--)
285 *port_addr = *buf++;
286}
287
288/*
289 * map I/O ports to memory-mapped addresses
290 */
291unsigned long microdev_isa_port2addr(unsigned long offset)
292{
293 unsigned long result;
294
295 if ((offset >= IO_LAN91C111_BASE) &&
296 (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
297 /*
298 * SMSC LAN91C111 Ethernet chip
299 */
300 result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE;
301 } else if ((offset >= IO_SUPERIO_BASE) &&
302 (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) {
303 /*
304 * SMSC FDC37C93xAPM SuperIO chip
305 *
306 * Configuration Registers
307 */
308 result = IO_SUPERIO_PHYS + (offset << 1);
309#if 0
310 } else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG ||
311 offset == KBD_STATUS_REG) {
312 /*
313 * SMSC FDC37C93xAPM SuperIO chip
314 *
315 * PS/2 Keyboard + Mouse (ports 0x60 and 0x64).
316 */
317 result = IO_SUPERIO_PHYS + (offset << 1);
318#endif
319 } else if (((offset >= IO_IDE1_BASE) &&
320 (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) ||
321 (offset == IO_IDE1_MISC)) {
322 /*
323 * SMSC FDC37C93xAPM SuperIO chip
324 *
325 * IDE #1
326 */
327 result = IO_SUPERIO_PHYS + (offset << 1);
328 } else if (((offset >= IO_IDE2_BASE) &&
329 (offset < IO_IDE2_BASE + IO_IDE_EXTENT)) ||
330 (offset == IO_IDE2_MISC)) {
331 /*
332 * SMSC FDC37C93xAPM SuperIO chip
333 *
334 * IDE #2
335 */
336 result = IO_SUPERIO_PHYS + (offset << 1);
337 } else if ((offset >= IO_SERIAL1_BASE) &&
338 (offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) {
339 /*
340 * SMSC FDC37C93xAPM SuperIO chip
341 *
342 * Serial #1
343 */
344 result = IO_SUPERIO_PHYS + (offset << 1);
345 } else if ((offset >= IO_SERIAL2_BASE) &&
346 (offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) {
347 /*
348 * SMSC FDC37C93xAPM SuperIO chip
349 *
350 * Serial #2
351 */
352 result = IO_SUPERIO_PHYS + (offset << 1);
353 } else if ((offset >= IO_ISP1161_BASE) &&
354 (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) {
355 /*
356 * Philips USB ISP1161x chip
357 */
358 result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE;
359 } else {
360 /*
361 * safe default.
362 */
363 printk("Warning: unexpected port in %s( offset = 0x%lx )\n",
364 __FUNCTION__, offset);
365 result = PVR;
366 }
367
368 return result;
369}
370
diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/superh/microdev/irq.c
new file mode 100644
index 000000000000..1298883eca4b
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/irq.c
@@ -0,0 +1,200 @@
1/*
2 * arch/sh/boards/superh/microdev/irq.c
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 *
6 * SuperH SH4-202 MicroDev board support.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15
16#include <asm/system.h>
17#include <asm/io.h>
18#include <asm/mach/irq.h>
19
20#define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */
21
22
23static const struct {
24 unsigned char fpgaIrq;
25 unsigned char mapped;
26 const char *name;
27} fpgaIrqTable[NUM_EXTERNAL_IRQS] = {
28 { 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */
29 { MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */
30 { MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */
31 { MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */
32 { MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */
33 { 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */
34 { 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */
35 { MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */
36 { MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */
37 { MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */
38 { MICRODEV_IRQ_PCI_INTC, 1, "PCI INTC" }, /* IRQ #10 IRL=5 0x340 */
39 { MICRODEV_IRQ_PCI_INTD, 1, "PCI INTD" }, /* IRQ #11 IRL=4 0x360 */
40 { MICRODEV_FPGA_IRQ_MOUSE, 1, "mouse" }, /* IRQ #12 IRL=3 0x380 */
41 { MICRODEV_FPGA_IRQ_IDE2, 1, "IDE #2" }, /* IRQ #13 IRL=2 0x3a0 */
42 { MICRODEV_FPGA_IRQ_IDE1, 1, "IDE #1" }, /* IRQ #14 IRL=1 0x3c0 */
43 { 0, 0, "unused" }, /* IRQ #15 IRL=0 0x3e0 */
44};
45
46#if (MICRODEV_LINUX_IRQ_KEYBOARD != 1)
47# error Inconsistancy in defining the IRQ# for Keyboard!
48#endif
49
50#if (MICRODEV_LINUX_IRQ_ETHERNET != 3)
51# error Inconsistancy in defining the IRQ# for Ethernet!
52#endif
53
54#if (MICRODEV_LINUX_IRQ_USB_HC != 7)
55# error Inconsistancy in defining the IRQ# for USB!
56#endif
57
58#if (MICRODEV_LINUX_IRQ_MOUSE != 12)
59# error Inconsistancy in defining the IRQ# for PS/2 Mouse!
60#endif
61
62#if (MICRODEV_LINUX_IRQ_IDE2 != 13)
63# error Inconsistancy in defining the IRQ# for secondary IDE!
64#endif
65
66#if (MICRODEV_LINUX_IRQ_IDE1 != 14)
67# error Inconsistancy in defining the IRQ# for primary IDE!
68#endif
69
70static void enable_microdev_irq(unsigned int irq);
71static void disable_microdev_irq(unsigned int irq);
72
73 /* shutdown is same as "disable" */
74#define shutdown_microdev_irq disable_microdev_irq
75
76static void mask_and_ack_microdev(unsigned int);
77static void end_microdev_irq(unsigned int irq);
78
79static unsigned int startup_microdev_irq(unsigned int irq)
80{
81 enable_microdev_irq(irq);
82 return 0; /* never anything pending */
83}
84
85static struct hw_interrupt_type microdev_irq_type = {
86 "MicroDev-IRQ",
87 startup_microdev_irq,
88 shutdown_microdev_irq,
89 enable_microdev_irq,
90 disable_microdev_irq,
91 mask_and_ack_microdev,
92 end_microdev_irq
93};
94
95static void disable_microdev_irq(unsigned int irq)
96{
97 unsigned int flags;
98 unsigned int fpgaIrq;
99
100 if (irq >= NUM_EXTERNAL_IRQS) return;
101 if (!fpgaIrqTable[irq].mapped) return;
102
103 fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
104
105 /* disable interrupts */
106 local_irq_save(flags);
107
108 /* disable interupts on the FPGA INTC register */
109 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
110
111 /* restore interrupts */
112 local_irq_restore(flags);
113}
114
115static void enable_microdev_irq(unsigned int irq)
116{
117 unsigned long priorityReg, priorities, pri;
118 unsigned int flags;
119 unsigned int fpgaIrq;
120
121
122 if (irq >= NUM_EXTERNAL_IRQS) return;
123 if (!fpgaIrqTable[irq].mapped) return;
124
125 pri = 15 - irq;
126
127 fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
128 priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
129
130 /* disable interrupts */
131 local_irq_save(flags);
132
133 /* set priority for the interrupt */
134 priorities = ctrl_inl(priorityReg);
135 priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
136 priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
137 ctrl_outl(priorities, priorityReg);
138
139 /* enable interupts on the FPGA INTC register */
140 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
141
142 /* restore interrupts */
143 local_irq_restore(flags);
144}
145
146 /* This functions sets the desired irq handler to be a MicroDev type */
147static void __init make_microdev_irq(unsigned int irq)
148{
149 disable_irq_nosync(irq);
150 irq_desc[irq].handler = &microdev_irq_type;
151 disable_microdev_irq(irq);
152}
153
154static void mask_and_ack_microdev(unsigned int irq)
155{
156 disable_microdev_irq(irq);
157}
158
159static void end_microdev_irq(unsigned int irq)
160{
161 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
162 {
163 enable_microdev_irq(irq);
164 }
165}
166
167extern void __init init_microdev_irq(void)
168{
169 int i;
170
171 /* disable interupts on the FPGA INTC register */
172 ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
173
174 for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
175 {
176 make_microdev_irq(i);
177 }
178}
179
180extern void microdev_print_fpga_intc_status(void)
181{
182 volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG;
183 volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG;
184 volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0);
185 volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8);
186 volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16);
187 volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24);
188 volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG;
189 volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG;
190
191 printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n");
192 printk("FPGA_INTENB = 0x%08x\n", *intenb);
193 printk("FPGA_INTDSB = 0x%08x\n", *intdsb);
194 printk("FPGA_INTSRC = 0x%08x\n", *intsrc);
195 printk("FPGA_INTREQ = 0x%08x\n", *intreq);
196 printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
197 printk("-------------------------------------------------------------------------------\n");
198}
199
200
diff --git a/arch/sh/boards/superh/microdev/led.c b/arch/sh/boards/superh/microdev/led.c
new file mode 100644
index 000000000000..52a98e69d3f0
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/led.c
@@ -0,0 +1,102 @@
1/*
2 * linux/arch/sh/kernel/led_microdev.c
3 *
4 * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com>
5 * Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com)
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 */
11
12#include <linux/config.h>
13#include <asm/io.h>
14
15#define LED_REGISTER 0xa6104d20
16
17static void mach_led_d9(int value)
18{
19 unsigned long reg;
20 reg = ctrl_inl(LED_REGISTER);
21 reg &= ~1;
22 reg |= (value & 1);
23 ctrl_outl(reg, LED_REGISTER);
24 return;
25}
26
27static void mach_led_d10(int value)
28{
29 unsigned long reg;
30 reg = ctrl_inl(LED_REGISTER);
31 reg &= ~2;
32 reg |= ((value & 1) << 1);
33 ctrl_outl(reg, LED_REGISTER);
34 return;
35}
36
37
38#ifdef CONFIG_HEARTBEAT
39#include <linux/sched.h>
40
41static unsigned char banner_table[] = {
42 0x11, 0x01, 0x11, 0x01, 0x11, 0x03,
43 0x11, 0x01, 0x11, 0x01, 0x13, 0x03,
44 0x11, 0x01, 0x13, 0x01, 0x13, 0x01, 0x11, 0x03,
45 0x11, 0x03,
46 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
47 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x07,
48 0x13, 0x01, 0x13, 0x03,
49 0x11, 0x01, 0x11, 0x03,
50 0x13, 0x01, 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
51 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
52 0x13, 0x01, 0x13, 0x01, 0x13, 0x03,
53 0x13, 0x01, 0x11, 0x01, 0x11, 0x03,
54 0x11, 0x03,
55 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x13, 0x07,
56 0xff
57};
58
59static void banner(void)
60{
61 static int pos = 0;
62 static int count = 0;
63
64 if (count) {
65 count--;
66 } else {
67 int val = banner_table[pos];
68 if (val == 0xff) {
69 pos = 0;
70 val = banner_table[pos];
71 }
72 pos++;
73 mach_led_d10((val >> 4) & 1);
74 count = 10 * (val & 0xf);
75 }
76}
77
78/* From heartbeat_harp in the stboards directory */
79/* acts like an actual heart beat -- ie thump-thump-pause... */
80void microdev_heartbeat(void)
81{
82 static unsigned cnt = 0, period = 0, dist = 0;
83
84 if (cnt == 0 || cnt == dist)
85 mach_led_d9(1);
86 else if (cnt == 7 || cnt == dist+7)
87 mach_led_d9(0);
88
89 if (++cnt > period) {
90 cnt = 0;
91 /* The hyperbolic function below modifies the heartbeat period
92 * length in dependency of the current (5min) load. It goes
93 * through the points f(0)=126, f(1)=86, f(5)=51,
94 * f(inf)->30. */
95 period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
96 dist = period / 4;
97 }
98
99 banner();
100}
101
102#endif
diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c
new file mode 100644
index 000000000000..c18919941ec0
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/setup.c
@@ -0,0 +1,278 @@
1/*
2 * arch/sh/boards/superh/microdev/setup.c
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 * Copyright (C) 2003, 2004 SuperH, Inc.
6 * Copyright (C) 2004 Paul Mundt
7 *
8 * SuperH SH4-202 MicroDev board support.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/ioport.h>
18#include <asm/io.h>
19#include <asm/mach/irq.h>
20#include <asm/mach/io.h>
21#include <asm/machvec.h>
22#include <asm/machvec_init.h>
23
24extern void microdev_heartbeat(void);
25
26/*
27 * The Machine Vector
28 */
29
30struct sh_machine_vector mv_sh4202_microdev __initmv = {
31 .mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */
32
33 .mv_inb = microdev_inb,
34 .mv_inw = microdev_inw,
35 .mv_inl = microdev_inl,
36 .mv_outb = microdev_outb,
37 .mv_outw = microdev_outw,
38 .mv_outl = microdev_outl,
39
40 .mv_inb_p = microdev_inb_p,
41 .mv_inw_p = microdev_inw_p,
42 .mv_inl_p = microdev_inl_p,
43 .mv_outb_p = microdev_outb_p,
44 .mv_outw_p = microdev_outw_p,
45 .mv_outl_p = microdev_outl_p,
46
47 .mv_insb = microdev_insb,
48 .mv_insw = microdev_insw,
49 .mv_insl = microdev_insl,
50 .mv_outsb = microdev_outsb,
51 .mv_outsw = microdev_outsw,
52 .mv_outsl = microdev_outsl,
53
54 .mv_isa_port2addr = microdev_isa_port2addr,
55
56 .mv_init_irq = init_microdev_irq,
57
58#ifdef CONFIG_HEARTBEAT
59 .mv_heartbeat = microdev_heartbeat,
60#endif
61};
62ALIAS_MV(sh4202_microdev)
63
64/****************************************************************************/
65
66
67 /*
68 * Setup for the SMSC FDC37C93xAPM
69 */
70#define SMSC_CONFIG_PORT_ADDR (0x3F0)
71#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
72#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
73
74#define SMSC_ENTER_CONFIG_KEY 0x55
75#define SMSC_EXIT_CONFIG_KEY 0xaa
76
77#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
78#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
79#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
80#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
81#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
82#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
83#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
84#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
85#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
86#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
87
88#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
89#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
90#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
91#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
92#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
93#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
94#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
95
96#define SMSC_READ_INDEXED(index) ({ \
97 outb((index), SMSC_INDEX_PORT_ADDR); \
98 inb(SMSC_DATA_PORT_ADDR); })
99#define SMSC_WRITE_INDEXED(val, index) ({ \
100 outb((index), SMSC_INDEX_PORT_ADDR); \
101 outb((val), SMSC_DATA_PORT_ADDR); })
102
103#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
104#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
105#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
106#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
107
108#define SERIAL1_PRIMARY_BASE 0x03f8
109#define SERIAL2_PRIMARY_BASE 0x02f8
110
111#define MSB(x) ( (x) >> 8 )
112#define LSB(x) ( (x) & 0xff )
113
114 /* General-Purpose base address on CPU-board FPGA */
115#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
116
117 /* assume a Keyboard Controller is present */
118int microdev_kbd_controller_present = 1;
119
120const char *get_system_type(void)
121{
122 return "SH4-202 MicroDev";
123}
124
125static struct resource smc91x_resources[] = {
126 [0] = {
127 .start = 0x300,
128 .end = 0x300 + 0x0001000 - 1,
129 .flags = IORESOURCE_MEM,
130 },
131 [1] = {
132 .start = MICRODEV_LINUX_IRQ_ETHERNET,
133 .end = MICRODEV_LINUX_IRQ_ETHERNET,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device smc91x_device = {
139 .name = "smc91x",
140 .id = -1,
141 .num_resources = ARRAY_SIZE(smc91x_resources),
142 .resource = smc91x_resources,
143};
144
145static int __init smc91x_setup(void)
146{
147 return platform_device_register(&smc91x_device);
148}
149
150__initcall(smc91x_setup);
151
152 /*
153 * Initialize the board
154 */
155void __init platform_setup(void)
156{
157 int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
158 const int fpgaRevision = *fpgaRevisionRegister;
159 int * const CacheControlRegister = (int*)CCR;
160
161 printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n",
162 get_system_type(), fpgaRevision, *CacheControlRegister);
163}
164
165
166/****************************************************************************/
167
168
169 /*
170 * Setup for the SMSC FDC37C93xAPM
171 */
172static int __init smsc_superio_setup(void)
173{
174
175 unsigned char devid, devrev;
176
177 /* Initially the chip is in run state */
178 /* Put it into configuration state */
179 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
180
181 /* Read device ID info */
182 devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
183 devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
184 if ( (devid==0x30) && (devrev==0x01) )
185 {
186 printk("SMSC FDC37C93xAPM SuperIO device detected\n");
187 }
188 else
189 { /* not the device identity we expected */
190 printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n",
191 devid, devrev);
192 /* inform the keyboard driver that we have no keyboard controller */
193 microdev_kbd_controller_present = 0;
194 /* little point in doing anything else in this functon */
195 return 0;
196 }
197
198 /* Select the keyboard device */
199 SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
200 /* enable it */
201 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
202 /* enable the interrupts */
203 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
204 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
205
206 /* Select the Serial #1 device */
207 SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
208 /* enable it */
209 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
210 /* program with port addresses */
211 SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
212 SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
213 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
214 /* enable the interrupts */
215 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
216
217 /* Select the Serial #2 device */
218 SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
219 /* enable it */
220 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
221 /* program with port addresses */
222 SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
223 SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
224 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
225 /* enable the interrupts */
226 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
227
228 /* Select the IDE#1 device */
229 SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
230 /* enable it */
231 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
232 /* program with port addresses */
233 SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
234 SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
235 SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
236 SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
237 SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
238 SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
239 /* select the interrupt */
240 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
241
242 /* Select the IDE#2 device */
243 SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
244 /* enable it */
245 SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
246 /* program with port addresses */
247 SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
248 SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
249 SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
250 SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
251 /* select the interrupt */
252 SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
253
254 /* Select the configuration registers */
255 SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
256 /* enable the appropriate GPIO pins for IDE functionality:
257 * bit[0] In/Out 1==input; 0==output
258 * bit[1] Polarity 1==invert; 0==no invert
259 * bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
260 * bit[3:4] Function Select 00==original; 01==Alternate Function #1
261 */
262 SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
263 SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
264 SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
265 SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
266 SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
267
268 /* Exit the configuraton state */
269 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
270
271 return 0;
272}
273
274
275/* This is grotty, but, because kernel is always referenced on the link line
276 * before any devices, this is safe.
277 */
278__initcall(smsc_superio_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 21:06:56 -0500