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-rw-r--r--arch/sh/boards/superh/microdev/setup.c166
1 files changed, 154 insertions, 12 deletions
diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c
index 1c1d65fb12df..892b14d31405 100644
--- a/arch/sh/boards/superh/microdev/setup.c
+++ b/arch/sh/boards/superh/microdev/setup.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 * Copyright (C) 2003, 2004 SuperH, Inc. 5 * Copyright (C) 2003, 2004 SuperH, Inc.
6 * Copyright (C) 2004 Paul Mundt 6 * Copyright (C) 2004, 2005 Paul Mundt
7 * 7 *
8 * SuperH SH4-202 MicroDev board support. 8 * SuperH SH4-202 MicroDev board support.
9 * 9 *
@@ -15,11 +15,10 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/ioport.h> 17#include <linux/ioport.h>
18#include <video/s1d13xxxfb.h>
19#include <asm/microdev.h>
18#include <asm/io.h> 20#include <asm/io.h>
19#include <asm/mach/irq.h>
20#include <asm/mach/io.h>
21#include <asm/machvec.h> 21#include <asm/machvec.h>
22#include <asm/machvec_init.h>
23 22
24extern void microdev_heartbeat(void); 23extern void microdev_heartbeat(void);
25 24
@@ -51,8 +50,6 @@ struct sh_machine_vector mv_sh4202_microdev __initmv = {
51 .mv_outsw = microdev_outsw, 50 .mv_outsw = microdev_outsw,
52 .mv_outsl = microdev_outsl, 51 .mv_outsl = microdev_outsl,
53 52
54 .mv_isa_port2addr = microdev_isa_port2addr,
55
56 .mv_init_irq = init_microdev_irq, 53 .mv_init_irq = init_microdev_irq,
57 54
58#ifdef CONFIG_HEARTBEAT 55#ifdef CONFIG_HEARTBEAT
@@ -142,16 +139,161 @@ static struct platform_device smc91x_device = {
142 .resource = smc91x_resources, 139 .resource = smc91x_resources,
143}; 140};
144 141
145static int __init smc91x_setup(void) 142#ifdef CONFIG_FB_S1D13XXX
143static struct s1d13xxxfb_regval s1d13806_initregs[] = {
144 { S1DREG_MISC, 0x00 },
145 { S1DREG_COM_DISP_MODE, 0x00 },
146 { S1DREG_GPIO_CNF0, 0x00 },
147 { S1DREG_GPIO_CNF1, 0x00 },
148 { S1DREG_GPIO_CTL0, 0x00 },
149 { S1DREG_GPIO_CTL1, 0x00 },
150 { S1DREG_CLK_CNF, 0x02 },
151 { S1DREG_LCD_CLK_CNF, 0x01 },
152 { S1DREG_CRT_CLK_CNF, 0x03 },
153 { S1DREG_MPLUG_CLK_CNF, 0x03 },
154 { S1DREG_CPU2MEM_WST_SEL, 0x02 },
155 { S1DREG_SDRAM_REF_RATE, 0x03 },
156 { S1DREG_SDRAM_TC0, 0x00 },
157 { S1DREG_SDRAM_TC1, 0x01 },
158 { S1DREG_MEM_CNF, 0x80 },
159 { S1DREG_PANEL_TYPE, 0x25 },
160 { S1DREG_MOD_RATE, 0x00 },
161 { S1DREG_LCD_DISP_HWIDTH, 0x63 },
162 { S1DREG_LCD_NDISP_HPER, 0x1e },
163 { S1DREG_TFT_FPLINE_START, 0x06 },
164 { S1DREG_TFT_FPLINE_PWIDTH, 0x03 },
165 { S1DREG_LCD_DISP_VHEIGHT0, 0x57 },
166 { S1DREG_LCD_DISP_VHEIGHT1, 0x02 },
167 { S1DREG_LCD_NDISP_VPER, 0x00 },
168 { S1DREG_TFT_FPFRAME_START, 0x0a },
169 { S1DREG_TFT_FPFRAME_PWIDTH, 0x81 },
170 { S1DREG_LCD_DISP_MODE, 0x03 },
171 { S1DREG_LCD_MISC, 0x00 },
172 { S1DREG_LCD_DISP_START0, 0x00 },
173 { S1DREG_LCD_DISP_START1, 0x00 },
174 { S1DREG_LCD_DISP_START2, 0x00 },
175 { S1DREG_LCD_MEM_OFF0, 0x90 },
176 { S1DREG_LCD_MEM_OFF1, 0x01 },
177 { S1DREG_LCD_PIX_PAN, 0x00 },
178 { S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
179 { S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
180 { S1DREG_CRT_DISP_HWIDTH, 0x63 },
181 { S1DREG_CRT_NDISP_HPER, 0x1f },
182 { S1DREG_CRT_HRTC_START, 0x04 },
183 { S1DREG_CRT_HRTC_PWIDTH, 0x8f },
184 { S1DREG_CRT_DISP_VHEIGHT0, 0x57 },
185 { S1DREG_CRT_DISP_VHEIGHT1, 0x02 },
186 { S1DREG_CRT_NDISP_VPER, 0x1b },
187 { S1DREG_CRT_VRTC_START, 0x00 },
188 { S1DREG_CRT_VRTC_PWIDTH, 0x83 },
189 { S1DREG_TV_OUT_CTL, 0x10 },
190 { S1DREG_CRT_DISP_MODE, 0x05 },
191 { S1DREG_CRT_DISP_START0, 0x00 },
192 { S1DREG_CRT_DISP_START1, 0x00 },
193 { S1DREG_CRT_DISP_START2, 0x00 },
194 { S1DREG_CRT_MEM_OFF0, 0x20 },
195 { S1DREG_CRT_MEM_OFF1, 0x03 },
196 { S1DREG_CRT_PIX_PAN, 0x00 },
197 { S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
198 { S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
199 { S1DREG_LCD_CUR_CTL, 0x00 },
200 { S1DREG_LCD_CUR_START, 0x01 },
201 { S1DREG_LCD_CUR_XPOS0, 0x00 },
202 { S1DREG_LCD_CUR_XPOS1, 0x00 },
203 { S1DREG_LCD_CUR_YPOS0, 0x00 },
204 { S1DREG_LCD_CUR_YPOS1, 0x00 },
205 { S1DREG_LCD_CUR_BCTL0, 0x00 },
206 { S1DREG_LCD_CUR_GCTL0, 0x00 },
207 { S1DREG_LCD_CUR_RCTL0, 0x00 },
208 { S1DREG_LCD_CUR_BCTL1, 0x1f },
209 { S1DREG_LCD_CUR_GCTL1, 0x3f },
210 { S1DREG_LCD_CUR_RCTL1, 0x1f },
211 { S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
212 { S1DREG_CRT_CUR_CTL, 0x00 },
213 { S1DREG_CRT_CUR_START, 0x01 },
214 { S1DREG_CRT_CUR_XPOS0, 0x00 },
215 { S1DREG_CRT_CUR_XPOS1, 0x00 },
216 { S1DREG_CRT_CUR_YPOS0, 0x00 },
217 { S1DREG_CRT_CUR_YPOS1, 0x00 },
218 { S1DREG_CRT_CUR_BCTL0, 0x00 },
219 { S1DREG_CRT_CUR_GCTL0, 0x00 },
220 { S1DREG_CRT_CUR_RCTL0, 0x00 },
221 { S1DREG_CRT_CUR_BCTL1, 0x1f },
222 { S1DREG_CRT_CUR_GCTL1, 0x3f },
223 { S1DREG_CRT_CUR_RCTL1, 0x1f },
224 { S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
225 { S1DREG_BBLT_CTL0, 0x00 },
226 { S1DREG_BBLT_CTL1, 0x00 },
227 { S1DREG_BBLT_CC_EXP, 0x00 },
228 { S1DREG_BBLT_OP, 0x00 },
229 { S1DREG_BBLT_SRC_START0, 0x00 },
230 { S1DREG_BBLT_SRC_START1, 0x00 },
231 { S1DREG_BBLT_SRC_START2, 0x00 },
232 { S1DREG_BBLT_DST_START0, 0x00 },
233 { S1DREG_BBLT_DST_START1, 0x00 },
234 { S1DREG_BBLT_DST_START2, 0x00 },
235 { S1DREG_BBLT_MEM_OFF0, 0x00 },
236 { S1DREG_BBLT_MEM_OFF1, 0x00 },
237 { S1DREG_BBLT_WIDTH0, 0x00 },
238 { S1DREG_BBLT_WIDTH1, 0x00 },
239 { S1DREG_BBLT_HEIGHT0, 0x00 },
240 { S1DREG_BBLT_HEIGHT1, 0x00 },
241 { S1DREG_BBLT_BGC0, 0x00 },
242 { S1DREG_BBLT_BGC1, 0x00 },
243 { S1DREG_BBLT_FGC0, 0x00 },
244 { S1DREG_BBLT_FGC1, 0x00 },
245 { S1DREG_LKUP_MODE, 0x00 },
246 { S1DREG_LKUP_ADDR, 0x00 },
247 { S1DREG_PS_CNF, 0x10 },
248 { S1DREG_PS_STATUS, 0x00 },
249 { S1DREG_CPU2MEM_WDOGT, 0x00 },
250 { S1DREG_COM_DISP_MODE, 0x02 },
251};
252
253static struct s1d13xxxfb_pdata s1d13806_platform_data = {
254 .initregs = s1d13806_initregs,
255 .initregssize = ARRAY_SIZE(s1d13806_initregs),
256};
257
258static struct resource s1d13806_resources[] = {
259 [0] = {
260 .start = 0x07200000,
261 .end = 0x07200000 + 0x00200000 - 1,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .start = 0x07000000,
266 .end = 0x07000000 + 0x00200000 - 1,
267 .flags = IORESOURCE_MEM,
268 },
269};
270
271static struct platform_device s1d13806_device = {
272 .name = "s1d13806fb",
273 .id = -1,
274 .num_resources = ARRAY_SIZE(s1d13806_resources),
275 .resource = s1d13806_resources,
276
277 .dev = {
278 .platform_data = &s1d13806_platform_data,
279 },
280};
281#endif
282
283static struct platform_device *microdev_devices[] __initdata = {
284 &smc91x_device,
285#ifdef CONFIG_FB_S1D13XXX
286 &s1d13806_device,
287#endif
288};
289
290static int __init microdev_devices_setup(void)
146{ 291{
147 return platform_device_register(&smc91x_device); 292 return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
148} 293}
149 294
150__initcall(smc91x_setup); 295__initcall(microdev_devices_setup);
151 296
152 /*
153 * Initialize the board
154 */
155void __init platform_setup(void) 297void __init platform_setup(void)
156{ 298{
157 int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul); 299 int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
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