diff options
Diffstat (limited to 'arch/sh/boards/se/7722/irq.c')
-rw-r--r-- | arch/sh/boards/se/7722/irq.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/sh/boards/se/7722/irq.c b/arch/sh/boards/se/7722/irq.c index 099e5deb77f8..26cff0efda40 100644 --- a/arch/sh/boards/se/7722/irq.c +++ b/arch/sh/boards/se/7722/irq.c | |||
@@ -19,15 +19,24 @@ | |||
19 | #define INTC_INTMSK0 0xFFD00044 | 19 | #define INTC_INTMSK0 0xFFD00044 |
20 | #define INTC_INTMSKCLR0 0xFFD00064 | 20 | #define INTC_INTMSKCLR0 0xFFD00064 |
21 | 21 | ||
22 | struct se7722_data { | ||
23 | unsigned char irq; | ||
24 | unsigned char ipr_idx; | ||
25 | unsigned char shift; | ||
26 | unsigned short priority; | ||
27 | unsigned long addr; | ||
28 | }; | ||
29 | |||
30 | |||
22 | static void disable_se7722_irq(unsigned int irq) | 31 | static void disable_se7722_irq(unsigned int irq) |
23 | { | 32 | { |
24 | struct ipr_data *p = get_irq_chip_data(irq); | 33 | struct se7722_data *p = get_irq_chip_data(irq); |
25 | ctrl_outw( ctrl_inw( p->addr ) | p->priority , p->addr ); | 34 | ctrl_outw( ctrl_inw( p->addr ) | p->priority , p->addr ); |
26 | } | 35 | } |
27 | 36 | ||
28 | static void enable_se7722_irq(unsigned int irq) | 37 | static void enable_se7722_irq(unsigned int irq) |
29 | { | 38 | { |
30 | struct ipr_data *p = get_irq_chip_data(irq); | 39 | struct se7722_data *p = get_irq_chip_data(irq); |
31 | ctrl_outw( ctrl_inw( p->addr ) & ~p->priority , p->addr ); | 40 | ctrl_outw( ctrl_inw( p->addr ) & ~p->priority , p->addr ); |
32 | } | 41 | } |
33 | 42 | ||
@@ -38,7 +47,7 @@ static struct irq_chip se7722_irq_chip __read_mostly = { | |||
38 | .mask_ack = disable_se7722_irq, | 47 | .mask_ack = disable_se7722_irq, |
39 | }; | 48 | }; |
40 | 49 | ||
41 | static struct ipr_data ipr_irq_table[] = { | 50 | static struct se7722_data ipr_irq_table[] = { |
42 | /* irq ,idx,sft, priority , addr */ | 51 | /* irq ,idx,sft, priority , addr */ |
43 | { MRSHPC_IRQ0 , 0 , 0 , MRSHPC_BIT0 , IRQ01_MASK } , | 52 | { MRSHPC_IRQ0 , 0 , 0 , MRSHPC_BIT0 , IRQ01_MASK } , |
44 | { MRSHPC_IRQ1 , 0 , 0 , MRSHPC_BIT1 , IRQ01_MASK } , | 53 | { MRSHPC_IRQ1 , 0 , 0 , MRSHPC_BIT1 , IRQ01_MASK } , |