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Diffstat (limited to 'arch/sh/boards/se/73180/irq.c')
-rw-r--r--arch/sh/boards/se/73180/irq.c47
1 files changed, 28 insertions, 19 deletions
diff --git a/arch/sh/boards/se/73180/irq.c b/arch/sh/boards/se/73180/irq.c
index 2c62b8ea350e..e7200c56bb45 100644
--- a/arch/sh/boards/se/73180/irq.c
+++ b/arch/sh/boards/se/73180/irq.c
@@ -87,13 +87,38 @@ shmse_irq_demux(int irq)
87 return irq; 87 return irq;
88} 88}
89 89
90static struct ipr_data se73180_siof0_ipr_map[] = {
91 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
92};
93static struct ipr_data se73180_vpu_ipr_map[] = {
94 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
95};
96static struct ipr_data se73180_other_ipr_map[] = {
97 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
98 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
99 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
100 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
101 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
102 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
103 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
104 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
105 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
106
107 /* VIO interrupt */
108 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
109 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
110 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
111
112 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
113};
114
90/* 115/*
91 * Initialize IRQ setting 116 * Initialize IRQ setting
92 */ 117 */
93void __init 118void __init
94init_73180se_IRQ(void) 119init_73180se_IRQ(void)
95{ 120{
96 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 121 make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map));
97 122
98 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ 123 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
99 ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */ 124 ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */
@@ -101,27 +126,11 @@ init_73180se_IRQ(void)
101 ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */ 126 ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */
102 make_intreq_irq(10); 127 make_intreq_irq(10);
103 128
104 make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8); 129 make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map));
105 130
106 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ 131 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
107 132
108 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 133 make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map));
109 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
110 make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
111 make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
112 make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
113 IIC0_PRIORITY);
114 make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
115 IIC0_PRIORITY);
116 make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
117 make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
118 make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
119
120 /* VIO interrupt */
121 make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
122 make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
123 make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
124 134
125 make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
126 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 135 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
127} 136}